diff --git a/hdl/eb_testbench/EB_2_wb_converter.vhd b/hdl/eb_testbench/EB_2_wb_converter.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90e419add7d7bd89c45b99400d7c443e438a0b9a
--- /dev/null
+++ b/hdl/eb_testbench/EB_2_wb_converter.vhd
@@ -0,0 +1,794 @@
+--! @file EB_2_wb_converter.vhd
+--! @brief EtherBone logic core
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+use work.wb32_package.all;
+
+entity eb_2_wb_converter is
+port(
+ clk_i : in std_logic; --! System Clk
+ nRst_i : in std_logic; --! active low sync reset
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i : in wb32_slave_in; --! Streaming wishbone(record) sink from RX transport protocol block
+ EB_RX_o : out wb32_slave_out; --! Streaming WB sink flow control to RX transport protocol block
+
+ EB_TX_i : in wb32_master_in; --! Streaming WB src flow control from TX transport protocol block
+ EB_TX_o : out wb32_master_out; --! Streaming WB src to TX transport protocol block
+
+ byte_count_rx_i : in std_logic_vector(15 downto 0); --! Payload byte length from RX transport protocol block
+
+ --config signals
+ config_master_i : in wb32_master_in; --! WB V4 interface to WB interconnect/device(s)
+ config_master_o : out wb32_master_out; --! WB V4 interface to WB interconnect/device(s)
+
+
+
+ --WB IC signals
+ WB_master_i : in wb32_master_in; --! WB V4 interface to WB interconnect/device(s)
+ WB_master_o : out wb32_master_out --! WB V4 interface to WB interconnect/device(s)
+
+
+
+);
+end eb_2_wb_converter;
+
+architecture behavioral of eb_2_wb_converter is
+
+--Signals
+------------------------------------------------------------------------------------------
+--State Machines
+------------------------------------------------------------------------------------------
+constant c_width_int : integer := 24;
+type t_state_RX is (IDLE, EB_HDR_REC, EB_HDR_PROC, CYC_HDR_REC, CYC_HDR_READ_PROC, CYC_HDR_READ_GET_ADR, WB_READ_RDY, WB_READ, CYC_HDR_WRITE_PROC, CYC_HDR_WRITE_GET_ADR, WB_WRITE_RDY, WB_WRITE, CYC_DONE, EB_DONE, ERROR);
+type t_state_TX is (IDLE, EB_HDR_INIT, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
+
+signal s_state_RX : t_state_RX := IDLE;
+signal s_state_TX : t_state_TX := IDLE;
+
+constant test : std_logic_vector(31 downto 0) := (others => '0');
+
+------------------------------------------------------------------------------------------
+--Wishbone Interfaces
+------------------------------------------------------------------------------------------
+signal s_WB_master_i : wb32_master_in;
+signal s_WB_master_o : wb32_master_out;
+
+signal s_WB_STB : std_logic;
+signal s_WB_ADR : std_logic_vector(WB_master_o.ADR'left downto 0);
+signal s_WB_CYC : std_logic;
+signal s_WB_WE : std_logic;
+signal s_TX_STROBED : std_logic;
+
+signal s_WB_addr_inc : unsigned(c_EB_ADDR_SIZE_n-1 downto 0);
+signal s_WB_addr_cnt : unsigned(c_EB_ADDR_SIZE_n-1 downto 0);
+
+------------------------------------------------------------------------------------------
+-- Byte/Pulse Counters
+------------------------------------------------------------------------------------------
+signal s_WB_ACK_cnt_big : unsigned(8 downto 0);
+alias a_WB_ACK_cnt : unsigned(7 downto 0) is s_WB_ACK_cnt_big(7 downto 0);
+alias a_WB_ACK_cnt_err : unsigned(0 downto 0) is s_WB_ACK_cnt_big(8 downto 8);
+
+signal s_EB_TX_zeropad_cnt : unsigned(7 downto 0);
+signal s_EB_RX_byte_cnt : unsigned(15 downto 0);
+signal s_EB_TX_byte_cnt : unsigned(15 downto 0);
+
+signal debug_stb_cnt : natural := 0;
+signal debug_byte_diff : unsigned(15 downto 0);
+signal debug_diff : std_logic;
+signal debugsum : unsigned(15 downto 0);
+
+------------------------------------------------------------------------------------------
+--Config and Status Regs
+------------------------------------------------------------------------------------------
+signal s_WB_Config_o : wb32_slave_out;
+signal s_WB_Config_i : wb32_slave_in;
+signal s_ADR_CONFIG : std_logic;
+
+signal s_status_en : std_logic;
+signal s_status_clr : std_logic;
+
+------------------------------------------------------------------------------------------
+--Etherbone Signals
+------------------------------------------------------------------------------------------
+signal s_EB_RX_ACK : std_logic;
+signal s_EB_RX_STALL : std_logic;
+signal s_EB_TX_STB : std_logic;
+signal s_packet_reception_complete : std_logic;
+
+signal sink_valid : std_logic;
+
+------------------------------------------------------------------------------------------
+--Etherbone Registers
+------------------------------------------------------------------------------------------
+constant c_WB_WORDSIZE : natural := 32;
+constant c_EB_HDR_LEN : unsigned(3 downto 0):= x"0";
+signal s_EB_TX_base_wr_adr : std_logic_vector(31 downto 0);
+signal s_EB_packet_length : unsigned(15 downto 0);
+
+signal s_EB_RX_HDR : EB_HDR;
+signal s_EB_RX_CUR_CYCLE : EB_CYC;
+signal s_EB_TX_HDR : EB_HDR;
+signal s_EB_TX_CUR_CYCLE : EB_CYC;
+
+------------------------------------------------------------------------------------------
+--Etherbone FIFO Buffers
+------------------------------------------------------------------------------------------
+signal s_tx_fifo_am_full : std_logic;
+signal s_tx_fifo_full : std_logic;
+signal s_tx_fifo_am_empty : std_logic;
+signal s_tx_fifo_empty : std_logic;
+signal s_tx_fifo_data : std_logic_vector(31 downto 0);
+signal s_tx_fifo_rd : std_logic;
+signal s_tx_fifo_clr : std_logic;
+signal s_tx_fifo_we : std_logic;
+signal s_tx_fifo_gauge : std_logic_vector(3 downto 0);
+
+signal s_rx_fifo_am_full : std_logic;
+signal s_rx_fifo_full : std_logic;
+signal s_rx_fifo_am_empty : std_logic;
+signal s_rx_fifo_empty : std_logic;
+signal s_rx_fifo_data : std_logic_vector(31 downto 0);
+signal s_rx_fifo_q : std_logic_vector(31 downto 0);
+signal s_rx_fifo_rd : std_logic;
+signal s_rx_fifo_clr : std_logic;
+signal s_rx_fifo_we : std_logic;
+signal s_rx_fifo_gauge : std_logic_vector(3 downto 0);
+------------------------------------------------------------------------------------------
+
+
+
+
+constant WBM_Zero_o : wb32_master_out := (CYC => '0',
+ STB => '0',
+ ADR => (others => '0'),
+ SEL => (others => '0'),
+ WE => '0',
+ DAT => (others => '0'));
+
+constant WBS_Zero_o : wb32_slave_out := (ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ STALL => '0',
+ DAT => (others => '0'));
+
+component alt_FIFO_am_full_flag IS
+ PORT
+ (
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ sclr : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_empty : OUT STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+ );
+end component alt_FIFO_am_full_flag;
+
+begin
+
+TX_FIFO : alt_FIFO_am_full_flag
+port map(
+ clock => clk_i,
+ data => s_tx_fifo_data,
+ rdreq => s_tx_fifo_rd,
+ sclr => s_tx_fifo_clr,
+ wrreq => s_tx_fifo_we,
+ almost_empty => s_tx_fifo_am_empty,
+ almost_full => s_tx_fifo_am_full,
+ empty => s_tx_fifo_empty,
+ full => s_tx_fifo_full,
+ q => EB_TX_o.DAT,
+ usedw => s_tx_fifo_gauge
+ );
+
+--strobe out as long as there is data left
+EB_TX_o.STB <= NOT s_tx_fifo_empty;
+
+--read data from RX fifo as long as TX interface is free
+s_tx_fifo_rd <= NOT EB_TX_i.STALL;
+
+--write in pending data as long as there is space left
+s_tx_fifo_we <= s_EB_TX_STB AND NOT s_tx_fifo_full;
+
+ RX_FIFO : alt_FIFO_am_full_flag
+port map(
+ clock => clk_i,
+ data => EB_RX_i.DAT,
+ rdreq => s_rx_fifo_rd,
+ sclr => s_rx_fifo_clr,
+ wrreq => s_rx_fifo_we,
+ almost_empty => open,
+ almost_full => s_rx_fifo_am_full,
+ empty => s_rx_fifo_empty,
+ full => s_rx_fifo_full,
+ q => s_rx_fifo_q,
+ usedw => s_rx_fifo_gauge
+ );
+
+--BUG: almost_empty flag is stuck after hitting empty repeatedly.
+--create our own for now
+s_rx_fifo_am_empty <= '1' when unsigned(s_rx_fifo_gauge) <= 1
+ else '0';
+
+--workaround to avoid creation of two drivers for the s_WB_master_o record
+s_WB_master_o.DAT <= s_rx_fifo_q;
+s_WB_master_o.STB <= s_WB_STB;
+
+--when reading, incoming rx data goes on the WB address lines
+s_WB_master_o.ADR <= s_rx_fifo_q when s_state_RX = WB_READ
+ else s_WB_ADR;
+
+s_WB_master_o.CYC <= s_WB_CYC;
+s_WB_master_o.WE <= s_WB_WE;
+EB_RX_o.STALL <= s_rx_fifo_am_full;
+EB_RX_o.ACK <= s_EB_RX_ACK;
+
+s_rx_fifo_we <= EB_RX_i.STB AND NOT (s_rx_fifo_am_full); -- OR s_packet_reception_complete);
+
+
+--MUX lines: WB master / config space master
+---------------------------------
+Mux_WB_Cfg_in : with s_ADR_CONFIG select
+s_WB_master_i <= config_master_i when '1',
+ WB_master_i when others;
+
+-- select WB Master Port Out: Tie to ground / Signal s_WB_master_o
+Mux_WB_out : with s_ADR_CONFIG select
+WB_master_o <= WBM_Zero_o when '1',
+ s_WB_master_o when others;
+
+-- select WB Master Port Out: Tie to ground / Signal s_WB_master_o
+Mux_Cfg_out : with s_ADR_CONFIG select
+config_master_o <= s_WB_master_o when '1',
+ WBM_Zero_o when others;
+-----------------------------------
+
+
+
+
+
+debug_diff <= '1' when debug_byte_diff > 0 else '0';
+
+count_io : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ if (nRST_i = '0') then
+ s_EB_RX_byte_cnt <= (others => '0');
+ s_EB_TX_byte_cnt <= (others => '0');
+ s_WB_ACK_cnt_big <= (others => '0');
+ else
+
+
+ --Counter: RX bytes received
+ if(s_state_RX = IDLE) then
+ s_EB_RX_byte_cnt <= (others => '0');
+ else
+ if(s_rx_fifo_we = '1') then
+ s_EB_RX_byte_cnt <= s_EB_RX_byte_cnt + 4;
+ end if;
+ end if;
+ -- packet reception is not complete if min packet size not reached and < s_EB_packet_length
+ --
+ if((s_EB_RX_byte_cnt < s_EB_packet_length) OR (s_EB_RX_byte_cnt < 16)) then
+ s_packet_reception_complete <= '0';
+ else
+ s_packet_reception_complete <= '1';
+ end if;
+
+ --Counter: WB ACKs received
+ if(s_state_RX = IDLE) then
+ s_WB_ACK_cnt_big <= (others => '0');
+ else
+ if(s_state_RX = CYC_HDR_WRITE_PROC) then
+ a_WB_ACK_cnt <= s_EB_RX_CUR_CYCLE.RD_CNT + s_EB_RX_CUR_CYCLE.WR_CNT;
+ elsif(s_WB_master_i.ACK = '1') then
+ a_WB_ACK_cnt <= a_WB_ACK_cnt -1;
+ end if;
+ end if;
+
+ --Counter: WB ACKs received
+ if(s_state_RX = IDLE) then
+ debug_stb_cnt <= 0;
+ else
+ if(s_state_RX = CYC_HDR_WRITE_PROC) then
+ debug_stb_cnt <= 0;
+ elsif(s_WB_master_o.STB = '1') then
+ debug_stb_cnt <= debug_stb_cnt +1;
+ end if;
+ end if;
+
+ --Counter: TX bytes sent
+ if(s_state_TX = IDLE) then
+ s_EB_TX_byte_cnt <= (others => '0');
+ else
+ if(s_tx_fifo_we = '1') then
+ s_EB_TX_byte_cnt <= s_EB_TX_byte_cnt + 4;
+ end if;
+ end if;
+
+ end if;
+ end if;
+end process;
+
+p_state_transition: process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+--==========================================================================
+
+ if (nRST_i = '0') then
+
+ s_state_TX <= IDLE;
+ s_state_RX <= IDLE;
+
+ else
+ -- RX cycle line lowered before all words were transferred
+ if (s_EB_RX_byte_cnt < s_EB_packet_length
+ AND EB_RX_i.CYC = '0') then
+ report "EB: PACKET WAS ABORTED" severity note;
+ -- ERROR: -- RX cycle line lowered before all words were transferred
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
+ --
+ elsif(s_EB_RX_byte_cnt > s_EB_packet_length AND NOT (s_EB_RX_byte_cnt < 16)) then
+ report "EB: PACKET TOO LONG" severity note;
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
+ else
+
+ case s_state_RX is
+ when IDLE => if(s_rx_fifo_empty = '1') then
+ s_state_TX <= IDLE;
+ s_state_RX <= EB_HDR_REC;
+ report "EB: RDY" severity note;
+ end if;
+
+ when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
+ s_state_RX <= EB_HDR_PROC;
+ end if;
+
+ when EB_HDR_PROC => if( (s_EB_RX_HDR.EB_MAGIC /= c_EB_MAGIC_WORD) -- not EB
+ OR (s_EB_RX_HDR.VER /= c_EB_VER) -- wrong version
+ OR ((s_EB_RX_HDR.ADDR_SIZE AND c_MY_EB_ADDR_SIZE) = x"0") -- wrong size
+ OR ((s_EB_RX_HDR.PORT_SIZE AND c_MY_EB_PORT_SIZE)= x"0")) -- wrong size
+ then
+ s_state_RX <= ERROR;
+ report "EB: MALFORMED PACKET" severity note;
+ else
+ --eb hdr seems valid, prepare answering packet. Prefill RX buffer
+ if(unsigned(s_rx_fifo_gauge) > 3) then
+ s_state_TX <= EB_HDR_INIT;
+ if(s_EB_RX_HDR.PROBE = '0') then -- no probe, prepare cycle reception
+ s_state_RX <= CYC_HDR_REC;
+ else
+ s_state_RX <= EB_DONE;
+ end if;
+ end if;
+ end if;
+
+ when CYC_HDR_REC => if(s_rx_fifo_empty = '0') then
+ s_state_RX <= CYC_HDR_WRITE_PROC;
+ end if;
+
+ when CYC_HDR_WRITE_PROC => if(s_EB_RX_CUR_CYCLE.WR_CNT > 0) then
+ s_state_RX <= CYC_HDR_WRITE_GET_ADR;
+ else
+ s_state_RX <= CYC_HDR_READ_PROC;
+ end if;
+
+
+ when CYC_HDR_WRITE_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ s_state_RX <= WB_WRITE_RDY;
+ end if;
+
+ when WB_WRITE_RDY => if(s_state_TX = RDY) then
+ s_state_RX <= WB_WRITE;
+ s_state_TX <= ZERO_PAD_WRITE;
+ end if;
+
+ when WB_WRITE => if(s_EB_RX_CUR_CYCLE.WR_CNT = 0 ) then --underflow of RX_cyc_wr_count
+ s_state_RX <= CYC_HDR_READ_PROC;
+ end if;
+
+ when CYC_HDR_READ_PROC => if(s_state_TX = RDY) then
+ --are there reads to do?
+
+ if(s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+ s_state_TX <= CYC_HDR_INIT;
+ s_state_RX <= CYC_HDR_READ_GET_ADR;
+ else
+ s_state_RX <= CYC_DONE;
+ end if;
+
+ end if;
+
+ when CYC_HDR_READ_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ s_state_RX <= WB_READ_RDY;
+ end if;
+
+ when WB_READ_RDY => if(s_state_TX = RDY) then
+ s_state_RX <= WB_READ;
+ s_state_TX <= BASE_WRITE_ADR_SEND;
+ end if;
+
+ when WB_READ => if(s_EB_RX_CUR_CYCLE.RD_CNT = 0) then
+ s_state_RX <= CYC_DONE;
+ end if;
+
+ when CYC_DONE => if(a_WB_ACK_cnt = 0 AND s_tx_fifo_we = '0') then
+ if((s_EB_RX_byte_cnt < s_EB_packet_length) OR (s_EB_RX_byte_cnt = s_EB_packet_length AND s_rx_fifo_am_empty = '0')) then
+ s_state_RX <= CYC_HDR_REC;
+ else
+ --no more cycles to do, packet is done. reset FSMs
+ if(s_tx_fifo_empty = '1') then
+ s_state_RX <= EB_DONE;
+ s_state_TX <= IDLE;
+ end if;
+ end if;
+ elsif(a_WB_ACK_cnt_err = "1") then
+ s_state_RX <= ERROR;
+ end if;
+
+ when EB_DONE => if(s_state_TX = IDLE OR s_state_TX = RDY) then -- 1. packet done, 2. probe done
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
+ end if;
+
+ when ERROR => s_state_TX <= IDLE;
+ s_state_RX <= IDLE;
+ if((s_EB_RX_HDR.VER /= c_EB_VER) -- wrong version
+ OR (s_EB_RX_HDR.ADDR_SIZE /= c_MY_EB_ADDR_SIZE) -- wrong size
+ OR (s_EB_RX_HDR.PORT_SIZE /= c_MY_EB_PORT_SIZE)) then
+ s_state_TX <= ERROR;
+ end if;
+
+ when others => s_state_RX <= IDLE;
+ end case;
+
+
+ case s_state_TX is
+ when IDLE => null;
+
+ when RDY => null;--wait
+
+ when EB_HDR_INIT => s_state_TX <= PACKET_HDR_SEND;
+
+ when PACKET_HDR_SEND => s_state_TX <= EB_HDR_SEND;
+
+ --TODO: padding to 64bit alignment
+ when EB_HDR_SEND => if(s_tx_fifo_full = '0') then
+ if(s_EB_RX_HDR.PROBE = '1') then
+ s_state_TX <= IDLE;
+ else
+ s_state_TX <= RDY;
+ end if;
+ end if;
+
+ when CYC_HDR_INIT => s_state_TX <= CYC_HDR_SEND;
+
+ when CYC_HDR_SEND => if(s_tx_fifo_full = '0') then
+ s_state_TX <= RDY;
+ end if;
+
+ when BASE_WRITE_ADR_SEND => if(s_tx_fifo_full = '0') then
+ s_state_TX <= DATA_SEND;
+ end if;
+
+ when DATA_SEND => --only write at the moment!
+ if(s_EB_TX_CUR_CYCLE.WR_CNT = 0) then
+ s_state_TX <= RDY;
+ end if;
+
+ when ZERO_PAD_WRITE => if(s_EB_TX_zeropad_cnt = 0) then
+ s_state_TX <= RDY;
+ end if;
+
+ when ZERO_PAD_WAIT => null;
+
+ when others => s_state_TX <= IDLE;
+ end case;
+
+ end if;
+
+ end if;
+ end if;
+
+end process p_state_transition;
+
+p_state_output: process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+--==========================================================================
+
+ if (nRST_i = '0') then
+
+ s_EB_TX_HDR <= init_EB_HDR;
+ s_EB_TX_CUR_CYCLE <= to_EB_CYC(test);
+ s_EB_TX_base_wr_adr<= (others => '0');
+ s_EB_RX_CUR_CYCLE <= to_EB_CYC(test);
+
+ s_EB_RX_ACK <= '0';
+
+
+ EB_TX_o.CYC <= '0';
+
+ EB_TX_o.ADR <= (others => '0');
+ EB_TX_o.SEL <= (others => '1');
+ EB_TX_o.WE <= '1';
+
+ s_EB_RX_STALL <= '0';
+
+ s_WB_addr_cnt <= (others => '0');
+ s_EB_packet_length <= (others => '0');
+ s_ADR_CONFIG <= '0';
+ s_tx_fifo_clr <= '1';
+ s_rx_fifo_clr <= '1';
+ s_status_en <= '0';
+ s_status_clr <= '0';
+
+
+ s_WB_STB <= '0';
+ s_WB_WE <= '0';
+ s_WB_ADR <= (others => '0');
+
+ s_EB_TX_zeropad_cnt<= (others => '0');
+ else
+
+
+ s_EB_RX_ACK <= s_rx_fifo_we; --EB_RX_i.STB AND NOT slave_RX_stream_STALL;
+
+
+
+ s_rx_fifo_rd <= '0';
+ s_WB_WE <= '0';
+ s_WB_STB <= '0';
+ s_EB_TX_STB <= '0';
+
+ s_status_en <= '0';
+ s_status_clr <= '0';
+
+ s_tx_fifo_clr <= '0';
+ s_rx_fifo_clr <= '0';
+
+
+
+
+ case s_state_RX is
+ when IDLE => s_tx_fifo_clr <= '1';
+ s_rx_fifo_clr <= '1';
+ s_status_clr <= '1';
+
+ when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
+ s_EB_RX_HDR <= to_EB_HDR(s_rx_fifo_q);
+ s_EB_packet_length <= unsigned(byte_count_rx_i) - 42; -- Length - IPHDR - UDPHDR
+ s_rx_fifo_rd <= '1';
+ end if;
+
+ when EB_HDR_PROC => null;
+
+ when CYC_HDR_REC => if(s_rx_fifo_empty = '0') then
+ s_EB_RX_CUR_CYCLE <= TO_EB_CYC(s_rx_fifo_q);
+ s_rx_fifo_rd <= '1';
+ end if;
+
+ when CYC_HDR_WRITE_PROC => if(s_EB_RX_CUR_CYCLE.WR_CNT > 0) then
+ --setup word counters
+ s_ADR_CONFIG <= s_EB_RX_CUR_CYCLE.WCA_CFG;
+ end if;
+
+
+ when CYC_HDR_WRITE_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ s_WB_addr_cnt <= unsigned(s_rx_fifo_q);
+ s_rx_fifo_rd <= '1'; -- only stall RX if we got an adress, otherwise continue listening
+ end if;
+
+ when WB_WRITE_RDY => if(s_state_TX = RDY) then
+ s_WB_CYC <= '1';
+ -- only stall RX if we got an adress, otherwise continue listening
+ --s_WB_master_o.DAT <= s_rx_fifo_q;
+ if(s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+ s_EB_TX_zeropad_cnt <= s_EB_RX_CUR_CYCLE.WR_CNT+1; --wr start addr
+ else
+ s_EB_TX_zeropad_cnt <= s_EB_RX_CUR_CYCLE.WR_CNT+2; --wr start addr + header because read block is not called
+ end if;
+ end if;
+
+ when WB_WRITE => s_status_en <= s_WB_master_i.ACK;
+ if(s_EB_RX_CUR_CYCLE.WR_CNT > 0 ) then --underflow of RX_cyc_wr_count
+
+ s_WB_ADR <= std_logic_vector(s_WB_addr_cnt);
+ s_WB_WE <= '1';
+
+ -- case 1: elements 0 -> n-2
+ -- case 2: n-1
+ -- done to prevent buffer underrun
+
+ if(s_rx_fifo_am_empty = '0') then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_rx_fifo_rd <= '1';
+ s_EB_RX_CUR_CYCLE.WR_CNT <= s_EB_RX_CUR_CYCLE.WR_CNT-1;
+ if(s_EB_RX_CUR_CYCLE.WR_FIFO = '0') then
+ s_WB_addr_cnt <= s_WB_addr_cnt + 4;
+ end if;
+ end if;
+ elsif(s_rx_fifo_empty = '0' AND (s_EB_RX_byte_cnt = s_EB_packet_length)) then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_EB_RX_CUR_CYCLE.WR_CNT <= s_EB_RX_CUR_CYCLE.WR_CNT-1;
+ end if;
+ end if;
+
+ end if;
+
+ when CYC_HDR_READ_PROC => if(s_state_TX = RDY) then
+ --are there reads to do?
+
+ if(s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+ --setup word counters
+ s_ADR_CONFIG <= s_EB_RX_CUR_CYCLE.RCA_CFG;
+
+ end if;
+
+ end if;
+
+ when CYC_HDR_READ_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ --wait for ready from tx output
+ s_EB_TX_base_wr_adr <= s_rx_fifo_q;
+ s_rx_fifo_rd <= '1';
+ end if;
+
+
+ when WB_READ_RDY => if(s_state_TX = RDY) then
+ s_WB_CYC <= '1';
+ end if;
+
+ when WB_READ => s_status_en <= s_WB_master_i.ACK;
+ if(s_state_TX = DATA_SEND AND s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+
+ --s_WB_ADR <= s_rx_fifo_q;
+ --only go down to almost empty to keep pipeline filled
+ if((s_rx_fifo_am_empty = '0') ) then
+ if(s_tx_fifo_am_full = '0') then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_rx_fifo_rd <= '1';
+ s_EB_RX_CUR_CYCLE.RD_CNT <= s_EB_RX_CUR_CYCLE.RD_CNT-1;
+ end if;
+ end if;
+ else
+ --if these are the last bytes of the packet, empty pipeline.
+ if(s_rx_fifo_empty = '0' AND (s_EB_RX_byte_cnt = s_EB_packet_length)) then
+ if(s_tx_fifo_am_full = '0') then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_EB_RX_CUR_CYCLE.RD_CNT <= s_EB_RX_CUR_CYCLE.RD_CNT-1;
+ end if;
+ end if;
+
+ end if;
+ end if;
+ end if;
+
+ when CYC_DONE => s_status_en <= s_WB_master_i.ACK;
+ if(a_WB_ACK_cnt = 0 AND s_tx_fifo_we = '0') then
+ --keep cycle line high if no drop requested
+ s_WB_CYC <= NOT s_EB_RX_CUR_CYCLE.DROP_CYC;
+ s_status_clr <= s_EB_RX_CUR_CYCLE.DROP_CYC;
+ end if;
+
+ when EB_DONE => report "EB: PACKET COMPLETE" severity note;
+ --TODO: test multi packet mode
+ s_WB_CYC <= NOT s_EB_RX_CUR_CYCLE.DROP_CYC;
+ --make sure there is no running transfer before resetting FSMs, also do not start a new packet proc before cyc has been lowered
+
+ when ERROR => report "EB: ERROR" severity warning;
+ s_WB_CYC <= '0';
+ end case;
+
+
+
+
+
+
+ case s_state_TX is
+ when IDLE => EB_TX_o.CYC <= '0';
+
+ when RDY => null;--wait
+
+ when EB_HDR_INIT => s_EB_TX_HDR <= init_EB_hdr;
+ s_EB_TX_HDR.PROBE_RES <= s_EB_RX_HDR.PROBE;
+
+ when PACKET_HDR_SEND => EB_TX_o.CYC <= '1';
+ --using stall line for signalling the completion of Eth packet hdr
+
+ --TODO: padding to 64bit alignment
+ when EB_HDR_SEND => s_EB_TX_STB <= '1';
+ s_tx_fifo_data <= to_std_logic_vector(s_EB_TX_HDR);
+
+ when CYC_HDR_INIT => s_EB_TX_CUR_CYCLE.WCA_CFG <= s_EB_RX_CUR_CYCLE.BCA_CFG;
+ s_EB_TX_CUR_CYCLE.RD_FIFO <= '0';
+ s_EB_TX_CUR_CYCLE.RD_CNT <= (others => '0');
+ s_EB_TX_CUR_CYCLE.WR_FIFO <= s_EB_RX_CUR_CYCLE.RD_FIFO;
+ s_EB_TX_CUR_CYCLE.WR_CNT <= s_EB_RX_CUR_CYCLE.RD_CNT;
+
+ when CYC_HDR_SEND => s_tx_fifo_data <= TO_STD_LOGIC_VECTOR(s_EB_TX_CUR_CYCLE);
+ s_EB_TX_STB <= '1';
+
+ when BASE_WRITE_ADR_SEND => s_EB_TX_STB <= '1';
+ s_tx_fifo_data <= s_EB_TX_base_wr_adr;
+
+ when DATA_SEND => s_tx_fifo_data <= s_WB_master_i.DAT;
+ s_EB_TX_STB <= s_WB_master_i.ACK;
+
+ if(s_WB_master_i.ACK = '1') then
+ s_EB_TX_CUR_CYCLE.WR_CNT <= s_EB_TX_CUR_CYCLE.WR_CNT-1;
+ end if;
+
+ when ZERO_PAD_WRITE => s_tx_fifo_data <= (others => '0');
+ if((s_tx_fifo_am_full = '0') AND (s_eb_tx_zeropad_cnt > 0)) then
+ --if(s_tx_fifo_we = '1') then
+ s_EB_TX_zeropad_cnt <= s_EB_TX_zeropad_cnt -1;
+ --end if;
+ s_EB_TX_STB <= '1';
+ end if;
+
+ when ZERO_PAD_WAIT => null;
+
+ when others => null;
+ end case;
+ end if;
+ end if;
+
+end process p_state_output;
+
+
+
+
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_2_wb_converter.vhd.bak b/hdl/eb_testbench/EB_2_wb_converter.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..1510f25fc2c6902a7fc704ed6cc8b423491cd338
--- /dev/null
+++ b/hdl/eb_testbench/EB_2_wb_converter.vhd.bak
@@ -0,0 +1,795 @@
+--! @file EB_2_wb_converter.vhd
+--! @brief EtherBone logic core
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+use work.wb32_package.all;
+
+entity eb_2_wb_converter is
+port(
+ clk_i : in std_logic; --! System Clk
+ nRst_i : in std_logic; --! active low sync reset
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i : in wb32_slave_in; --! Streaming wishbone(record) sink from RX transport protocol block
+ EB_RX_o : out wb32_slave_out; --! Streaming WB sink flow control to RX transport protocol block
+
+ EB_TX_i : in wb32_master_in; --! Streaming WB src flow control from TX transport protocol block
+ EB_TX_o : out wb32_master_out; --! Streaming WB src to TX transport protocol block
+
+ byte_count_rx_i : in std_logic_vector(15 downto 0); --! Payload byte length from RX transport protocol block
+
+ --config signals
+ config_master_i : in wb32_master_in; --! WB V4 interface to WB interconnect/device(s)
+ config_master_o : out wb32_master_out; --! WB V4 interface to WB interconnect/device(s)
+
+
+
+ --WB IC signals
+ WB_master_i : in wb32_master_in; --! WB V4 interface to WB interconnect/device(s)
+ WB_master_o : out wb32_master_out --! WB V4 interface to WB interconnect/device(s)
+
+
+
+);
+end eb_2_wb_converter;
+
+architecture behavioral of eb_2_wb_converter is
+
+--Signals
+------------------------------------------------------------------------------------------
+--State Machines
+------------------------------------------------------------------------------------------
+constant c_width_int : integer := 24;
+type t_state_RX is (IDLE, EB_HDR_REC, EB_HDR_PROC, CYC_HDR_REC, CYC_HDR_READ_PROC, CYC_HDR_READ_GET_ADR, WB_READ_RDY, WB_READ, CYC_HDR_WRITE_PROC, CYC_HDR_WRITE_GET_ADR, WB_WRITE_RDY, WB_WRITE, CYC_DONE, EB_DONE, ERROR);
+type t_state_TX is (IDLE, EB_HDR_INIT, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
+
+signal s_state_RX : t_state_RX := IDLE;
+signal s_state_TX : t_state_TX := IDLE;
+
+constant test : std_logic_vector(31 downto 0) := (others => '0');
+
+------------------------------------------------------------------------------------------
+--Wishbone Interfaces
+------------------------------------------------------------------------------------------
+signal s_WB_master_i : wb32_master_in;
+signal s_WB_master_o : wb32_master_out;
+
+signal s_WB_STB : std_logic;
+signal s_WB_ADR : std_logic_vector(WB_master_o.ADR'left downto 0);
+signal s_WB_CYC : std_logic;
+signal s_WB_WE : std_logic;
+signal s_TX_STROBED : std_logic;
+
+signal s_WB_addr_inc : unsigned(c_EB_ADDR_SIZE_n-1 downto 0);
+signal s_WB_addr_cnt : unsigned(c_EB_ADDR_SIZE_n-1 downto 0);
+
+------------------------------------------------------------------------------------------
+-- Byte/Pulse Counters
+------------------------------------------------------------------------------------------
+signal s_WB_ACK_cnt_big : unsigned(8 downto 0);
+alias a_WB_ACK_cnt : unsigned(7 downto 0) is s_WB_ACK_cnt_big(7 downto 0);
+alias a_WB_ACK_cnt_err : unsigned(0 downto 0) is s_WB_ACK_cnt_big(8 downto 8);
+
+signal s_EB_TX_zeropad_cnt : unsigned(7 downto 0);
+signal s_EB_RX_byte_cnt : unsigned(15 downto 0);
+signal s_EB_TX_byte_cnt : unsigned(15 downto 0);
+
+signal debug_stb_cnt : natural := 0;
+signal debug_byte_diff : unsigned(15 downto 0);
+signal debug_diff : std_logic;
+signal debugsum : unsigned(15 downto 0);
+
+------------------------------------------------------------------------------------------
+--Config and Status Regs
+------------------------------------------------------------------------------------------
+signal s_WB_Config_o : wb32_slave_out;
+signal s_WB_Config_i : wb32_slave_in;
+signal s_ADR_CONFIG : std_logic;
+
+signal s_status_en : std_logic;
+signal s_status_clr : std_logic;
+
+------------------------------------------------------------------------------------------
+--Etherbone Signals
+------------------------------------------------------------------------------------------
+signal s_EB_RX_ACK : std_logic;
+signal s_EB_RX_STALL : std_logic;
+signal s_EB_TX_STB : std_logic;
+signal s_packet_reception_complete : std_logic;
+
+signal sink_valid : std_logic;
+
+------------------------------------------------------------------------------------------
+--Etherbone Registers
+------------------------------------------------------------------------------------------
+constant c_WB_WORDSIZE : natural := 32;
+constant c_EB_HDR_LEN : unsigned(3 downto 0):= x"0";
+signal s_EB_TX_base_wr_adr : std_logic_vector(31 downto 0);
+signal s_EB_packet_length : unsigned(15 downto 0);
+
+signal s_EB_RX_HDR : EB_HDR;
+signal s_EB_RX_CUR_CYCLE : EB_CYC;
+signal s_EB_TX_HDR : EB_HDR;
+signal s_EB_TX_CUR_CYCLE : EB_CYC;
+
+------------------------------------------------------------------------------------------
+--Etherbone FIFO Buffers
+------------------------------------------------------------------------------------------
+signal s_tx_fifo_am_full : std_logic;
+signal s_tx_fifo_full : std_logic;
+signal s_tx_fifo_am_empty : std_logic;
+signal s_tx_fifo_empty : std_logic;
+signal s_tx_fifo_data : std_logic_vector(31 downto 0);
+signal s_tx_fifo_rd : std_logic;
+signal s_tx_fifo_clr : std_logic;
+signal s_tx_fifo_we : std_logic;
+signal s_tx_fifo_gauge : std_logic_vector(3 downto 0);
+
+signal s_rx_fifo_am_full : std_logic;
+signal s_rx_fifo_full : std_logic;
+signal s_rx_fifo_am_empty : std_logic;
+signal s_rx_fifo_empty : std_logic;
+signal s_rx_fifo_data : std_logic_vector(31 downto 0);
+signal s_rx_fifo_q : std_logic_vector(31 downto 0);
+signal s_rx_fifo_rd : std_logic;
+signal s_rx_fifo_clr : std_logic;
+signal s_rx_fifo_we : std_logic;
+signal s_rx_fifo_gauge : std_logic_vector(3 downto 0);
+------------------------------------------------------------------------------------------
+
+
+
+
+constant WBM_Zero_o : wb32_master_out := (CYC => '0',
+ STB => '0',
+ ADR => (others => '0'),
+ SEL => (others => '0'),
+ WE => '0',
+ DAT => (others => '0'));
+
+constant WBS_Zero_o : wb32_slave_out := (ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ STALL => '0',
+ DAT => (others => '0'));
+
+component alt_FIFO_am_full_flag IS
+ PORT
+ (
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ sclr : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_empty : OUT STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+ );
+end component alt_FIFO_am_full_flag;
+
+begin
+
+TX_FIFO : alt_FIFO_am_full_flag
+port map(
+ clock => clk_i,
+ data => s_tx_fifo_data,
+ rdreq => s_tx_fifo_rd,
+ sclr => s_tx_fifo_clr,
+ wrreq => s_tx_fifo_we,
+ almost_empty => s_tx_fifo_am_empty,
+ almost_full => s_tx_fifo_am_full,
+ empty => s_tx_fifo_empty,
+ full => s_tx_fifo_full,
+ q => EB_TX_o.DAT,
+ usedw => s_tx_fifo_gauge
+ );
+
+--strobe out as long as there is data left
+EB_TX_o.STB <= NOT s_tx_fifo_empty;
+
+--read data from RX fifo as long as TX interface is free
+s_tx_fifo_rd <= NOT EB_TX_i.STALL;
+
+--write in pending data as long as there is space left
+s_tx_fifo_we <= s_EB_TX_STB AND NOT s_tx_fifo_full;
+
+ RX_FIFO : alt_FIFO_am_full_flag
+port map(
+ clock => clk_i,
+ data => EB_RX_i.DAT,
+ rdreq => s_rx_fifo_rd,
+ sclr => s_rx_fifo_clr,
+ wrreq => s_rx_fifo_we,
+ almost_empty => open,
+ almost_full => s_rx_fifo_am_full,
+ empty => s_rx_fifo_empty,
+ full => s_rx_fifo_full,
+ q => s_rx_fifo_q,
+ usedw => s_rx_fifo_gauge
+ );
+
+--BUG: almost_empty flag is stuck after hitting empty repeatedly.
+--create our own for now
+s_rx_fifo_am_empty <= '1' when unsigned(s_rx_fifo_gauge) <= 1
+ else '0';
+
+--workaround to avoid creation of two drivers for the s_WB_master_o record
+s_WB_master_o.DAT <= s_rx_fifo_q;
+s_WB_master_o.STB <= s_WB_STB;
+
+--when reading, incoming rx data goes on the WB address lines
+s_WB_master_o.ADR <= s_rx_fifo_q when s_state_RX = WB_READ
+ else s_WB_ADR;
+
+s_WB_master_o.CYC <= s_WB_CYC;
+s_WB_master_o.WE <= s_WB_WE;
+EB_RX_o.STALL <= s_rx_fifo_am_full;
+EB_RX_o.ACK <= s_EB_RX_ACK;
+
+s_rx_fifo_we <= EB_RX_i.STB AND NOT (s_rx_fifo_am_full); -- OR s_packet_reception_complete);
+
+
+--MUX lines: WB master / config space master
+---------------------------------
+Mux_WB_Cfg_in : with s_ADR_CONFIG select
+s_WB_master_i <= config_master_i when '1',
+ WB_master_i when others;
+
+-- select WB Master Port Out: Tie to ground / Signal s_WB_master_o
+Mux_WB_out : with s_ADR_CONFIG select
+WB_master_o <= WBM_Zero_o when '1',
+ s_WB_master_o when others;
+
+-- select WB Master Port Out: Tie to ground / Signal s_WB_master_o
+Mux_Cfg_out : with s_ADR_CONFIG select
+config_master_o <= s_WB_master_o when '1',
+ WBM_Zero_o when others;
+-----------------------------------
+
+
+
+
+
+debug_diff <= '1' when debug_byte_diff > 0 else '0';
+
+count_io : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ if (nRST_i = '0') then
+ s_EB_RX_byte_cnt <= (others => '0');
+ s_EB_TX_byte_cnt <= (others => '0');
+ s_WB_ACK_cnt_big <= (others => '0');
+ else
+
+
+ --Counter: RX bytes received
+ if(s_state_RX = IDLE) then
+ s_EB_RX_byte_cnt <= (others => '0');
+ else
+ if(s_rx_fifo_we = '1') then
+ s_EB_RX_byte_cnt <= s_EB_RX_byte_cnt + 4;
+ end if;
+ end if;
+ -- packet reception is not complete if min packet size not reached and < s_EB_packet_length
+ --
+ if((s_EB_RX_byte_cnt < s_EB_packet_length) OR (s_EB_RX_byte_cnt < 16)) then
+ s_packet_reception_complete <= '0';
+ else
+ s_packet_reception_complete <= '1';
+ end if;
+
+ --Counter: WB ACKs received
+ if(s_state_RX = IDLE) then
+ s_WB_ACK_cnt_big <= (others => '0');
+ else
+ if(s_state_RX = CYC_HDR_WRITE_PROC) then
+ a_WB_ACK_cnt <= s_EB_RX_CUR_CYCLE.RD_CNT + s_EB_RX_CUR_CYCLE.WR_CNT;
+ elsif(s_WB_master_i.ACK = '1') then
+ a_WB_ACK_cnt <= a_WB_ACK_cnt -1;
+ end if;
+ end if;
+
+ --Counter: WB ACKs received
+ if(s_state_RX = IDLE) then
+ debug_stb_cnt <= 0;
+ else
+ if(s_state_RX = CYC_HDR_WRITE_PROC) then
+ debug_stb_cnt <= 0;
+ elsif(s_WB_master_o.STB = '1') then
+ debug_stb_cnt <= debug_stb_cnt +1;
+ end if;
+ end if;
+
+ --Counter: TX bytes sent
+ if(s_state_TX = IDLE) then
+ s_EB_TX_byte_cnt <= (others => '0');
+ else
+ if(s_tx_fifo_we = '1') then
+ s_EB_TX_byte_cnt <= s_EB_TX_byte_cnt + 4;
+ end if;
+ end if;
+
+ end if;
+ end if;
+end process;
+
+p_state_transition: process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+--==========================================================================
+
+ if (nRST_i = '0') then
+
+ s_state_TX <= IDLE;
+ s_state_RX <= IDLE;
+
+ else
+ -- RX cycle line lowered before all words were transferred
+ if (s_EB_RX_byte_cnt < s_EB_packet_length
+ AND EB_RX_i.CYC = '0') then
+ report "EB: PACKET WAS ABORTED" severity note;
+ -- ERROR: -- RX cycle line lowered before all words were transferred
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
+ --
+ elsif(s_EB_RX_byte_cnt > s_EB_packet_length AND NOT (s_EB_RX_byte_cnt < 16)) then
+ report "EB: PACKET TOO LONG" severity note;
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
+ else
+
+ case s_state_RX is
+ when IDLE => if(s_rx_fifo_empty = '1') then
+ s_state_TX <= IDLE;
+ s_state_RX <= EB_HDR_REC;
+ report "EB: RDY" severity note;
+ end if;
+
+ when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
+ s_state_RX <= EB_HDR_PROC;
+ end if;
+
+ when EB_HDR_PROC => if( (s_EB_RX_HDR.EB_MAGIC /= c_EB_MAGIC_WORD) -- not EB
+ OR (s_EB_RX_HDR.VER /= c_EB_VER) -- wrong version
+ OR ((s_EB_RX_HDR.ADDR_SIZE AND c_MY_EB_ADDR_SIZE) = x"0") -- wrong size
+ OR ((s_EB_RX_HDR.PORT_SIZE AND c_MY_EB_PORT_SIZE)= x"0")) -- wrong size
+ then
+ s_state_RX <= ERROR;
+ report "EB: MALFORMED PACKET" severity note;
+ else
+ --eb hdr seems valid, prepare answering packet. Prefill RX buffer
+ if(unsigned(s_rx_fifo_gauge) > 3) then
+ s_state_TX <= EB_HDR_INIT;
+ if(s_EB_RX_HDR.PROBE = '0') then -- no probe, prepare cycle reception
+ s_state_RX <= CYC_HDR_REC;
+ else
+ s_EB_RX_HDR
+ s_state_RX <= EB_DONE;
+ end if;
+ end if;
+ end if;
+
+ when CYC_HDR_REC => if(s_rx_fifo_empty = '0') then
+ s_state_RX <= CYC_HDR_WRITE_PROC;
+ end if;
+
+ when CYC_HDR_WRITE_PROC => if(s_EB_RX_CUR_CYCLE.WR_CNT > 0) then
+ s_state_RX <= CYC_HDR_WRITE_GET_ADR;
+ else
+ s_state_RX <= CYC_HDR_READ_PROC;
+ end if;
+
+
+ when CYC_HDR_WRITE_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ s_state_RX <= WB_WRITE_RDY;
+ end if;
+
+ when WB_WRITE_RDY => if(s_state_TX = RDY) then
+ s_state_RX <= WB_WRITE;
+ s_state_TX <= ZERO_PAD_WRITE;
+ end if;
+
+ when WB_WRITE => if(s_EB_RX_CUR_CYCLE.WR_CNT = 0 ) then --underflow of RX_cyc_wr_count
+ s_state_RX <= CYC_HDR_READ_PROC;
+ end if;
+
+ when CYC_HDR_READ_PROC => if(s_state_TX = RDY) then
+ --are there reads to do?
+
+ if(s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+ s_state_TX <= CYC_HDR_INIT;
+ s_state_RX <= CYC_HDR_READ_GET_ADR;
+ else
+ s_state_RX <= CYC_DONE;
+ end if;
+
+ end if;
+
+ when CYC_HDR_READ_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ s_state_RX <= WB_READ_RDY;
+ end if;
+
+ when WB_READ_RDY => if(s_state_TX = RDY) then
+ s_state_RX <= WB_READ;
+ s_state_TX <= BASE_WRITE_ADR_SEND;
+ end if;
+
+ when WB_READ => if(s_EB_RX_CUR_CYCLE.RD_CNT = 0) then
+ s_state_RX <= CYC_DONE;
+ end if;
+
+ when CYC_DONE => if(a_WB_ACK_cnt = 0 AND s_tx_fifo_we = '0') then
+ if((s_EB_RX_byte_cnt < s_EB_packet_length) OR (s_EB_RX_byte_cnt = s_EB_packet_length AND s_rx_fifo_am_empty = '0')) then
+ s_state_RX <= CYC_HDR_REC;
+ else
+ --no more cycles to do, packet is done. reset FSMs
+ if(s_tx_fifo_empty = '1') then
+ s_state_RX <= EB_DONE;
+ s_state_TX <= IDLE;
+ end if;
+ end if;
+ elsif(a_WB_ACK_cnt_err = "1") then
+ s_state_RX <= ERROR;
+ end if;
+
+ when EB_DONE => if(s_state_TX = IDLE OR s_state_TX = RDY) then -- 1. packet done, 2. probe done
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
+ end if;
+
+ when ERROR => s_state_TX <= IDLE;
+ s_state_RX <= IDLE;
+ if((s_EB_RX_HDR.VER /= c_EB_VER) -- wrong version
+ OR (s_EB_RX_HDR.ADDR_SIZE /= c_MY_EB_ADDR_SIZE) -- wrong size
+ OR (s_EB_RX_HDR.PORT_SIZE /= c_MY_EB_PORT_SIZE)) then
+ s_state_TX <= ERROR;
+ end if;
+
+ when others => s_state_RX <= IDLE;
+ end case;
+
+
+ case s_state_TX is
+ when IDLE => null;
+
+ when RDY => null;--wait
+
+ when EB_HDR_INIT => s_state_TX <= PACKET_HDR_SEND;
+
+ when PACKET_HDR_SEND => s_state_TX <= EB_HDR_SEND;
+
+ --TODO: padding to 64bit alignment
+ when EB_HDR_SEND => if(s_tx_fifo_full = '0') then
+ if(s_EB_RX_HDR.PROBE = '1') then
+ s_state_TX <= IDLE;
+ else
+ s_state_TX <= RDY;
+ end if;
+ end if;
+
+ when CYC_HDR_INIT => s_state_TX <= CYC_HDR_SEND;
+
+ when CYC_HDR_SEND => if(s_tx_fifo_full = '0') then
+ s_state_TX <= RDY;
+ end if;
+
+ when BASE_WRITE_ADR_SEND => if(s_tx_fifo_full = '0') then
+ s_state_TX <= DATA_SEND;
+ end if;
+
+ when DATA_SEND => --only write at the moment!
+ if(s_EB_TX_CUR_CYCLE.WR_CNT = 0) then
+ s_state_TX <= RDY;
+ end if;
+
+ when ZERO_PAD_WRITE => if(s_EB_TX_zeropad_cnt = 0) then
+ s_state_TX <= RDY;
+ end if;
+
+ when ZERO_PAD_WAIT => null;
+
+ when others => s_state_TX <= IDLE;
+ end case;
+
+ end if;
+
+ end if;
+ end if;
+
+end process p_state_transition;
+
+p_state_output: process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+--==========================================================================
+
+ if (nRST_i = '0') then
+
+ s_EB_TX_HDR <= init_EB_HDR;
+ s_EB_TX_CUR_CYCLE <= to_EB_CYC(test);
+ s_EB_TX_base_wr_adr<= (others => '0');
+ s_EB_RX_CUR_CYCLE <= to_EB_CYC(test);
+
+ s_EB_RX_ACK <= '0';
+
+
+ EB_TX_o.CYC <= '0';
+
+ EB_TX_o.ADR <= (others => '0');
+ EB_TX_o.SEL <= (others => '1');
+ EB_TX_o.WE <= '1';
+
+ s_EB_RX_STALL <= '0';
+
+ s_WB_addr_cnt <= (others => '0');
+ s_EB_packet_length <= (others => '0');
+ s_ADR_CONFIG <= '0';
+ s_tx_fifo_clr <= '1';
+ s_rx_fifo_clr <= '1';
+ s_status_en <= '0';
+ s_status_clr <= '0';
+
+
+ s_WB_STB <= '0';
+ s_WB_WE <= '0';
+ s_WB_ADR <= (others => '0');
+
+ s_EB_TX_zeropad_cnt<= (others => '0');
+ else
+
+
+ s_EB_RX_ACK <= s_rx_fifo_we; --EB_RX_i.STB AND NOT slave_RX_stream_STALL;
+
+
+
+ s_rx_fifo_rd <= '0';
+ s_WB_WE <= '0';
+ s_WB_STB <= '0';
+ s_EB_TX_STB <= '0';
+
+ s_status_en <= '0';
+ s_status_clr <= '0';
+
+ s_tx_fifo_clr <= '0';
+ s_rx_fifo_clr <= '0';
+
+
+
+
+ case s_state_RX is
+ when IDLE => s_tx_fifo_clr <= '1';
+ s_rx_fifo_clr <= '1';
+ s_status_clr <= '1';
+
+ when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
+ s_EB_RX_HDR <= to_EB_HDR(s_rx_fifo_q);
+ s_EB_packet_length <= unsigned(byte_count_rx_i) - 42; -- Length - IPHDR - UDPHDR
+ s_rx_fifo_rd <= '1';
+ end if;
+
+ when EB_HDR_PROC => null;
+
+ when CYC_HDR_REC => if(s_rx_fifo_empty = '0') then
+ s_EB_RX_CUR_CYCLE <= TO_EB_CYC(s_rx_fifo_q);
+ s_rx_fifo_rd <= '1';
+ end if;
+
+ when CYC_HDR_WRITE_PROC => if(s_EB_RX_CUR_CYCLE.WR_CNT > 0) then
+ --setup word counters
+ s_ADR_CONFIG <= s_EB_RX_CUR_CYCLE.WCA_CFG;
+ end if;
+
+
+ when CYC_HDR_WRITE_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ s_WB_addr_cnt <= unsigned(s_rx_fifo_q);
+ s_rx_fifo_rd <= '1'; -- only stall RX if we got an adress, otherwise continue listening
+ end if;
+
+ when WB_WRITE_RDY => if(s_state_TX = RDY) then
+ s_WB_CYC <= '1';
+ -- only stall RX if we got an adress, otherwise continue listening
+ --s_WB_master_o.DAT <= s_rx_fifo_q;
+ if(s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+ s_EB_TX_zeropad_cnt <= s_EB_RX_CUR_CYCLE.WR_CNT+1; --wr start addr
+ else
+ s_EB_TX_zeropad_cnt <= s_EB_RX_CUR_CYCLE.WR_CNT+2; --wr start addr + header because read block is not called
+ end if;
+ end if;
+
+ when WB_WRITE => s_status_en <= s_WB_master_i.ACK;
+ if(s_EB_RX_CUR_CYCLE.WR_CNT > 0 ) then --underflow of RX_cyc_wr_count
+
+ s_WB_ADR <= std_logic_vector(s_WB_addr_cnt);
+ s_WB_WE <= '1';
+
+ -- case 1: elements 0 -> n-2
+ -- case 2: n-1
+ -- done to prevent buffer underrun
+
+ if(s_rx_fifo_am_empty = '0') then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_rx_fifo_rd <= '1';
+ s_EB_RX_CUR_CYCLE.WR_CNT <= s_EB_RX_CUR_CYCLE.WR_CNT-1;
+ if(s_EB_RX_CUR_CYCLE.WR_FIFO = '0') then
+ s_WB_addr_cnt <= s_WB_addr_cnt + 4;
+ end if;
+ end if;
+ elsif(s_rx_fifo_empty = '0' AND (s_EB_RX_byte_cnt = s_EB_packet_length)) then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_EB_RX_CUR_CYCLE.WR_CNT <= s_EB_RX_CUR_CYCLE.WR_CNT-1;
+ end if;
+ end if;
+
+ end if;
+
+ when CYC_HDR_READ_PROC => if(s_state_TX = RDY) then
+ --are there reads to do?
+
+ if(s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+ --setup word counters
+ s_ADR_CONFIG <= s_EB_RX_CUR_CYCLE.RCA_CFG;
+
+ end if;
+
+ end if;
+
+ when CYC_HDR_READ_GET_ADR => if(s_rx_fifo_am_empty = '0') then
+ --wait for ready from tx output
+ s_EB_TX_base_wr_adr <= s_rx_fifo_q;
+ s_rx_fifo_rd <= '1';
+ end if;
+
+
+ when WB_READ_RDY => if(s_state_TX = RDY) then
+ s_WB_CYC <= '1';
+ end if;
+
+ when WB_READ => s_status_en <= s_WB_master_i.ACK;
+ if(s_state_TX = DATA_SEND AND s_EB_RX_CUR_CYCLE.RD_CNT > 0) then
+
+ --s_WB_ADR <= s_rx_fifo_q;
+ --only go down to almost empty to keep pipeline filled
+ if((s_rx_fifo_am_empty = '0') ) then
+ if(s_tx_fifo_am_full = '0') then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_rx_fifo_rd <= '1';
+ s_EB_RX_CUR_CYCLE.RD_CNT <= s_EB_RX_CUR_CYCLE.RD_CNT-1;
+ end if;
+ end if;
+ else
+ --if these are the last bytes of the packet, empty pipeline.
+ if(s_rx_fifo_empty = '0' AND (s_EB_RX_byte_cnt = s_EB_packet_length)) then
+ if(s_tx_fifo_am_full = '0') then
+ s_WB_STB <= '1';
+ if(s_WB_master_i.STALL = '0') then
+ s_EB_RX_CUR_CYCLE.RD_CNT <= s_EB_RX_CUR_CYCLE.RD_CNT-1;
+ end if;
+ end if;
+
+ end if;
+ end if;
+ end if;
+
+ when CYC_DONE => s_status_en <= s_WB_master_i.ACK;
+ if(a_WB_ACK_cnt = 0 AND s_tx_fifo_we = '0') then
+ --keep cycle line high if no drop requested
+ s_WB_CYC <= NOT s_EB_RX_CUR_CYCLE.DROP_CYC;
+ s_status_clr <= s_EB_RX_CUR_CYCLE.DROP_CYC;
+ end if;
+
+ when EB_DONE => report "EB: PACKET COMPLETE" severity note;
+ --TODO: test multi packet mode
+ s_WB_CYC <= NOT s_EB_RX_CUR_CYCLE.DROP_CYC;
+ --make sure there is no running transfer before resetting FSMs, also do not start a new packet proc before cyc has been lowered
+
+ when ERROR => report "EB: ERROR" severity warning;
+ s_WB_CYC <= '0';
+ end case;
+
+
+
+
+
+
+ case s_state_TX is
+ when IDLE => EB_TX_o.CYC <= '0';
+
+ when RDY => null;--wait
+
+ when EB_HDR_INIT => s_EB_TX_HDR <= init_EB_hdr;
+ s_EB_TX_HDR.PROBE_RES <= s_EB_RX_HDR.PROBE;
+
+ when PACKET_HDR_SEND => EB_TX_o.CYC <= '1';
+ --using stall line for signalling the completion of Eth packet hdr
+
+ --TODO: padding to 64bit alignment
+ when EB_HDR_SEND => s_EB_TX_STB <= '1';
+ s_tx_fifo_data <= to_std_logic_vector(s_EB_TX_HDR);
+
+ when CYC_HDR_INIT => s_EB_TX_CUR_CYCLE.WCA_CFG <= s_EB_RX_CUR_CYCLE.BCA_CFG;
+ s_EB_TX_CUR_CYCLE.RD_FIFO <= '0';
+ s_EB_TX_CUR_CYCLE.RD_CNT <= (others => '0');
+ s_EB_TX_CUR_CYCLE.WR_FIFO <= s_EB_RX_CUR_CYCLE.RD_FIFO;
+ s_EB_TX_CUR_CYCLE.WR_CNT <= s_EB_RX_CUR_CYCLE.RD_CNT;
+
+ when CYC_HDR_SEND => s_tx_fifo_data <= TO_STD_LOGIC_VECTOR(s_EB_TX_CUR_CYCLE);
+ s_EB_TX_STB <= '1';
+
+ when BASE_WRITE_ADR_SEND => s_EB_TX_STB <= '1';
+ s_tx_fifo_data <= s_EB_TX_base_wr_adr;
+
+ when DATA_SEND => s_tx_fifo_data <= s_WB_master_i.DAT;
+ s_EB_TX_STB <= s_WB_master_i.ACK;
+
+ if(s_WB_master_i.ACK = '1') then
+ s_EB_TX_CUR_CYCLE.WR_CNT <= s_EB_TX_CUR_CYCLE.WR_CNT-1;
+ end if;
+
+ when ZERO_PAD_WRITE => s_tx_fifo_data <= (others => '0');
+ if((s_tx_fifo_am_full = '0') AND (s_eb_tx_zeropad_cnt > 0)) then
+ --if(s_tx_fifo_we = '1') then
+ s_EB_TX_zeropad_cnt <= s_EB_TX_zeropad_cnt -1;
+ --end if;
+ s_EB_TX_STB <= '1';
+ end if;
+
+ when ZERO_PAD_WAIT => null;
+
+ when others => null;
+ end case;
+ end if;
+ end if;
+
+end process p_state_output;
+
+
+
+
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_CORE.vhd b/hdl/eb_testbench/EB_CORE.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..520e13f74d14ec176fe2af3d6972dc85a156d11e
--- /dev/null
+++ b/hdl/eb_testbench/EB_CORE.vhd
@@ -0,0 +1,575 @@
+--! @file EB_CORE.vhd
+--! @brief Top file for EtherBone core
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.EB_HDR_PKG.all;
+--use work.EB_components_pkg.all;
+use work.wb32_package.all;
+use work.wb16_package.all;
+
+
+entity EB_CORE is
+generic(g_master_slave : natural := 0);
+port
+(
+ clk_i : in std_logic; --! clock input
+ nRst_i : in std_logic;
+
+ -- slave RX streaming IF -------------------------------------
+ snk_CYC_i : in std_logic; --
+ snk_STB_i : in std_logic; --
+ snk_DAT_i : in std_logic_vector(15 downto 0); --
+ snk_sel_i : in std_logic_vector(1 downto 0);
+ snk_adr_i : in std_logic_vector(1 downto 0);
+ snk_WE_i : in std_logic;
+ snk_STALL_o : out std_logic; --
+ snk_ERR_o : out std_logic; --
+ snk_ACK_o : out std_logic; --
+ --------------------------------------------------------------
+
+ -- master TX streaming IF ------------------------------------
+ src_CYC_o : out std_logic; --
+ src_STB_o : out std_logic; --
+ src_WE_o : out std_logic;
+ src_DAT_o : out std_logic_vector(15 downto 0); --
+ src_STALL_i : in std_logic; --
+ src_ERR_i : in std_logic; --
+ src_ACK_i : in std_logic; --
+ src_adr_o : out std_logic_vector(1 downto 0);
+
+ src_sel_o : out std_logic_vector(1 downto 0);
+ --------------------------------------------------------------
+ debug_TX_TOL_o : out std_logic_vector(15 downto 0);
+ hex_switch_i : in std_logic_vector(3 downto 0);
+
+ -- slave Cfg IF ----------------------------------------------
+ cfg_slave_cyc_i : in std_logic;
+cfg_slave_we_i : in std_logic;
+cfg_slave_stb_i : in std_logic;
+cfg_slave_sel_i : in std_logic_vector(3 downto 0);
+cfg_slave_adr_i : in std_logic_vector(31 downto 0);
+cfg_slave_dat_i : in std_logic_vector(31 downto 0);
+cfg_slave_dat_o : out std_logic_vector(31 downto 0);
+cfg_slave_stall_o : out std_logic;
+cfg_slave_ack_o : out std_logic;
+cfg_slave_err_o : out std_logic;
+
+ -- master IC IF ----------------------------------------------
+ master_cyc_o : out std_logic;
+ master_we_o : out std_logic;
+ master_stb_o : out std_logic;
+ master_sel_o : out std_logic_vector(3 downto 0);
+ master_adr_o : out std_logic_vector(31 downto 0);
+ master_dat_o : out std_logic_vector(31 downto 0);
+ master_dat_i : in std_logic_vector(31 downto 0);
+ master_stall_i : in std_logic;
+ master_ack_i : in std_logic
+ --------------------------------------------------------------
+
+);
+end EB_CORE;
+
+
+
+
+
+
+architecture behavioral of EB_CORE is
+
+signal s_status_en : std_logic;
+signal s_status_clr : std_logic;
+
+
+signal DEBUG_sink1_valid : std_logic;
+signal DEBUG_sink23_valid : std_logic;
+
+signal DEBUG_WB_master_o : wb32_master_out;
+signal WB_master_i : wb32_master_in;
+
+
+-- int eb if to cfg space
+signal eb_2_CFG_slave : wb32_slave_in;
+signal CFG_2_eb_slave : wb32_slave_out;
+
+
+-- ext if to cfg space
+signal EXT_2_CFG_slave : wb32_slave_in;
+signal CFG_2_EXT_slave : wb32_slave_out;
+
+
+
+-- TX CTRL <-> EBCORE signals
+
+signal EB_2_TXCTRL_wb_slave : wb32_slave_in;
+signal TXCTRL_2_EB_wb_slave : wb32_slave_out;
+
+
+
+signal EB_2_RXCTRL_wb_master : wb32_master_in;
+signal RXCTRL_2_EB_wb_master : wb32_master_out;
+
+-- RX CTRL <-> TXCTRL signals
+signal RXCTRL_2_TXCTRL_reply_MAC : std_logic_vector(47 downto 0);
+signal RXCTRL_2_TXCTRL_reply_IP : std_logic_vector(31 downto 0);
+signal RXCTRL_2_TXCTRL_reply_PORT : std_logic_vector(15 downto 0);
+signal RXCTRL_2_TXCTRL_TOL : std_logic_vector(15 downto 0);
+signal RXCTRL_2_TXCTRL_valid : std_logic;
+
+--EB <-> TXCTRL
+signal EB_2_TXCTRL_wb_master : wb32_master_out;
+signal TXCTRL_2_EB_wb_master : wb32_master_in;
+
+--EB <-> RXCTRL
+signal EB_2_RXCTRL_wb_slave : wb32_slave_out;
+signal RXCTRL_2_EB_wb_slave : wb32_slave_in;
+
+signal EB_RX_i : wb16_slave_in;
+signal EB_RX_o : wb16_slave_out;
+
+signal EB_TX_i : wb16_master_in;
+signal EB_TX_o : wb16_master_out;
+
+component binary_sink is
+generic(filename : string := "123.pcap"; wordsize : natural := 64; endian : natural := 0);
+port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+
+ rdy_o : out std_logic;
+
+ sample_i : in std_logic;
+ valid_i : in std_logic;
+ data_i : in std_logic_vector(wordsize-1 downto 0)
+);
+end component;
+
+
+
+component EB_TX_CTRL is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i : in wb32_slave_in;
+ wb_slave_o : out wb32_slave_out;
+
+ TX_master_o : out wb16_master_out; --! Wishbone master output lines
+ TX_master_i : in wb16_master_in; --!
+
+
+
+ reply_MAC_i : in std_logic_vector(47 downto 0);
+ reply_IP_i : in std_logic_vector(31 downto 0);
+ reply_PORT_i : in std_logic_vector(15 downto 0);
+
+ TOL_i : in std_logic_vector(15 downto 0);
+
+ valid_i : in std_logic
+
+);
+end component;
+
+component EB_RX_CTRL is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+
+ RX_slave_o : out wb16_slave_out; --! Wishbone master output lines
+ RX_slave_i : in wb16_slave_in; --!
+
+ --Eth MAC WB Streaming signals
+ wb_master_i : in wb32_master_in;
+ wb_master_o : out wb32_master_out;
+
+ reply_VLAN_o : out std_logic_vector(31 downto 0);
+ reply_MAC_o : out std_logic_vector(47 downto 0);
+ reply_IP_o : out std_logic_vector(31 downto 0);
+ reply_PORT_o : out std_logic_vector(15 downto 0);
+
+ TOL_o : out std_logic_vector(15 downto 0);
+
+
+ valid_o : out std_logic
+
+);
+end component;
+
+component eb_2_wb_converter is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i : in wb32_slave_in;
+ EB_RX_o : out wb32_slave_out;
+
+ EB_TX_i : in wb32_master_in;
+ EB_TX_o : out wb32_master_out;
+
+ byte_count_rx_i : in std_logic_vector(15 downto 0);
+
+ --config signals
+ config_master_i : in wb32_master_in; --! WB V4 interface to WB interconnect/device(s)
+ config_master_o : out wb32_master_out; --! WB V4 interface to WB interconnect/device(s)
+
+
+ --WB IC signals
+ WB_master_i : in wb32_master_in;
+ WB_master_o : out wb32_master_out
+
+);
+end component;
+
+component eb_config is
+ port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+ status_i : in std_logic;
+ status_en : in std_logic;
+ status_clr : in std_logic;
+
+ my_mac_address_o : out std_logic_vector(47 downto 0);
+ my_ip_address_o : out std_logic_vector(31 downto 0);
+
+ local_slave_o : out wb32_slave_out;
+ local_slave_i : in wb32_slave_in; --! local Wishbone master lines
+
+ eb_slave_o : out wb32_slave_out; --! EB Wishbone slave lines
+ eb_slave_i : in wb32_slave_in
+ );
+end component;
+
+
+component eb_mini_master is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i : in wb32_slave_in;
+ EB_RX_o : out wb32_slave_out;
+
+ EB_TX_i : in wb32_master_in;
+ EB_TX_o : out wb32_master_out;
+
+ byte_count_rx_i : in std_logic_vector(15 downto 0);
+
+ dst_MAC_o : out std_logic_vector(47 downto 0);
+ dst_IP_o : out std_logic_vector(31 downto 0);
+ dst_PORT_o : out std_logic_vector(15 downto 0);
+
+ TOL_o : out std_logic_vector(15 downto 0);
+ hex_switch_i : in std_logic_vector(3 downto 0);
+
+ valid_o : out std_logic
+
+);
+end component;
+
+
+ begin
+
+ debug_TX_TOL_o <= RXCTRL_2_TXCTRL_TOL;
+
+
+
+
+-- file_sink1: binary_sink generic map ( filename => "Eb_RX_data.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => RXCTRL_2_EB_wb_master.CYC,
+ -- valid_i => DEBUG_sink1_valid,
+ -- data_i => RXCTRL_2_EB_wb_master.DAT );
+
+-- file_sink2: binary_sink generic map ( filename => "Eb_WB_data_o.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => DEBUG_WB_master_o.CYC,
+ -- valid_i => DEBUG_sink23_valid,
+ -- data_i => DEBUG_WB_master_o.DAT );
+
+ -- file_sink3: binary_sink generic map ( filename => "Eb_WB_addr.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => DEBUG_WB_master_o.CYC,
+ -- valid_i => DEBUG_sink23_valid,
+ -- data_i => DEBUG_WB_master_o.ADR );
+
+ -- file_sink4: binary_sink generic map ( filename => "Eb_WB_data_i.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => DEBUG_WB_master_o.CYC,
+ -- valid_i => WB_master_i.ACK,
+ -- data_i => WB_master_i.DAT );
+
+
+ DEBUG_sink1_valid <= (RXCTRL_2_EB_wb_master.STB AND NOT EB_2_RXCTRL_wb_slave.STALL);
+ DEBUG_sink23_valid <= (DEBUG_WB_master_o.STB AND NOT WB_master_i.STALL);
+
+
+
+
+
+ -- EB type conversions for WB daisychain
+EB_2_TXCTRL_wb_slave <= wb32_slave_in(EB_2_TXCTRL_wb_master);
+TXCTRL_2_EB_wb_master <= wb32_master_in(TXCTRL_2_EB_wb_slave);
+
+EB_2_RXCTRL_wb_master <= wb32_master_in(EB_2_RXCTRL_wb_slave);
+RXCTRL_2_EB_wb_slave <= wb32_slave_in(RXCTRL_2_EB_wb_master);
+
+-- assign records to individual bus signals.
+-- slave RX
+EB_RX_i.CYC <= snk_CYC_i;
+EB_RX_i.STB <= snk_STB_i;
+EB_RX_i.DAT <= snk_DAT_i;
+EB_RX_i.WE <= snk_WE_i;
+snk_STALL_o <= EB_RX_o.STALL;
+snk_ERR_o <= EB_RX_o.ERR;
+snk_ACK_o <= EB_RX_o.ACK;
+
+-- master TX
+src_CYC_o <= EB_TX_o.CYC;
+src_STB_o <= EB_TX_o.STB;
+src_DAT_o <= EB_TX_o.DAT;
+src_WE_o <= EB_TX_o.WE;
+EB_TX_i.STALL <= src_STALL_i;
+EB_TX_i.ERR <= src_ERR_i;
+EB_TX_i.ACK <= src_ACK_i;
+
+master_cyc_o <= DEBUG_WB_master_o.CYC;
+master_we_o <= DEBUG_WB_master_o.WE;
+master_stb_o <= DEBUG_WB_master_o.STB;
+master_sel_o <= DEBUG_WB_master_o.SEL;
+master_adr_o <= DEBUG_WB_master_o.ADR;
+master_dat_o <= DEBUG_WB_master_o.DAT;
+WB_master_i.DAT <= master_dat_i;
+WB_master_i.STALL <= master_stall_i;
+WB_master_i.ACK <= master_ack_i;
+
+
+
+-- ext interface to cfg space
+EXT_2_CFG_slave.CYC <= cfg_slave_cyc_i;
+EXT_2_CFG_slave.STB <= cfg_slave_stb_i;
+EXT_2_CFG_slave.WE <= cfg_slave_we_i;
+EXT_2_CFG_slave.SEL <= cfg_slave_sel_i;
+EXT_2_CFG_slave.ADR <= cfg_slave_adr_i;
+EXT_2_CFG_slave.DAT <= cfg_slave_dat_i;
+
+cfg_slave_ack_o <= CFG_2_EXT_slave.ACK;
+cfg_slave_stall_o <= CFG_2_EXT_slave.STALL;
+cfg_slave_err_o <= CFG_2_EXT_slave.ERR;
+cfg_slave_dat_o <= CFG_2_EXT_slave.DAT;
+
+
+
+
+src_adr_o <= (others => '0');
+src_sel_o <= (others => '1');
+
+master : if(g_master_slave = 1) generate
+
+ minimaster : eb_mini_master
+ port map(
+ --general
+ clk_i => clk_i,
+ nRst_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i => RXCTRL_2_EB_wb_slave,
+ EB_RX_o => EB_2_RXCTRL_wb_slave,
+
+ EB_TX_i => TXCTRL_2_EB_wb_master,
+ EB_TX_o => EB_2_TXCTRL_wb_master,
+
+ byte_count_rx_i => RXCTRL_2_TXCTRL_TOL,
+
+ dst_MAC_o => RXCTRL_2_TXCTRL_reply_MAC,
+ dst_IP_o => RXCTRL_2_TXCTRL_reply_IP,
+ dst_PORT_o => RXCTRL_2_TXCTRL_reply_PORT,
+ TOL_o => RXCTRL_2_TXCTRL_TOL,
+ hex_switch_i => hex_switch_i,
+ valid_o => RXCTRL_2_TXCTRL_valid
+ );
+
+ TXCTRL : EB_TX_CTRL
+ port map
+ (
+ clk_i => clk_i,
+ nRST_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i => EB_2_TXCTRL_wb_slave,
+ wb_slave_o => TXCTRL_2_EB_wb_slave,
+
+ TX_master_o => EB_TX_o,
+ TX_master_i => EB_TX_i, --!
+
+ reply_MAC_i => RXCTRL_2_TXCTRL_reply_MAC,
+ reply_IP_i => RXCTRL_2_TXCTRL_reply_IP,
+ reply_PORT_i => RXCTRL_2_TXCTRL_reply_PORT,
+
+ TOL_i => RXCTRL_2_TXCTRL_TOL,
+
+ valid_i => RXCTRL_2_TXCTRL_valid
+
+ );
+
+
+ RXCTRL: EB_RX_CTRL port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ wb_master_i => EB_2_RXCTRL_wb_master,
+ wb_master_o => RXCTRL_2_EB_wb_master,
+
+ RX_slave_o => EB_RX_o,
+ RX_slave_i => EB_RX_i,
+
+ reply_MAC_o => open,
+ reply_IP_o => open,
+ reply_PORT_o => open,
+ TOL_o => open,
+ valid_o => open);
+
+
+
+end generate;
+
+slave : if(g_master_slave = 0) generate
+
+ TXCTRL : EB_TX_CTRL
+ port map
+ (
+ clk_i => clk_i,
+ nRST_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i => EB_2_TXCTRL_wb_slave,
+ wb_slave_o => TXCTRL_2_EB_wb_slave,
+
+ TX_master_o => EB_TX_o,
+ TX_master_i => EB_TX_i, --!
+
+ reply_MAC_i => RXCTRL_2_TXCTRL_reply_MAC,
+ reply_IP_i => RXCTRL_2_TXCTRL_reply_IP,
+ reply_PORT_i => RXCTRL_2_TXCTRL_reply_PORT,
+
+ TOL_i => RXCTRL_2_TXCTRL_TOL,
+
+ valid_i => RXCTRL_2_TXCTRL_valid
+
+ );
+
+
+ RXCTRL: EB_RX_CTRL port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ wb_master_i => EB_2_RXCTRL_wb_master,
+ wb_master_o => RXCTRL_2_EB_wb_master,
+
+ RX_slave_o => EB_RX_o,
+ RX_slave_i => EB_RX_i,
+
+ reply_MAC_o => RXCTRL_2_TXCTRL_reply_MAC,
+ reply_IP_o => RXCTRL_2_TXCTRL_reply_IP,
+ reply_PORT_o => RXCTRL_2_TXCTRL_reply_PORT,
+ TOL_o => RXCTRL_2_TXCTRL_TOL,
+ valid_o => RXCTRL_2_TXCTRL_valid);
+
+
+
+
+ EB : eb_2_wb_converter
+ port map(
+ --general
+ clk_i => clk_i,
+ nRst_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i => RXCTRL_2_EB_wb_slave,
+ EB_RX_o => EB_2_RXCTRL_wb_slave,
+
+ EB_TX_i => TXCTRL_2_EB_wb_master,
+ EB_TX_o => EB_2_TXCTRL_wb_master,
+
+ byte_count_rx_i => RXCTRL_2_TXCTRL_TOL,
+
+ config_master_i => CFG_2_eb_slave,
+ config_master_o => eb_2_CFG_slave,
+
+ --WB IC signals
+ WB_master_i => WB_master_i,
+ WB_master_o => DEBUG_WB_master_o
+ );
+
+
+ s_status_en <= WB_master_i.ACK OR WB_master_i.ERR;
+ s_status_clr <= NOT DEBUG_WB_master_o.CYC;
+
+ cfg_space : eb_config
+ port map(
+ --general
+ clk_i => clk_i,
+ nRst_i => nRst_i,
+
+ status_i => WB_master_i.ERR,
+ status_en => s_status_en,
+ status_clr => s_status_clr,
+
+ my_mac_address_o => open,
+ my_ip_address_o => open,
+
+ local_slave_o => CFG_2_EXT_slave,
+ local_slave_i => EXT_2_CFG_slave,
+
+ eb_slave_o => CFG_2_eb_slave,
+ eb_slave_i => eb_2_CFG_slave
+ );
+
+
+
+end generate;
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_CORE.vhd.bak b/hdl/eb_testbench/EB_CORE.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..01f34e5daff070376294696b6f529609eb3c5b4f
--- /dev/null
+++ b/hdl/eb_testbench/EB_CORE.vhd.bak
@@ -0,0 +1,575 @@
+--! @file EB_CORE.vhd
+--! @brief Top file for EtherBone core
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.EB_HDR_PKG.all;
+--use work.EB_components_pkg.all;
+use work.wb32_package.all;
+use work.wb16_package.all;
+
+
+entity EB_CORE is
+generic(g_master_slave : natural := 0);
+port
+(
+ clk_i : in std_logic; --! clock input
+ nRst_i : in std_logic;
+
+ -- slave RX streaming IF -------------------------------------
+ snk_CYC_i : in std_logic; --
+ snk_STB_i : in std_logic; --
+ snk_DAT_i : in std_logic_vector(15 downto 0); --
+ snk_sel_i : in std_logic_vector(1 downto 0);
+ snk_adr_i : in std_logic_vector(1 downto 0);
+ snk_WE_i : in std_logic;
+ snk_STALL_o : out std_logic; --
+ snk_ERR_o : out std_logic; --
+ snk_ACK_o : out std_logic; --
+ --------------------------------------------------------------
+
+ -- master TX streaming IF ------------------------------------
+ src_CYC_o : out std_logic; --
+ src_STB_o : out std_logic; --
+ src_WE_o : out std_logic;
+ src_DAT_o : out std_logic_vector(15 downto 0); --
+ src_STALL_i : in std_logic; --
+ src_ERR_i : in std_logic; --
+ src_ACK_i : in std_logic; --
+ src_adr_o : out std_logic_vector(1 downto 0);
+
+ src_sel_o : out std_logic_vector(1 downto 0);
+ --------------------------------------------------------------
+ debug_TX_TOL_o : out std_logic_vector(15 downto 0);
+ hex_switch_i : in std_logic_vector(3 downto 0);
+
+ -- slave Cfg IF ----------------------------------------------
+ cfg_slave_cyc_i : in std_logic;
+cfg_slave_we_i : in std_logic;
+cfg_slave_stb_i : in std_logic;
+cfg_slave_sel_i : in std_logic_vector(3 downto 0);
+cfg_slave_adr_i : in std_logic_vector(31 downto 0);
+cfg_slave_dat_i : in std_logic_vector(31 downto 0);
+cfg_slave_dat_o : out std_logic_vector(31 downto 0);
+cfg_slave_stall_o : out std_logic;
+cfg_slave_ack_o : out std_logic;
+cfg_slave_err_o : out std_logic;
+
+ -- master IC IF ----------------------------------------------
+ master_cyc_o : out std_logic;
+ master_we_o : out std_logic;
+ master_stb_o : out std_logic;
+ master_sel_o : out std_logic_vector(3 downto 0);
+ master_adr_o : out std_logic_vector(31 downto 0);
+ master_dat_o : out std_logic_vector(31 downto 0);
+ master_dat_i : in std_logic_vector(31 downto 0);
+ master_stall_i : in std_logic;
+ master_ack_i : in std_logic
+ --------------------------------------------------------------
+
+);
+end EB_CORE;
+
+
+
+
+
+
+architecture behavioral of EB_CORE is
+
+s_status_en : std_logic;
+s_status_clr : std_logic;
+
+
+signal DEBUG_sink1_valid : std_logic;
+signal DEBUG_sink23_valid : std_logic;
+
+signal DEBUG_WB_master_o : wb32_master_out;
+signal WB_master_i : wb32_master_in;
+
+
+-- int eb if to cfg space
+signal eb_2_CFG_slave : wb32_slave_in;
+signal CFG_2_eb_slave : wb32_slave_out;
+
+
+-- ext if to cfg space
+signal EXT_2_CFG_slave : wb32_slave_in;
+signal CFG_2_EXT_slave : wb32_slave_out;
+
+
+
+-- TX CTRL <-> EBCORE signals
+
+signal EB_2_TXCTRL_wb_slave : wb32_slave_in;
+signal TXCTRL_2_EB_wb_slave : wb32_slave_out;
+
+
+
+signal EB_2_RXCTRL_wb_master : wb32_master_in;
+signal RXCTRL_2_EB_wb_master : wb32_master_out;
+
+-- RX CTRL <-> TXCTRL signals
+signal RXCTRL_2_TXCTRL_reply_MAC : std_logic_vector(47 downto 0);
+signal RXCTRL_2_TXCTRL_reply_IP : std_logic_vector(31 downto 0);
+signal RXCTRL_2_TXCTRL_reply_PORT : std_logic_vector(15 downto 0);
+signal RXCTRL_2_TXCTRL_TOL : std_logic_vector(15 downto 0);
+signal RXCTRL_2_TXCTRL_valid : std_logic;
+
+--EB <-> TXCTRL
+signal EB_2_TXCTRL_wb_master : wb32_master_out;
+signal TXCTRL_2_EB_wb_master : wb32_master_in;
+
+--EB <-> RXCTRL
+signal EB_2_RXCTRL_wb_slave : wb32_slave_out;
+signal RXCTRL_2_EB_wb_slave : wb32_slave_in;
+
+signal EB_RX_i : wb16_slave_in;
+signal EB_RX_o : wb16_slave_out;
+
+signal EB_TX_i : wb16_master_in;
+signal EB_TX_o : wb16_master_out;
+
+component binary_sink is
+generic(filename : string := "123.pcap"; wordsize : natural := 64; endian : natural := 0);
+port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+
+ rdy_o : out std_logic;
+
+ sample_i : in std_logic;
+ valid_i : in std_logic;
+ data_i : in std_logic_vector(wordsize-1 downto 0)
+);
+end component;
+
+
+
+component EB_TX_CTRL is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i : in wb32_slave_in;
+ wb_slave_o : out wb32_slave_out;
+
+ TX_master_o : out wb16_master_out; --! Wishbone master output lines
+ TX_master_i : in wb16_master_in; --!
+
+
+
+ reply_MAC_i : in std_logic_vector(47 downto 0);
+ reply_IP_i : in std_logic_vector(31 downto 0);
+ reply_PORT_i : in std_logic_vector(15 downto 0);
+
+ TOL_i : in std_logic_vector(15 downto 0);
+
+ valid_i : in std_logic
+
+);
+end component;
+
+component EB_RX_CTRL is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+
+ RX_slave_o : out wb16_slave_out; --! Wishbone master output lines
+ RX_slave_i : in wb16_slave_in; --!
+
+ --Eth MAC WB Streaming signals
+ wb_master_i : in wb32_master_in;
+ wb_master_o : out wb32_master_out;
+
+ reply_VLAN_o : out std_logic_vector(31 downto 0);
+ reply_MAC_o : out std_logic_vector(47 downto 0);
+ reply_IP_o : out std_logic_vector(31 downto 0);
+ reply_PORT_o : out std_logic_vector(15 downto 0);
+
+ TOL_o : out std_logic_vector(15 downto 0);
+
+
+ valid_o : out std_logic
+
+);
+end component;
+
+component eb_2_wb_converter is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i : in wb32_slave_in;
+ EB_RX_o : out wb32_slave_out;
+
+ EB_TX_i : in wb32_master_in;
+ EB_TX_o : out wb32_master_out;
+
+ byte_count_rx_i : in std_logic_vector(15 downto 0);
+
+ --config signals
+ config_master_i : in wb32_master_in; --! WB V4 interface to WB interconnect/device(s)
+ config_master_o : out wb32_master_out; --! WB V4 interface to WB interconnect/device(s)
+
+
+ --WB IC signals
+ WB_master_i : in wb32_master_in;
+ WB_master_o : out wb32_master_out
+
+);
+end component;
+
+component eb_config is
+ port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+ status_i : in std_logic;
+ status_en : in std_logic;
+ status_clr : in std_logic;
+
+ my_mac_address_o : out std_logic_vector(47 downto 0);
+ my_ip_address_o : out std_logic_vector(31 downto 0);
+
+ local_slave_o : out wb32_slave_out;
+ local_slave_i : in wb32_slave_in; --! local Wishbone master lines
+
+ eb_slave_o : out wb32_slave_out; --! EB Wishbone slave lines
+ eb_slave_i : in wb32_slave_in
+ );
+end component;
+
+
+component eb_mini_master is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i : in wb32_slave_in;
+ EB_RX_o : out wb32_slave_out;
+
+ EB_TX_i : in wb32_master_in;
+ EB_TX_o : out wb32_master_out;
+
+ byte_count_rx_i : in std_logic_vector(15 downto 0);
+
+ dst_MAC_o : out std_logic_vector(47 downto 0);
+ dst_IP_o : out std_logic_vector(31 downto 0);
+ dst_PORT_o : out std_logic_vector(15 downto 0);
+
+ TOL_o : out std_logic_vector(15 downto 0);
+ hex_switch_i : in std_logic_vector(3 downto 0);
+
+ valid_o : out std_logic
+
+);
+end component;
+
+
+ begin
+
+ debug_TX_TOL_o <= RXCTRL_2_TXCTRL_TOL;
+
+
+
+
+-- file_sink1: binary_sink generic map ( filename => "Eb_RX_data.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => RXCTRL_2_EB_wb_master.CYC,
+ -- valid_i => DEBUG_sink1_valid,
+ -- data_i => RXCTRL_2_EB_wb_master.DAT );
+
+-- file_sink2: binary_sink generic map ( filename => "Eb_WB_data_o.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => DEBUG_WB_master_o.CYC,
+ -- valid_i => DEBUG_sink23_valid,
+ -- data_i => DEBUG_WB_master_o.DAT );
+
+ -- file_sink3: binary_sink generic map ( filename => "Eb_WB_addr.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => DEBUG_WB_master_o.CYC,
+ -- valid_i => DEBUG_sink23_valid,
+ -- data_i => DEBUG_WB_master_o.ADR );
+
+ -- file_sink4: binary_sink generic map ( filename => "Eb_WB_data_i.dat",
+ -- wordsize => 32,
+ -- endian => 0)
+ -- port map ( clk_i => clk_i,
+ -- nRST_i => nRST_i,
+ -- rdy_o => open,
+ -- sample_i => DEBUG_WB_master_o.CYC,
+ -- valid_i => WB_master_i.ACK,
+ -- data_i => WB_master_i.DAT );
+
+
+ DEBUG_sink1_valid <= (RXCTRL_2_EB_wb_master.STB AND NOT EB_2_RXCTRL_wb_slave.STALL);
+ DEBUG_sink23_valid <= (DEBUG_WB_master_o.STB AND NOT WB_master_i.STALL);
+
+
+
+
+
+ -- EB type conversions for WB daisychain
+EB_2_TXCTRL_wb_slave <= wb32_slave_in(EB_2_TXCTRL_wb_master);
+TXCTRL_2_EB_wb_master <= wb32_master_in(TXCTRL_2_EB_wb_slave);
+
+EB_2_RXCTRL_wb_master <= wb32_master_in(EB_2_RXCTRL_wb_slave);
+RXCTRL_2_EB_wb_slave <= wb32_slave_in(RXCTRL_2_EB_wb_master);
+
+-- assign records to individual bus signals.
+-- slave RX
+EB_RX_i.CYC <= snk_CYC_i;
+EB_RX_i.STB <= snk_STB_i;
+EB_RX_i.DAT <= snk_DAT_i;
+EB_RX_i.WE <= snk_WE_i;
+snk_STALL_o <= EB_RX_o.STALL;
+snk_ERR_o <= EB_RX_o.ERR;
+snk_ACK_o <= EB_RX_o.ACK;
+
+-- master TX
+src_CYC_o <= EB_TX_o.CYC;
+src_STB_o <= EB_TX_o.STB;
+src_DAT_o <= EB_TX_o.DAT;
+src_WE_o <= EB_TX_o.WE;
+EB_TX_i.STALL <= src_STALL_i;
+EB_TX_i.ERR <= src_ERR_i;
+EB_TX_i.ACK <= src_ACK_i;
+
+master_cyc_o <= DEBUG_WB_master_o.CYC;
+master_we_o <= DEBUG_WB_master_o.WE;
+master_stb_o <= DEBUG_WB_master_o.STB;
+master_sel_o <= DEBUG_WB_master_o.SEL;
+master_adr_o <= DEBUG_WB_master_o.ADR;
+master_dat_o <= DEBUG_WB_master_o.DAT;
+WB_master_i.DAT <= master_dat_i;
+WB_master_i.STALL <= master_stall_i;
+WB_master_i.ACK <= master_ack_i;
+
+
+
+-- ext interface to cfg space
+EXT_2_CFG_slave.CYC <= cfg_slave_cyc_i;
+EXT_2_CFG_slave.STB <= cfg_slave_stb_i;
+EXT_2_CFG_slave.WE <= cfg_slave_we_i;
+EXT_2_CFG_slave.SEL <= cfg_slave_sel_i;
+EXT_2_CFG_slave.ADR <= cfg_slave_adr_i;
+EXT_2_CFG_slave.DAT <= cfg_slave_dat_i;
+
+cfg_slave_ack_o <= CFG_2_EXT_slave.ACK;
+cfg_slave_stall_o <= CFG_2_EXT_slave.STALL;
+cfg_slave_err_o <= CFG_2_EXT_slave.ERR;
+cfg_slave_dat_o <= CFG_2_EXT_slave.DAT;
+
+
+
+
+src_adr_o <= (others => '0');
+src_sel_o <= (others => '1');
+
+master : if(g_master_slave = 1) generate
+
+ minimaster : eb_mini_master
+ port map(
+ --general
+ clk_i => clk_i,
+ nRst_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i => RXCTRL_2_EB_wb_slave,
+ EB_RX_o => EB_2_RXCTRL_wb_slave,
+
+ EB_TX_i => TXCTRL_2_EB_wb_master,
+ EB_TX_o => EB_2_TXCTRL_wb_master,
+
+ byte_count_rx_i => RXCTRL_2_TXCTRL_TOL,
+
+ dst_MAC_o => RXCTRL_2_TXCTRL_reply_MAC,
+ dst_IP_o => RXCTRL_2_TXCTRL_reply_IP,
+ dst_PORT_o => RXCTRL_2_TXCTRL_reply_PORT,
+ TOL_o => RXCTRL_2_TXCTRL_TOL,
+ hex_switch_i => hex_switch_i,
+ valid_o => RXCTRL_2_TXCTRL_valid
+ );
+
+ TXCTRL : EB_TX_CTRL
+ port map
+ (
+ clk_i => clk_i,
+ nRST_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i => EB_2_TXCTRL_wb_slave,
+ wb_slave_o => TXCTRL_2_EB_wb_slave,
+
+ TX_master_o => EB_TX_o,
+ TX_master_i => EB_TX_i, --!
+
+ reply_MAC_i => RXCTRL_2_TXCTRL_reply_MAC,
+ reply_IP_i => RXCTRL_2_TXCTRL_reply_IP,
+ reply_PORT_i => RXCTRL_2_TXCTRL_reply_PORT,
+
+ TOL_i => RXCTRL_2_TXCTRL_TOL,
+
+ valid_i => RXCTRL_2_TXCTRL_valid
+
+ );
+
+
+ RXCTRL: EB_RX_CTRL port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ wb_master_i => EB_2_RXCTRL_wb_master,
+ wb_master_o => RXCTRL_2_EB_wb_master,
+
+ RX_slave_o => EB_RX_o,
+ RX_slave_i => EB_RX_i,
+
+ reply_MAC_o => open,
+ reply_IP_o => open,
+ reply_PORT_o => open,
+ TOL_o => open,
+ valid_o => open);
+
+
+
+end generate;
+
+slave : if(g_master_slave = 0) generate
+
+ TXCTRL : EB_TX_CTRL
+ port map
+ (
+ clk_i => clk_i,
+ nRST_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i => EB_2_TXCTRL_wb_slave,
+ wb_slave_o => TXCTRL_2_EB_wb_slave,
+
+ TX_master_o => EB_TX_o,
+ TX_master_i => EB_TX_i, --!
+
+ reply_MAC_i => RXCTRL_2_TXCTRL_reply_MAC,
+ reply_IP_i => RXCTRL_2_TXCTRL_reply_IP,
+ reply_PORT_i => RXCTRL_2_TXCTRL_reply_PORT,
+
+ TOL_i => RXCTRL_2_TXCTRL_TOL,
+
+ valid_i => RXCTRL_2_TXCTRL_valid
+
+ );
+
+
+ RXCTRL: EB_RX_CTRL port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ wb_master_i => EB_2_RXCTRL_wb_master,
+ wb_master_o => RXCTRL_2_EB_wb_master,
+
+ RX_slave_o => EB_RX_o,
+ RX_slave_i => EB_RX_i,
+
+ reply_MAC_o => RXCTRL_2_TXCTRL_reply_MAC,
+ reply_IP_o => RXCTRL_2_TXCTRL_reply_IP,
+ reply_PORT_o => RXCTRL_2_TXCTRL_reply_PORT,
+ TOL_o => RXCTRL_2_TXCTRL_TOL,
+ valid_o => RXCTRL_2_TXCTRL_valid);
+
+
+
+
+ EB : eb_2_wb_converter
+ port map(
+ --general
+ clk_i => clk_i,
+ nRst_i => nRst_i,
+
+ --Eth MAC WB Streaming signals
+ EB_RX_i => RXCTRL_2_EB_wb_slave,
+ EB_RX_o => EB_2_RXCTRL_wb_slave,
+
+ EB_TX_i => TXCTRL_2_EB_wb_master,
+ EB_TX_o => EB_2_TXCTRL_wb_master,
+
+ byte_count_rx_i => RXCTRL_2_TXCTRL_TOL,
+
+ config_master_i => CFG_2_eb_slave,
+ config_master_o => eb_2_CFG_slave,
+
+ --WB IC signals
+ WB_master_i => WB_master_i,
+ WB_master_o => DEBUG_WB_master_o
+ );
+
+
+ s_status_en <= WB_master_i.ACK OR WB_master_i.ERR;
+ s_status_clr <= NOT DEBUG_WB_master_o.CYC;
+
+ cfg_space : eb_config
+ port map(
+ --general
+ clk_i => clk_i,
+ nRst_i => nRst_i,
+
+ status_i => WB_master_i.ERR,
+ status_en => s_status_en,
+ status_clr => s_status_clr,
+
+ my_mac_address_o => open,
+ my_ip_address_o => open,
+
+ local_slave_o => CFG_2_EXT_slave,
+ local_slave_i => EXT_2_CFG_slave,
+
+ eb_slave_o => CFG_2_eb_slave,
+ eb_slave_i => eb_2_CFG_slave
+ );
+
+
+
+end generate;
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_HDR_pkg.vhd b/hdl/eb_testbench/EB_HDR_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..00b7a5aafb14ff35895a79180c5ad8f5a0e391f1
--- /dev/null
+++ b/hdl/eb_testbench/EB_HDR_pkg.vhd
@@ -0,0 +1,408 @@
+--! @file EB_HDR_pkg.vhd
+--! @brief EtherBone Header definitions - Eth, IPV4, UDP, EB
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+--use work.XXX.all;
+
+
+package EB_HDR_PKG is
+
+
+--Constants ------------------------
+constant c_MY_MAC : std_logic_vector(6*8-1 downto 0) := x"D15EA5EDBEEF";
+constant c_PREAMBLE : std_logic_vector(8*8-1 downto 0) := x"55555555555555D5";
+
+constant c_MY_IP : std_logic_vector(4*8-1 downto 0) := x"C0A80164"; -- fixed address for now. 192.168.1.100
+constant c_BROADCAST_IP : std_logic_vector(4*8-1 downto 0) := x"FFFFFFFF";
+constant c_PRO_UDP : std_logic_vector(1*8-1 downto 0) := x"11";
+
+constant c_EB_MAGIC_WORD : std_logic_vector(15 downto 0) := x"4E6F";
+constant c_EB_PORT : std_logic_vector(15 downto 0) := x"EBD0";
+constant c_EB_VER : std_logic_vector(3 downto 0) := x"1";
+constant c_MY_EB_PORT_SIZE : std_logic_vector(3 downto 0) := x"4";
+constant c_MY_EB_ADDR_SIZE : std_logic_vector(3 downto 0) := x"4";
+
+constant c_EB_PORT_SIZE_n : natural := 32;
+constant c_EB_ADDR_SIZE_n : natural := 32;
+
+
+constant c_ETH_HLEN : natural := 112;
+constant c_IPV4_HLEN : natural := 160;
+constant c_UDP_HLEN : natural := 64;
+constant c_HDR_LEN : natural := (c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)/8;
+-----------------------------------
+
+type ETH_HDR is record
+ --PRE_SFD : std_logic_vector((8*8)-1 downto 0);
+ DST : std_logic_vector((6*8)-1 downto 0);
+ SRC : std_logic_vector((6*8)-1 downto 0);
+ TPID : std_logic_vector((2*8)-1 downto 0);
+ PCP : std_logic_vector(2 downto 0);
+ CFI : std_logic;
+ VID : std_logic_vector(11 downto 0);
+ TYP : std_logic_vector((2*8)-1 downto 0);
+
+end record;
+
+--define IPV4 header
+type IPV4_HDR is record
+
+ -- RX only, use constant fields for TX --------
+ VER : std_logic_vector(3 downto 0);
+ IHL : std_logic_vector(3 downto 0);
+ TOS : std_logic_vector(7 downto 0);
+ TOL : std_logic_vector(15 downto 0);
+ ID : std_logic_vector(15 downto 0);
+ FLG : std_logic_vector(2 downto 0);
+ FRO : std_logic_vector(12 downto 0);
+ TTL : std_logic_vector(7 downto 0);
+ PRO : std_logic_vector(7 downto 0);
+ SUM : std_logic_vector(15 downto 0);
+ SRC : std_logic_vector(31 downto 0);
+ DST : std_logic_vector(31 downto 0);
+ --- options (optional) here
+end record;
+
+
+
+--define UDP header
+type UDP_HDR is record
+ SRC_PORT : std_logic_vector(15 downto 0);
+ DST_PORT : std_logic_vector(15 downto 0);
+ MLEN : std_logic_vector(15 downto 0);
+ SUM : std_logic_vector(15 downto 0);
+end record;
+
+--define Etherbone header
+type EB_HDR is record
+ EB_MAGIC : std_logic_vector(15 downto 0);
+ VER : std_logic_vector(3 downto 0);
+ RESERVED1 : std_logic_vector(1 downto 0);
+ PROBE_RES : std_logic;
+ PROBE : std_logic;
+ ADDR_SIZE : std_logic_vector(3 downto 0);
+ PORT_SIZE : std_logic_vector(3 downto 0);
+end record;
+
+type EB_CYC is record
+
+ BCA_CFG : std_logic;
+ RCA_CFG : std_logic;
+ RD_FIFO : std_logic;
+ RESERVED1 : std_logic;
+
+ DROP_CYC : std_logic;
+ WCA_CFG : std_logic;
+ WR_FIFO : std_logic;
+ RESERVED2 : std_logic;
+
+ RESERVED3 : std_logic_vector(7 downto 0);
+ WR_CNT : unsigned(7 downto 0);
+ RD_CNT : unsigned(7 downto 0);
+end record;
+
+
+
+
+--conversion function prototyes
+
+-- Eth
+function TO_ETH_HDR(X : std_logic_vector)
+return ETH_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : ETH_HDR)
+return std_logic_vector;
+
+function INIT_ETH_HDR(SRC_MAC : std_logic_vector)
+return ETH_HDR;
+
+
+-- IPV4
+function TO_IPV4_HDR(X : std_logic_vector)
+return IPV4_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : IPV4_HDR)
+return std_logic_vector;
+
+function INIT_IPV4_HDR(SRC_IP : std_logic_vector)
+return IPV4_HDR;
+
+-- UDP
+function TO_UDP_HDR(X : std_logic_vector)
+return UDP_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : UDP_HDR)
+return std_logic_vector;
+
+function INIT_UDP_HDR(SRC_PORT : std_logic_vector)
+return UDP_HDR;
+
+-- EB HDR
+function TO_EB_HDR(X : std_logic_vector)
+return EB_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : EB_HDR)
+return std_logic_vector;
+
+function INIT_EB_HDR
+return EB_HDR;
+
+-- EB CYC
+function TO_EB_CYC(X : std_logic_vector)
+return EB_CYC;
+
+function TO_STD_LOGIC_VECTOR(X : EB_CYC)
+return std_logic_vector;
+
+end EB_HDR_PKG;
+
+package body EB_HDR_PKG is
+
+--conversion functions
+
+-- ETH Functions
+-- check for VLAN tag
+function TO_ETH_HDR(X : std_logic_vector)
+return ETH_HDR is
+ variable tmp : ETH_HDR;
+ begin
+ tmp.DST := X(X'LEFT downto X'LENGTH-(6*8));
+ tmp.SRC := X(X'LEFT-(6*8) downto X'LENGTH-(12*8));
+
+-- if(X(X'LEFT-(12*8) downto X'LENGTH-(14*8)) = x"8100") then --VLAN tag detected
+-- tmp.TPID := X(X'LEFT-(12*8) downto X'LENGTH-(14*8));
+-- tmp.PCP := X(X'LEFT-(14*8) downto X'LENGTH-(14*8)-3);
+-- tmp.CFI := X(X'LENGTH-(14*8)-4);
+-- tmp.VID := X(X'LEFT-(14*8)-4 downto X'LENGTH-(16*8));
+-- tmp.TYP := X(X'LEFT-(16*8) downto X'LENGTH-(18*8));
+-- else
+
+ tmp.TYP := X(X'LEFT-(12*8) downto X'LENGTH-(14*8));
+ --end if;
+
+ return tmp;
+end function TO_ETH_HDR;
+
+
+
+function TO_STD_LOGIC_VECTOR(X : ETH_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector((6+6+2)*8-1 downto 0) := (others => '0');
+ begin
+
+ tmp := X.DST & X.SRC & X.TYP;
+
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+
+function INIT_ETH_HDR(SRC_MAC : std_logic_vector)
+return ETH_HDR is
+variable tmp : ETH_HDR;
+ begin
+ --tmp.PRE_SFD := c_PREAMBLE; -- 4
+ tmp.DST := (others => '1'); -- 4
+ tmp.SRC := SRC_MAC; -- 8
+ --tmp.TPID := (others => '0');
+ --tmp.PCP := (others => '0');
+ --tmp.CFI := '0';
+ --tmp.VID := (others => '0');
+ tmp.TYP := x"0800"; --type ID
+ return tmp;
+end function INIT_ETH_HDR;
+
+-- IPV4 functions
+
+function TO_STD_LOGIC_VECTOR(X : IPV4_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector(159 downto 0) := (others => '0');
+ begin
+ tmp := X.VER & X.IHL & X.TOS & X.TOL & X.ID & X.FLG & X.FRO & X.TTL & X.PRO & X.SUM & X.SRC & X.DST ;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function INIT_IPV4_HDR(SRC_IP : std_logic_vector) --loads constants into a given IPV4_HDR record
+return IPV4_HDR is
+variable tmp : IPV4_HDR;
+ begin
+ tmp.VER := x"4"; -- 4b
+ tmp.IHL := x"5"; -- 4b
+ tmp.TOS := x"00"; -- 8b
+ tmp.TOL := (others => '0'); --16b
+ tmp.ID := (others => '0'); --16b
+ tmp.FLG := "010"; -- 3b
+ tmp.FRO := (others => '0'); -- 0b
+ tmp.TTL := x"40"; -- 8b --64 Hops
+ tmp.PRO := c_PRO_UDP; -- 8b --UDP
+ --tmp.PRO := x"88"; -- 8b --UDP Lite
+ tmp.SUM := (others => '0'); --16b
+ tmp.SRC := SRC_IP; --32b -- SRC is already known
+ tmp.DST := (others => '1'); --32b
+
+ return tmp;
+end function INIT_IPV4_HDR;
+
+function TO_IPV4_HDR(X : std_logic_vector)
+return IPV4_HDR is
+ variable tmp : IPV4_HDR;
+ begin
+ tmp.VER := X(159 downto 156);
+ tmp.IHL := X(155 downto 152);
+ tmp.TOS := X(151 downto 144);
+ tmp.TOL := X(143 downto 128);
+ tmp.ID := X(127 downto 112);
+ tmp.FLG := X(111 downto 109);
+ tmp.FRO := X(108 downto 96);
+ tmp.TTL := X(95 downto 88);
+ tmp.PRO := X(87 downto 80);
+ tmp.SUM := X(79 downto 64);
+ tmp.SRC := X(63 downto 32);
+ tmp.DST := X(31 downto 0);
+
+ return tmp;
+end function TO_IPV4_HDR;
+
+-- END IPV4 --------------------------------------------------------------
+
+
+-- UDP functions
+function TO_STD_LOGIC_VECTOR(X : UDP_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector(63 downto 0) := (others => '0');
+ begin
+ tmp := X.SRC_PORT & X.DST_PORT & X.MLEN & X.SUM;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function TO_UDP_HDR(X : std_logic_vector)
+return UDP_HDR is
+ variable tmp : UDP_HDR;
+ begin
+ tmp.SRC_PORT := X(63 downto 48);
+ tmp.DST_PORT := X(47 downto 32);
+ tmp.MLEN := X(31 downto 16);
+ tmp.SUM := X(15 downto 0);
+ return tmp;
+end function TO_UDP_HDR;
+
+function INIT_UDP_HDR(SRC_PORT : std_logic_vector)
+return UDP_HDR is
+ variable tmp : UDP_HDR;
+ begin
+ tmp.SRC_PORT := SRC_PORT; --16 --E ther B one D ata 0 bject
+ tmp.DST_PORT := c_EB_PORT; --16 --E ther B one D ata 0 bject
+ tmp.MLEN := (others => '0'); --16
+ tmp.SUM := (others => '0'); --16
+ return tmp;
+end function INIT_UDP_HDR;
+
+-- END UDP -------------- END UDP ----------------------------------------
+
+-- EB functions
+function TO_EB_HDR(X : std_logic_vector)
+return EB_HDR is
+ variable tmp : EB_HDR;
+ begin
+
+ tmp.EB_MAGIC := X(31 downto 16);
+ tmp.VER := X(15 downto 12);
+ tmp.RESERVED1 := X(11 downto 10);
+ tmp.PROBE_RES := X(9);
+ tmp.PROBE := X(8);
+ tmp.ADDR_SIZE := X(7 downto 4);
+ tmp.PORT_SIZE := X(3 downto 0);
+ return tmp;
+end function TO_EB_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : EB_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector(31 downto 0) := (others => '0');
+ begin
+ tmp := X.EB_MAGIC & X.VER & X.RESERVED1 & X.PROBE_RES & X.PROBE & X.ADDR_SIZE & X.PORT_SIZE;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function INIT_EB_HDR
+return EB_HDR is
+ variable tmp : EB_HDR;
+ begin
+ tmp.EB_MAGIC := c_EB_MAGIC_WORD;--16
+ tmp.VER := c_EB_VER; -- 4
+ tmp.RESERVED1 := (others => '0'); -- reserved 3bit
+ tmp.PROBE_RES := '0';
+ tmp.PROBE := '0';
+ tmp.ADDR_SIZE := c_MY_EB_ADDR_SIZE; -- 4 -- 32 bit
+ tmp.PORT_SIZE := c_MY_EB_PORT_SIZE; -- 4
+ return tmp;
+end function INIT_EB_HDR;
+
+function TO_EB_CYC(X : std_logic_vector)
+return EB_CYC is
+ variable tmp : EB_CYC;
+ begin
+ tmp.BCA_CFG := X(31);
+ tmp.RCA_CFG := X(30);
+ tmp.RD_FIFO := X(29);
+ tmp.RESERVED1 := X(28);
+ tmp.DROP_CYC := X(27);
+ tmp.WCA_CFG := X(26);
+ tmp.WR_FIFO := X(25);
+ tmp.RESERVED2 := X(24);
+ tmp.RESERVED3 := X(23 downto 16);
+ tmp.WR_CNT := unsigned(X(15 downto 8));
+ tmp.RD_CNT := unsigned(X(7 downto 0));
+
+ return tmp;
+end function TO_EB_CYC;
+
+function TO_STD_LOGIC_VECTOR(X : EB_CYC)
+return std_logic_vector is
+ variable tmp : std_logic_vector(31 downto 0) := (others => '0');
+ begin
+ tmp := X.BCA_CFG & X.RCA_CFG & X.RD_FIFO & X.RESERVED1 & X.DROP_CYC & X.WCA_CFG & X.WR_FIFO & X.RESERVED2
+ & X.RESERVED3 & std_logic_vector(X.WR_CNT) & std_logic_vector(X.RD_CNT) ;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+
+-- END EB -------------- END EB ----------------------------------------
+
+----------------------------------------------------------------------------------
+
+end package body;
+
+
+
+
diff --git a/hdl/eb_testbench/EB_HDR_pkg.vhd.bak b/hdl/eb_testbench/EB_HDR_pkg.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..89d4a5532abaca996db2d83620dd5f827f98b858
--- /dev/null
+++ b/hdl/eb_testbench/EB_HDR_pkg.vhd.bak
@@ -0,0 +1,407 @@
+--! @file EB_HDR_pkg.vhd
+--! @brief EtherBone Header definitions - Eth, IPV4, UDP, EB
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+--use work.XXX.all;
+
+
+package EB_HDR_PKG is
+
+
+--Constants ------------------------
+constant c_MY_MAC : std_logic_vector(6*8-1 downto 0) := x"D15EA5EDBEEF";
+constant c_PREAMBLE : std_logic_vector(8*8-1 downto 0) := x"55555555555555D5";
+
+constant c_MY_IP : std_logic_vector(4*8-1 downto 0) := x"C0A80164"; -- fixed address for now. 192.168.1.100
+constant c_BROADCAST_IP : std_logic_vector(4*8-1 downto 0) := x"FFFFFFFF";
+constant c_PRO_UDP : std_logic_vector(1*8-1 downto 0) := x"11";
+
+constant c_EB_MAGIC_WORD : std_logic_vector(15 downto 0) := x"4E6F";
+constant c_EB_PORT : std_logic_vector(15 downto 0) := x"EBD0";
+constant c_EB_VER : std_logic_vector(3 downto 0) := x"1";
+constant c_MY_EB_PORT_SIZE : std_logic_vector(3 downto 0) := x"4";
+constant c_MY_EB_ADDR_SIZE : std_logic_vector(3 downto 0) := x"4";
+
+constant c_EB_PORT_SIZE_n : natural := 32;
+constant c_EB_ADDR_SIZE_n : natural := 32;
+
+
+constant c_ETH_HLEN : natural := 112;
+constant c_IPV4_HLEN : natural := 160;
+constant c_UDP_HLEN : natural := 64;
+constant c_HDR_LEN : natural := (c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)/8;
+-----------------------------------
+
+type ETH_HDR is record
+ --PRE_SFD : std_logic_vector((8*8)-1 downto 0);
+ DST : std_logic_vector((6*8)-1 downto 0);
+ SRC : std_logic_vector((6*8)-1 downto 0);
+ TPID : std_logic_vector((2*8)-1 downto 0);
+ PCP : std_logic_vector(2 downto 0);
+ CFI : std_logic;
+ VID : std_logic_vector(11 downto 0);
+ TYP : std_logic_vector((2*8)-1 downto 0);
+
+end record;
+
+--define IPV4 header
+type IPV4_HDR is record
+
+ -- RX only, use constant fields for TX --------
+ VER : std_logic_vector(3 downto 0);
+ IHL : std_logic_vector(3 downto 0);
+ TOS : std_logic_vector(7 downto 0);
+ TOL : std_logic_vector(15 downto 0);
+ ID : std_logic_vector(15 downto 0);
+ FLG : std_logic_vector(2 downto 0);
+ FRO : std_logic_vector(12 downto 0);
+ TTL : std_logic_vector(7 downto 0);
+ PRO : std_logic_vector(7 downto 0);
+ SUM : std_logic_vector(15 downto 0);
+ SRC : std_logic_vector(31 downto 0);
+ DST : std_logic_vector(31 downto 0);
+ --- options (optional) here
+end record;
+
+
+
+--define UDP header
+type UDP_HDR is record
+ SRC_PORT : std_logic_vector(15 downto 0);
+ DST_PORT : std_logic_vector(15 downto 0);
+ MLEN : std_logic_vector(15 downto 0);
+ SUM : std_logic_vector(15 downto 0);
+end record;
+
+--define Etherbone header
+type EB_HDR is record
+ EB_MAGIC : std_logic_vector(15 downto 0);
+ VER : std_logic_vector(3 downto 0);
+ RESERVED1 : std_logic_vector(1 downto 0);
+ PROBE_RES : std_logic;
+ PROBE : std_logic;
+ ADDR_SIZE : std_logic_vector(3 downto 0);
+ PORT_SIZE : std_logic_vector(3 downto 0);
+end record;
+
+type EB_CYC is record
+
+ BCA_CFG : std_logic;
+ RCA_CFG : std_logic;
+ RD_FIFO : std_logic;
+ RESERVED1 : std_logic;
+
+ DROP_CYC : std_logic;
+ WCA_CFG : std_logic;
+ WR_FIFO : std_logic;
+ RESERVED2 : std_logic;
+
+ RESERVED3 : std_logic_vector(7 downto 0);
+ WR_CNT : unsigned(7 downto 0);
+ RD_CNT : unsigned(7 downto 0);
+end record;
+
+
+
+
+--conversion function prototyes
+
+-- Eth
+function TO_ETH_HDR(X : std_logic_vector)
+return ETH_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : ETH_HDR)
+return std_logic_vector;
+
+function INIT_ETH_HDR(SRC_MAC : std_logic_vector)
+return ETH_HDR;
+
+
+-- IPV4
+function TO_IPV4_HDR(X : std_logic_vector)
+return IPV4_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : IPV4_HDR)
+return std_logic_vector;
+
+function INIT_IPV4_HDR(SRC_IP : std_logic_vector)
+return IPV4_HDR;
+
+-- UDP
+function TO_UDP_HDR(X : std_logic_vector)
+return UDP_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : UDP_HDR)
+return std_logic_vector;
+
+function INIT_UDP_HDR(SRC_PORT : std_logic_vector)
+return UDP_HDR;
+
+-- EB HDR
+function TO_EB_HDR(X : std_logic_vector)
+return EB_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : EB_HDR)
+return std_logic_vector;
+
+function INIT_EB_HDR
+return EB_HDR;
+
+-- EB CYC
+function TO_EB_CYC(X : std_logic_vector)
+return EB_CYC;
+
+function TO_STD_LOGIC_VECTOR(X : EB_CYC)
+return std_logic_vector;
+
+end EB_HDR_PKG;
+
+package body EB_HDR_PKG is
+
+--conversion functions
+
+-- ETH Functions
+-- check for VLAN tag
+function TO_ETH_HDR(X : std_logic_vector)
+return ETH_HDR is
+ variable tmp : ETH_HDR;
+ begin
+ tmp.DST := X(X'LEFT downto X'LENGTH-(6*8));
+ tmp.SRC := X(X'LEFT-(6*8) downto X'LENGTH-(12*8));
+
+-- if(X(X'LEFT-(12*8) downto X'LENGTH-(14*8)) = x"8100") then --VLAN tag detected
+-- tmp.TPID := X(X'LEFT-(12*8) downto X'LENGTH-(14*8));
+-- tmp.PCP := X(X'LEFT-(14*8) downto X'LENGTH-(14*8)-3);
+-- tmp.CFI := X(X'LENGTH-(14*8)-4);
+-- tmp.VID := X(X'LEFT-(14*8)-4 downto X'LENGTH-(16*8));
+-- tmp.TYP := X(X'LEFT-(16*8) downto X'LENGTH-(18*8));
+-- else
+
+ tmp.TYP := X(X'LEFT-(12*8) downto X'LENGTH-(14*8));
+ --end if;
+
+ return tmp;
+end function TO_ETH_HDR;
+
+
+
+function TO_STD_LOGIC_VECTOR(X : ETH_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector((6+6+2)*8-1 downto 0) := (others => '0');
+ begin
+
+ tmp := X.DST & X.SRC & X.TYP;
+
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+
+function INIT_ETH_HDR(SRC_MAC : std_logic_vector)
+return ETH_HDR is
+variable tmp : ETH_HDR;
+ begin
+ --tmp.PRE_SFD := c_PREAMBLE; -- 4
+ tmp.DST := (others => '1'); -- 4
+ tmp.SRC := SRC_MAC; -- 8
+ --tmp.TPID := (others => '0');
+ --tmp.PCP := (others => '0');
+ --tmp.CFI := '0';
+ --tmp.VID := (others => '0');
+ tmp.TYP := x"0800"; --type ID
+ return tmp;
+end function INIT_ETH_HDR;
+
+-- IPV4 functions
+
+function TO_STD_LOGIC_VECTOR(X : IPV4_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector(159 downto 0) := (others => '0');
+ begin
+ tmp := X.VER & X.IHL & X.TOS & X.TOL & X.ID & X.FLG & X.FRO & X.TTL & X.PRO & X.SUM & X.SRC & X.DST ;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function INIT_IPV4_HDR(SRC_IP : std_logic_vector) --loads constants into a given IPV4_HDR record
+return IPV4_HDR is
+variable tmp : IPV4_HDR;
+ begin
+ tmp.VER := x"4"; -- 4b
+ tmp.IHL := x"5"; -- 4b
+ tmp.TOS := x"00"; -- 8b
+ tmp.TOL := (others => '0'); --16b
+ tmp.ID := (others => '0'); --16b
+ tmp.FLG := "010"; -- 3b
+ tmp.FRO := (others => '0'); -- 0b
+ tmp.TTL := x"40"; -- 8b --64 Hops
+ tmp.PRO := c_PRO_UDP; -- 8b --UDP
+ --tmp.PRO := x"88"; -- 8b --UDP Lite
+ tmp.SUM := (others => '0'); --16b
+ tmp.SRC := SRC_IP; --32b -- SRC is already known
+ tmp.DST := (others => '1'); --32b
+
+ return tmp;
+end function INIT_IPV4_HDR;
+
+function TO_IPV4_HDR(X : std_logic_vector)
+return IPV4_HDR is
+ variable tmp : IPV4_HDR;
+ begin
+ tmp.VER := X(159 downto 156);
+ tmp.IHL := X(155 downto 152);
+ tmp.TOS := X(151 downto 144);
+ tmp.TOL := X(143 downto 128);
+ tmp.ID := X(127 downto 112);
+ tmp.FLG := X(111 downto 109);
+ tmp.FRO := X(108 downto 96);
+ tmp.TTL := X(95 downto 88);
+ tmp.PRO := X(87 downto 80);
+ tmp.SUM := X(79 downto 64);
+ tmp.SRC := X(63 downto 32);
+ tmp.DST := X(31 downto 0);
+
+ return tmp;
+end function TO_IPV4_HDR;
+
+-- END IPV4 --------------------------------------------------------------
+
+
+-- UDP functions
+function TO_STD_LOGIC_VECTOR(X : UDP_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector(63 downto 0) := (others => '0');
+ begin
+ tmp := X.SRC_PORT & X.DST_PORT & X.MLEN & X.SUM;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function TO_UDP_HDR(X : std_logic_vector)
+return UDP_HDR is
+ variable tmp : UDP_HDR;
+ begin
+ tmp.SRC_PORT := X(63 downto 48);
+ tmp.DST_PORT := X(47 downto 32);
+ tmp.MLEN := X(31 downto 16);
+ tmp.SUM := X(15 downto 0);
+ return tmp;
+end function TO_UDP_HDR;
+
+function INIT_UDP_HDR(SRC_PORT : std_logic_vector)
+return UDP_HDR is
+ variable tmp : UDP_HDR;
+ begin
+ tmp.SRC_PORT := SRC_PORT; --16 --E ther B one D ata 0 bject
+ tmp.DST_PORT := c_EB_PORT; --16 --E ther B one D ata 0 bject
+ tmp.MLEN := (others => '0'); --16
+ tmp.SUM := (others => '0'); --16
+ return tmp;
+end function INIT_UDP_HDR;
+
+-- END UDP -------------- END UDP ----------------------------------------
+
+-- EB functions
+function TO_EB_HDR(X : std_logic_vector)
+return EB_HDR is
+ variable tmp : EB_HDR;
+ begin
+
+ tmp.EB_MAGIC := X(31 downto 16);
+ tmp.VER := X(15 downto 12);
+ tmp.RESERVED1 := X(11 downto 10);
+ tmp.PROBE_RES := X(9);
+ tmp.PROBE := X(8);
+ tmp.ADDR_SIZE := X(7 downto 4);
+ tmp.PORT_SIZE := X(3 downto 0);
+ return tmp;
+end function TO_EB_HDR;
+
+function TO_STD_LOGIC_VECTOR(X : EB_HDR)
+return std_logic_vector is
+ variable tmp : std_logic_vector(31 downto 0) := (others => '0');
+ begin
+ tmp := X.EB_MAGIC & X.VER & X.RESERVED1 & X.PROBE_RES & X.PROBE & X.ADDR_SIZE & X.PORT_SIZE;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function INIT_EB_HDR
+return EB_HDR is
+ variable tmp : EB_HDR;
+ begin
+ tmp.EB_MAGIC := c_EB_MAGIC_WORD;--16
+ tmp.VER := c_EB_VER; -- 4
+ tmp.RESERVED1 := (others => '0'); -- reserved 3bit
+ tmp.PROBE := '0';
+ tmp.ADDR_SIZE := c_MY_EB_ADDR_SIZE; -- 4 -- 32 bit
+ tmp.PORT_SIZE := c_MY_EB_PORT_SIZE; -- 4
+ return tmp;
+end function INIT_EB_HDR;
+
+function TO_EB_CYC(X : std_logic_vector)
+return EB_CYC is
+ variable tmp : EB_CYC;
+ begin
+ tmp.BCA_CFG := X(31);
+ tmp.RCA_CFG := X(30);
+ tmp.RD_FIFO := X(29);
+ tmp.RESERVED1 := X(28);
+ tmp.DROP_CYC := X(27);
+ tmp.WCA_CFG := X(26);
+ tmp.WR_FIFO := X(25);
+ tmp.RESERVED2 := X(24);
+ tmp.RESERVED3 := X(23 downto 16);
+ tmp.WR_CNT := unsigned(X(15 downto 8));
+ tmp.RD_CNT := unsigned(X(7 downto 0));
+
+ return tmp;
+end function TO_EB_CYC;
+
+function TO_STD_LOGIC_VECTOR(X : EB_CYC)
+return std_logic_vector is
+ variable tmp : std_logic_vector(31 downto 0) := (others => '0');
+ begin
+ tmp := X.BCA_CFG & X.RCA_CFG & X.RD_FIFO & X.RESERVED1 & X.DROP_CYC & X.WCA_CFG & X.WR_FIFO & X.RESERVED2
+ & X.RESERVED3 & std_logic_vector(X.WR_CNT) & std_logic_vector(X.RD_CNT) ;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+
+-- END EB -------------- END EB ----------------------------------------
+
+----------------------------------------------------------------------------------
+
+end package body;
+
+
+
+
diff --git a/hdl/eb_testbench/EB_RX_CTRL.vhd b/hdl/eb_testbench/EB_RX_CTRL.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..37d033961cea260f276910c58fba3f1d4dd55a6f
--- /dev/null
+++ b/hdl/eb_testbench/EB_RX_CTRL.vhd
@@ -0,0 +1,396 @@
+--! @file EB_RX_CTRL.vhd
+--! @brief EtherBone RX Packet/Frame parser
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+--use work.EB_components_pkg.all;
+use work.wb32_package.all;
+use work.wb16_package.all;
+
+entity EB_RX_CTRL is
+generic(g_eth_deframer : STRING := "ACTIVE");
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+
+ RX_slave_o : out wb16_slave_out; --! Wishbone master output lines
+ RX_slave_i : in wb16_slave_in; --!
+
+ --Eth MAC WB Streaming signals
+ wb_master_i : in wb32_master_in;
+ wb_master_o : out wb32_master_out;
+
+ reply_VLAN_o : out std_logic_vector(31 downto 0);
+ reply_MAC_o : out std_logic_vector(47 downto 0);
+ reply_IP_o : out std_logic_vector(31 downto 0);
+ reply_PORT_o : out std_logic_vector(15 downto 0);
+
+ TOL_o : out std_logic_vector(15 downto 0);
+
+
+ valid_o : out std_logic
+
+);
+end entity;
+
+
+architecture behavioral of EB_RX_CTRL is
+
+component WB_bus_adapter_streaming_sg
+ generic(g_adr_width_A : natural := 32; g_adr_width_B : natural := 32;
+ g_dat_width_A : natural := 32; g_dat_width_B : natural := 16;
+ g_pipeline : natural
+ );
+ port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+ A_CYC_i : in std_logic;
+ A_STB_i : in std_logic;
+ A_ADR_i : in std_logic_vector(g_adr_width_A-1 downto 0);
+ A_SEL_i : in std_logic_vector(g_dat_width_A/8-1 downto 0);
+ A_WE_i : in std_logic;
+ A_DAT_i : in std_logic_vector(g_dat_width_A-1 downto 0);
+ A_ACK_o : out std_logic;
+ A_ERR_o : out std_logic;
+ A_RTY_o : out std_logic;
+ A_STALL_o : out std_logic;
+ A_DAT_o : out std_logic_vector(g_dat_width_A-1 downto 0);
+ B_CYC_o : out std_logic;
+ B_STB_o : out std_logic;
+ B_ADR_o : out std_logic_vector(g_adr_width_B-1 downto 0);
+ B_SEL_o : out std_logic_vector(g_dat_width_B/8-1 downto 0);
+ B_WE_o : out std_logic;
+ B_DAT_o : out std_logic_vector(g_dat_width_B-1 downto 0);
+ B_ACK_i : in std_logic;
+ B_ERR_i : in std_logic;
+ B_RTY_i : in std_logic;
+ B_STALL_i : in std_logic;
+ B_DAT_i : in std_logic_vector(g_dat_width_B-1 downto 0)
+ );
+ end component;
+
+component sipo_flag is
+generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ clr_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+ full_o : out std_logic;
+ empty_o : out std_logic
+);
+end component;
+
+signal conv_A : wb16_slave_out; --! Wishbone master output lines
+signal conv_B : wb32_master_out; --!
+
+
+-- main FSM
+type st is (IDLE, HDR_RECEIVE, CALC_CHKSUM, WAIT_STATE, CHECK_HDR, PAYLOAD_RECEIVE, ERROR);
+signal state_RX : st := IDLE;
+
+--split shift register output and convert to hdr records
+signal ETH_RX : ETH_HDR;
+signal IPV4_RX : IPV4_HDR;
+signal UDP_RX : UDP_HDR;
+signal RX_HDR_slv : std_logic_vector(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto 0);
+alias ETH_RX_slv : std_logic_vector(c_ETH_HLEN -1 downto 0) is RX_HDR_slv(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto c_IPV4_HLEN + c_UDP_HLEN);
+alias IPV4_RX_slv : std_logic_vector(c_IPV4_HLEN-1 downto 0) is RX_HDR_slv(c_IPV4_HLEN + c_UDP_HLEN-1 downto c_UDP_HLEN);
+alias UDP_RX_slv : std_logic_vector(c_UDP_HLEN-1 downto 0) is RX_HDR_slv(c_UDP_HLEN-1 downto 0);
+
+--forking the bus
+type stmux is (HEADER, PAYLOAD);
+signal state_mux : stmux := HEADER;
+signal RX_hdr_o : wb16_slave_out; --! Wishbone master output lines
+signal wb_payload_stb_o : wb32_master_out;
+
+--shift register input and control signals
+signal counter_input : unsigned(7 downto 0);
+signal sipo_clr : std_logic;
+signal sipo_full : std_logic;
+signal sipo_empty : std_logic;
+signal sipo_en : std_logic;
+
+--IP checksum check NOT USED ATM
+--signal p_chk_vals : std_logic_vector(95 downto 0);
+--signal s_chk_vals : std_logic_vector(15 downto 0);
+--signal IP_chk_sum : std_logic_vector(15 downto 0);
+signal calc_chk_en : std_logic;
+signal ld_p_chk_vals : std_logic; --parallel load
+signal counter_chksum : unsigned(7 downto 0);
+signal sh_chk_en : std_logic;
+-- signal en_i : std_logic;
+-- signal chksum_done : std_logic;
+
+signal PAYLOAD_STB_i : std_logic;
+signal PAYLOAD_CYC_i : std_logic;
+
+
+begin
+
+ETH_RX <= TO_ETH_HDR(ETH_RX_slv);
+IPV4_RX <= TO_IPV4_HDR(IPV4_RX_slv);
+UDP_RX <= TO_UDP_HDR(UDP_RX_slv);
+
+Shift_in: sipo_flag generic map (16, c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)
+ port map ( d_i => RX_slave_i.DAT,
+ q_o => RX_HDR_slv,
+ clk_i => clk_i,
+ nRST_i => nRST_i,
+ en_i => sipo_en,
+ clr_i => sipo_clr,
+ full_o => sipo_full,
+ empty_o => sipo_empty
+ );
+
+sh : sipo_en <= '1' when (sipo_full = '0' AND RX_slave_i.CYC = '1' AND RX_slave_i.STB = '1')
+ else '0';
+
+
+-- convert streaming input from 16 to 32 bit data width
+uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
+ g_adr_width_B => 32,
+ g_dat_width_A => 16,
+ g_dat_width_B => 32,
+ g_pipeline => 3)
+ port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ A_CYC_i => PAYLOAD_CYC_i,
+ A_STB_i => PAYLOAD_STB_i,
+ A_ADR_i => RX_slave_i.ADR,
+ A_SEL_i => RX_slave_i.SEL,
+ A_WE_i => RX_slave_i.WE,
+ A_DAT_i => RX_slave_i.DAT,
+ A_ACK_o => conv_A.ACK,
+ A_ERR_o => conv_A.ERR,
+ A_RTY_o => conv_A.RTY,
+ A_STALL_o => conv_A.STALL,
+ A_DAT_o => conv_A.DAT,
+ B_CYC_o => conv_B.CYC,
+ B_STB_o => conv_B.STB,
+ B_ADR_o => conv_B.ADR,
+ B_SEL_o => conv_B.SEL,
+ B_WE_o => conv_B.WE,
+ B_DAT_o => conv_B.DAT,
+ B_ACK_i => wb_master_i.ACK,
+ B_ERR_i => wb_master_i.ERR,
+ B_RTY_i => wb_master_i.RTY,
+ B_STALL_i => wb_master_i.STALL,
+ B_DAT_i => wb_master_i.DAT);
+
+
+
+RX_hdr_o.STALL <= sipo_full;
+
+MUX_RX : with state_mux select
+RX_slave_o <= conv_A when PAYLOAD,
+ RX_hdr_o when others;
+
+MUX_PAYLOADSTB : with state_mux select
+PAYLOAD_STB_i <= RX_slave_i.STB when PAYLOAD,
+ '0' when others;
+
+MUX_PAYLOADCYC : with state_mux select
+PAYLOAD_CYC_i <= RX_slave_i.CYC when PAYLOAD,
+ '0' when others;
+
+
+MUX_WB : with state_mux select
+wb_master_o <= conv_B when PAYLOAD,
+ wb_payload_stb_o when others;
+
+
+
+--postpone VLAN support
+--reply_VLAN_o <= ETH_RX.TPID & ETH_RX.PCP & ETH_RX.CFI & ETH_RX.VID;
+reply_MAC_o <= ETH_RX.SRC;
+reply_IP_o <= IPV4_RX.SRC;
+reply_PORT_o <= UDP_RX.SRC_PORT;
+TOL_o <= IPV4_RX.TOL;
+
+main_fsm : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+ --==========================================================================
+ if (nRST_i = '0') then
+
+ RX_hdr_o.ACK <= '0';
+
+ RX_hdr_o.ERR <= '0';
+ RX_hdr_o.DAT <= (others => '0');
+ RX_hdr_o.RTY <= '0';
+
+ wb_payload_stb_o.STB <= '0';
+ wb_payload_stb_o.CYC <= '1';
+ wb_payload_stb_o.WE <= '1';
+ wb_payload_stb_o.SEL <= (others => '1');
+ wb_payload_stb_o.ADR <= (others => '0');
+ wb_payload_stb_o.DAT <= (others => '0');
+
+
+ state_mux <= HEADER;
+
+
+ counter_input <= (others => '0');
+ counter_chksum <= (others => '0');
+ -- prepare chk sum field_RX_hdr, fill in reply IP and TOL field_RX_hdr when available
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+ else
+
+ sipo_clr <= '0';
+ valid_o <= '0';
+
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+
+
+
+
+ if((RX_slave_i.CYC = '0') AND NOT ((state_RX = PAYLOAD_RECEIVE) OR (state_RX = IDLE))) then --packet aborted before completion
+ state_RX <= ERROR;
+ else
+
+ case state_RX is
+ when IDLE => state_mux <= HEADER;
+ counter_chksum <= (others => '0');
+ counter_input <= (others => '0');
+ --sipo_clr <= '1';
+ if(RX_slave_i.CYC = '1' AND RX_slave_i.STB = '1') then
+
+ counter_input <= counter_chksum +1;
+ state_RX <= HDR_RECEIVE;
+ end if;
+
+ when HDR_RECEIVE => if(sipo_full = '1') then -- VLAN?
+ state_RX <= CHECK_HDR;
+ end if;
+
+
+ --if(RX_slave_i.DAT = x"8100") then
+
+
+
+ --counter_input <= counter_input + 1;
+
+
+ -- when CALC_CHKSUM => RX_hdr_o.STALL <= '1';
+ -- if(counter_chksum < 6) then
+ -- sh_chk_en <= '1';
+ -- calc_chk_en <= '1';
+ -- counter_chksum <= counter_chksum +1;
+ -- else
+ -- if(chksum_done = '1') then
+ -- state_RX <= WAIT_STATE;
+ -- end if;
+ -- end if;
+
+ when WAIT_STATE => state_RX <= CHECK_HDR;
+
+ when CHECK_HDR => --RX_hdr_o.STALL <= '1';
+ --if(ETH_RX.PRE_SFD = c_PREAMBLE) then
+ --if(IP_chksum = x"FFFF") then -- correct ?
+ --if(IPV4_RX.DST = c_MY_IP OR IPV4_RX.DST = c_BROADCAST_IP) then
+ --if(IPV4_RX.PRO = c_PRO_UDP) then
+ --if(UDP_RX.DST_PORT = c_EB_PORT) then
+ --copy info to TX for reply
+ if(ETH_RX.TYP = x"0800" AND IPV4_RX.PRO = x"11") then
+ valid_o <= '1';
+ --
+ state_mux <= PAYLOAD;
+ state_rx <= PAYLOAD_RECEIVE;
+ else
+ report("BAD PACKET HDR") severity Warning;
+ state_rx <= ERROR;
+ end if;
+ --set payload counter to UDP payload bytes => TOL - 20 - 8
+
+ --else
+ -- report("Wrong Port") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+ --else
+ -- report("Not UDP") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+ --else
+ --report("Wrong Dst IP") severity warning;
+ --state_rx <= ERROR;
+ --end if;
+ --else
+ -- report("Bad IP checksum") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+ --else
+ -- report("No Eth Preamble found") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+
+
+ when PAYLOAD_RECEIVE => if(RX_slave_i.CYC = '0') then
+ state_RX <= IDLE;
+ sipo_clr <= '1';
+ end if;
+
+ when ERROR => sipo_clr <= '1';
+ state_rx <= IDLE;
+
+ when others => state_RX <= IDLE;
+
+
+ end case;
+
+ end if;
+
+
+
+ end if;
+ end if;
+
+end process;
+
+
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_RX_CTRL.vhd.bak b/hdl/eb_testbench/EB_RX_CTRL.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..0a65722b3f1ba14817d1e9c67fcdcca5a71c48a1
--- /dev/null
+++ b/hdl/eb_testbench/EB_RX_CTRL.vhd.bak
@@ -0,0 +1,395 @@
+--! @file EB_RX_CTRL.vhd
+--! @brief EtherBone RX Packet/Frame parser
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+--use work.EB_components_pkg.all;
+use work.wb32_package.all;
+use work.wb16_package.all;
+
+entity EB_RX_CTRL is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+
+ RX_slave_o : out wb16_slave_out; --! Wishbone master output lines
+ RX_slave_i : in wb16_slave_in; --!
+
+ --Eth MAC WB Streaming signals
+ wb_master_i : in wb32_master_in;
+ wb_master_o : out wb32_master_out;
+
+ reply_VLAN_o : out std_logic_vector(31 downto 0);
+ reply_MAC_o : out std_logic_vector(47 downto 0);
+ reply_IP_o : out std_logic_vector(31 downto 0);
+ reply_PORT_o : out std_logic_vector(15 downto 0);
+
+ TOL_o : out std_logic_vector(15 downto 0);
+
+
+ valid_o : out std_logic
+
+);
+end entity;
+
+
+architecture behavioral of EB_RX_CTRL is
+
+component WB_bus_adapter_streaming_sg
+ generic(g_adr_width_A : natural := 32; g_adr_width_B : natural := 32;
+ g_dat_width_A : natural := 32; g_dat_width_B : natural := 16;
+ g_pipeline : natural
+ );
+ port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+ A_CYC_i : in std_logic;
+ A_STB_i : in std_logic;
+ A_ADR_i : in std_logic_vector(g_adr_width_A-1 downto 0);
+ A_SEL_i : in std_logic_vector(g_dat_width_A/8-1 downto 0);
+ A_WE_i : in std_logic;
+ A_DAT_i : in std_logic_vector(g_dat_width_A-1 downto 0);
+ A_ACK_o : out std_logic;
+ A_ERR_o : out std_logic;
+ A_RTY_o : out std_logic;
+ A_STALL_o : out std_logic;
+ A_DAT_o : out std_logic_vector(g_dat_width_A-1 downto 0);
+ B_CYC_o : out std_logic;
+ B_STB_o : out std_logic;
+ B_ADR_o : out std_logic_vector(g_adr_width_B-1 downto 0);
+ B_SEL_o : out std_logic_vector(g_dat_width_B/8-1 downto 0);
+ B_WE_o : out std_logic;
+ B_DAT_o : out std_logic_vector(g_dat_width_B-1 downto 0);
+ B_ACK_i : in std_logic;
+ B_ERR_i : in std_logic;
+ B_RTY_i : in std_logic;
+ B_STALL_i : in std_logic;
+ B_DAT_i : in std_logic_vector(g_dat_width_B-1 downto 0)
+ );
+ end component;
+
+component sipo_flag is
+generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ clr_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+ full_o : out std_logic;
+ empty_o : out std_logic
+);
+end component;
+
+signal conv_A : wb16_slave_out; --! Wishbone master output lines
+signal conv_B : wb32_master_out; --!
+
+
+-- main FSM
+type st is (IDLE, HDR_RECEIVE, CALC_CHKSUM, WAIT_STATE, CHECK_HDR, PAYLOAD_RECEIVE, ERROR);
+signal state_RX : st := IDLE;
+
+--split shift register output and convert to hdr records
+signal ETH_RX : ETH_HDR;
+signal IPV4_RX : IPV4_HDR;
+signal UDP_RX : UDP_HDR;
+signal RX_HDR_slv : std_logic_vector(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto 0);
+alias ETH_RX_slv : std_logic_vector(c_ETH_HLEN -1 downto 0) is RX_HDR_slv(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto c_IPV4_HLEN + c_UDP_HLEN);
+alias IPV4_RX_slv : std_logic_vector(c_IPV4_HLEN-1 downto 0) is RX_HDR_slv(c_IPV4_HLEN + c_UDP_HLEN-1 downto c_UDP_HLEN);
+alias UDP_RX_slv : std_logic_vector(c_UDP_HLEN-1 downto 0) is RX_HDR_slv(c_UDP_HLEN-1 downto 0);
+
+--forking the bus
+type stmux is (HEADER, PAYLOAD);
+signal state_mux : stmux := HEADER;
+signal RX_hdr_o : wb16_slave_out; --! Wishbone master output lines
+signal wb_payload_stb_o : wb32_master_out;
+
+--shift register input and control signals
+signal counter_input : unsigned(7 downto 0);
+signal sipo_clr : std_logic;
+signal sipo_full : std_logic;
+signal sipo_empty : std_logic;
+signal sipo_en : std_logic;
+
+--IP checksum check NOT USED ATM
+--signal p_chk_vals : std_logic_vector(95 downto 0);
+--signal s_chk_vals : std_logic_vector(15 downto 0);
+--signal IP_chk_sum : std_logic_vector(15 downto 0);
+signal calc_chk_en : std_logic;
+signal ld_p_chk_vals : std_logic; --parallel load
+signal counter_chksum : unsigned(7 downto 0);
+signal sh_chk_en : std_logic;
+-- signal en_i : std_logic;
+-- signal chksum_done : std_logic;
+
+signal PAYLOAD_STB_i : std_logic;
+signal PAYLOAD_CYC_i : std_logic;
+
+
+begin
+
+ETH_RX <= TO_ETH_HDR(ETH_RX_slv);
+IPV4_RX <= TO_IPV4_HDR(IPV4_RX_slv);
+UDP_RX <= TO_UDP_HDR(UDP_RX_slv);
+
+Shift_in: sipo_flag generic map (16, c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)
+ port map ( d_i => RX_slave_i.DAT,
+ q_o => RX_HDR_slv,
+ clk_i => clk_i,
+ nRST_i => nRST_i,
+ en_i => sipo_en,
+ clr_i => sipo_clr,
+ full_o => sipo_full,
+ empty_o => sipo_empty
+ );
+
+sh : sipo_en <= '1' when (sipo_full = '0' AND RX_slave_i.CYC = '1' AND RX_slave_i.STB = '1')
+ else '0';
+
+
+-- convert streaming input from 16 to 32 bit data width
+uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
+ g_adr_width_B => 32,
+ g_dat_width_A => 16,
+ g_dat_width_B => 32,
+ g_pipeline => 3)
+ port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ A_CYC_i => PAYLOAD_CYC_i,
+ A_STB_i => PAYLOAD_STB_i,
+ A_ADR_i => RX_slave_i.ADR,
+ A_SEL_i => RX_slave_i.SEL,
+ A_WE_i => RX_slave_i.WE,
+ A_DAT_i => RX_slave_i.DAT,
+ A_ACK_o => conv_A.ACK,
+ A_ERR_o => conv_A.ERR,
+ A_RTY_o => conv_A.RTY,
+ A_STALL_o => conv_A.STALL,
+ A_DAT_o => conv_A.DAT,
+ B_CYC_o => conv_B.CYC,
+ B_STB_o => conv_B.STB,
+ B_ADR_o => conv_B.ADR,
+ B_SEL_o => conv_B.SEL,
+ B_WE_o => conv_B.WE,
+ B_DAT_o => conv_B.DAT,
+ B_ACK_i => wb_master_i.ACK,
+ B_ERR_i => wb_master_i.ERR,
+ B_RTY_i => wb_master_i.RTY,
+ B_STALL_i => wb_master_i.STALL,
+ B_DAT_i => wb_master_i.DAT);
+
+
+
+RX_hdr_o.STALL <= sipo_full;
+
+MUX_RX : with state_mux select
+RX_slave_o <= conv_A when PAYLOAD,
+ RX_hdr_o when others;
+
+MUX_PAYLOADSTB : with state_mux select
+PAYLOAD_STB_i <= RX_slave_i.STB when PAYLOAD,
+ '0' when others;
+
+MUX_PAYLOADCYC : with state_mux select
+PAYLOAD_CYC_i <= RX_slave_i.CYC when PAYLOAD,
+ '0' when others;
+
+
+MUX_WB : with state_mux select
+wb_master_o <= conv_B when PAYLOAD,
+ wb_payload_stb_o when others;
+
+
+
+--postpone VLAN support
+--reply_VLAN_o <= ETH_RX.TPID & ETH_RX.PCP & ETH_RX.CFI & ETH_RX.VID;
+reply_MAC_o <= ETH_RX.SRC;
+reply_IP_o <= IPV4_RX.SRC;
+reply_PORT_o <= UDP_RX.SRC_PORT;
+TOL_o <= IPV4_RX.TOL;
+
+main_fsm : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+ --==========================================================================
+ if (nRST_i = '0') then
+
+ RX_hdr_o.ACK <= '0';
+
+ RX_hdr_o.ERR <= '0';
+ RX_hdr_o.DAT <= (others => '0');
+ RX_hdr_o.RTY <= '0';
+
+ wb_payload_stb_o.STB <= '0';
+ wb_payload_stb_o.CYC <= '1';
+ wb_payload_stb_o.WE <= '1';
+ wb_payload_stb_o.SEL <= (others => '1');
+ wb_payload_stb_o.ADR <= (others => '0');
+ wb_payload_stb_o.DAT <= (others => '0');
+
+
+ state_mux <= HEADER;
+
+
+ counter_input <= (others => '0');
+ counter_chksum <= (others => '0');
+ -- prepare chk sum field_RX_hdr, fill in reply IP and TOL field_RX_hdr when available
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+ else
+
+ sipo_clr <= '0';
+ valid_o <= '0';
+
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+
+
+
+
+ if((RX_slave_i.CYC = '0') AND NOT ((state_RX = PAYLOAD_RECEIVE) OR (state_RX = IDLE))) then --packet aborted before completion
+ state_RX <= ERROR;
+ else
+
+ case state_RX is
+ when IDLE => state_mux <= HEADER;
+ counter_chksum <= (others => '0');
+ counter_input <= (others => '0');
+ --sipo_clr <= '1';
+ if(RX_slave_i.CYC = '1' AND RX_slave_i.STB = '1') then
+
+ counter_input <= counter_chksum +1;
+ state_RX <= HDR_RECEIVE;
+ end if;
+
+ when HDR_RECEIVE => if(sipo_full = '1') then -- VLAN?
+ state_RX <= CHECK_HDR;
+ end if;
+
+
+ --if(RX_slave_i.DAT = x"8100") then
+
+
+
+ --counter_input <= counter_input + 1;
+
+
+ -- when CALC_CHKSUM => RX_hdr_o.STALL <= '1';
+ -- if(counter_chksum < 6) then
+ -- sh_chk_en <= '1';
+ -- calc_chk_en <= '1';
+ -- counter_chksum <= counter_chksum +1;
+ -- else
+ -- if(chksum_done = '1') then
+ -- state_RX <= WAIT_STATE;
+ -- end if;
+ -- end if;
+
+ when WAIT_STATE => state_RX <= CHECK_HDR;
+
+ when CHECK_HDR => --RX_hdr_o.STALL <= '1';
+ --if(ETH_RX.PRE_SFD = c_PREAMBLE) then
+ --if(IP_chksum = x"FFFF") then -- correct ?
+ --if(IPV4_RX.DST = c_MY_IP OR IPV4_RX.DST = c_BROADCAST_IP) then
+ --if(IPV4_RX.PRO = c_PRO_UDP) then
+ --if(UDP_RX.DST_PORT = c_EB_PORT) then
+ --copy info to TX for reply
+ if(ETH_RX.TYP = x"0800" AND IPV4_RX.PRO = x"11") then
+ valid_o <= '1';
+ --
+ state_mux <= PAYLOAD;
+ state_rx <= PAYLOAD_RECEIVE;
+ else
+ report("BAD PACKET HDR") severity Warning;
+ state_rx <= ERROR;
+ end if;
+ --set payload counter to UDP payload bytes => TOL - 20 - 8
+
+ --else
+ -- report("Wrong Port") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+ --else
+ -- report("Not UDP") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+ --else
+ --report("Wrong Dst IP") severity warning;
+ --state_rx <= ERROR;
+ --end if;
+ --else
+ -- report("Bad IP checksum") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+ --else
+ -- report("No Eth Preamble found") severity warning;
+ -- state_rx <= ERROR;
+ --end if;
+
+
+ when PAYLOAD_RECEIVE => if(RX_slave_i.CYC = '0') then
+ state_RX <= IDLE;
+ sipo_clr <= '1';
+ end if;
+
+ when ERROR => sipo_clr <= '1';
+ state_rx <= IDLE;
+
+ when others => state_RX <= IDLE;
+
+
+ end case;
+
+ end if;
+
+
+
+ end if;
+ end if;
+
+end process;
+
+
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_TX_CTRL.vhd b/hdl/eb_testbench/EB_TX_CTRL.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c42469067f8634ad4c91875860e4034dacec04d5
--- /dev/null
+++ b/hdl/eb_testbench/EB_TX_CTRL.vhd
@@ -0,0 +1,441 @@
+--! @file EB_TX_CTRL.vhd
+--! @brief EtherBone TX Packet/Frame Builder
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+use work.wb32_package.all;
+use work.wb16_package.all;
+
+entity EB_TX_CTRL is
+generic(g_eth_framer : STRING := "ACTIVE");
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i : in wb32_slave_in;
+ wb_slave_o : out wb32_slave_out;
+
+ TX_master_o : out wb16_master_out; --! Wishbone master output lines
+ TX_master_i : in wb16_master_in; --!
+
+
+
+ reply_MAC_i : in std_logic_vector(47 downto 0);
+ reply_IP_i : in std_logic_vector(31 downto 0);
+ reply_PORT_i : in std_logic_vector(15 downto 0);
+
+ TOL_i : in std_logic_vector(15 downto 0);
+
+ valid_i : in std_logic
+
+);
+end entity;
+
+
+architecture behavioral of EB_TX_CTRL is
+
+component EB_checksum is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ en_i : in std_logic;
+ data_i : in std_logic_vector(15 downto 0);
+
+ done_o : out std_logic;
+ sum_o : out std_logic_vector(15 downto 0)
+);
+end component;
+
+component WB_bus_adapter_streaming_sg
+ generic(g_adr_width_A : natural := 32; g_adr_width_B : natural := 32;
+ g_dat_width_A : natural := 32; g_dat_width_B : natural := 16;
+ g_pipeline : natural
+ );
+ port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+ A_CYC_i : in std_logic;
+ A_STB_i : in std_logic;
+ A_ADR_i : in std_logic_vector(g_adr_width_A-1 downto 0);
+ A_SEL_i : in std_logic_vector(g_dat_width_A/8-1 downto 0);
+ A_WE_i : in std_logic;
+ A_DAT_i : in std_logic_vector(g_dat_width_A-1 downto 0);
+ A_ACK_o : out std_logic;
+ A_ERR_o : out std_logic;
+ A_RTY_o : out std_logic;
+ A_STALL_o : out std_logic;
+ A_DAT_o : out std_logic_vector(g_dat_width_A-1 downto 0);
+ B_CYC_o : out std_logic;
+ B_STB_o : out std_logic;
+ B_ADR_o : out std_logic_vector(g_adr_width_B-1 downto 0);
+ B_SEL_o : out std_logic_vector(g_dat_width_B/8-1 downto 0);
+ B_WE_o : out std_logic;
+ B_DAT_o : out std_logic_vector(g_dat_width_B-1 downto 0);
+ B_ACK_i : in std_logic;
+ B_ERR_i : in std_logic;
+ B_RTY_i : in std_logic;
+ B_STALL_i : in std_logic;
+ B_DAT_i : in std_logic_vector(g_dat_width_B-1 downto 0)
+ );
+ end component;
+
+component piso_flag is
+generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ ld_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+ full_o : out std_logic;
+ empty_o : out std_logic
+);
+ end component;
+
+signal conv_B : wb16_master_out; --! Wishbone master output lines
+signal conv_A : wb32_slave_out; --!
+
+-- main FSM
+type st is (IDLE, CALC_CHKSUM, WAIT_SEND_REQ, HDR_SEND, PAYLOAD_SEND, WAIT_IFGAP);
+signal state_tx : st := IDLE;
+
+-- convert shift register input from hdr records to standard logic vectors and join them
+signal ETH_TX : ETH_HDR;
+signal IPV4_TX : IPV4_HDR;
+signal UDP_TX : UDP_HDR;
+signal TX_HDR_slv : std_logic_vector(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto 0);
+alias ETH_TX_slv : std_logic_vector(c_ETH_HLEN-1 downto 0) is TX_HDR_slv(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto c_IPV4_HLEN + c_UDP_HLEN);
+alias IPV4_TX_slv : std_logic_vector(c_IPV4_HLEN-1 downto 0) is TX_HDR_slv(c_IPV4_HLEN + c_UDP_HLEN-1 downto c_UDP_HLEN);
+alias UDP_TX_slv : std_logic_vector(c_UDP_HLEN-1 downto 0) is TX_HDR_slv(c_UDP_HLEN-1 downto 0);
+
+--shift register output and control signals
+signal s_out : std_logic_vector(31 downto 0);
+signal sh_hdr_en : std_logic;
+signal ld_hdr : std_logic;
+signal counter_ouput : unsigned(7 downto 0);
+
+signal chksum_empty : std_logic;
+signal hdr_empty : std_logic;
+signal chksum_full : std_logic;
+signal hdr_full : std_logic;
+
+
+-- forking the bus
+type stmux is (HEADER, PAYLOAD);
+signal state_mux : stmux := HEADER;
+signal TX_hdr_o : wb16_master_out; --! Wishbone master output lines
+signal wb_payload_stall_o : wb32_slave_out;
+signal stalled : std_logic;
+
+-- IP checksum generator
+signal counter_chksum : unsigned(7 downto 0);
+signal p_chk_vals : std_logic_vector(95 downto 0);
+signal s_chk_vals : std_logic_vector(15 downto 0);
+signal IP_chk_sum : std_logic_vector(15 downto 0);
+signal sh_chk_en : std_logic;
+signal calc_chk_en : std_logic;
+signal ld_p_chk_vals : std_logic; --parallel load
+signal chksum_done : std_logic;
+
+signal DEBUG_cmp_chksum : IPV4_HDR;
+
+signal PISO_STALL : std_logic;
+
+function calc_ip_chksum(input : IPV4_HDR)
+return IPV4_HDR is
+ variable tmp : unsigned(c_IPV4_HLEN-1 downto 0);
+ variable output : IPV4_HDR;
+ variable tmp_sum : unsigned(31 downto 0) := (others => '0');
+ variable tmp_slice : unsigned(15 downto 0);
+ begin
+ tmp := unsigned(to_std_logic_vector(input));
+ for i in c_IPV4_HLEN/16-1 downto 0 loop
+ tmp_slice := tmp((i+1)*16-1 downto i*16);
+ tmp_sum := tmp_sum + (x"0000" & tmp_slice);
+ end loop;
+ tmp_sum := (x"0000" & tmp_sum(15 downto 0)) + (x"0000" + tmp_sum(31 downto 16));
+ output.SUM := std_logic_vector(NOT(tmp_sum(15 downto 0) + tmp_sum(31 downto 16)));
+ return output;
+end function calc_ip_chksum;
+
+begin
+
+ETH_TX_slv <= TO_STD_LOGIC_VECTOR(ETH_TX);
+IPV4_TX_slv <= TO_STD_LOGIC_VECTOR(IPV4_TX);
+UDP_TX_slv <= TO_STD_LOGIC_VECTOR(UDP_TX);
+
+
+MUX_TX : with state_mux select
+TX_master_o <= conv_B when PAYLOAD,
+ TX_hdr_o when others;
+
+MUX_WB : with state_mux select
+wb_slave_o <= conv_A when others; --wb_payload_stall_o when HEADER,
+
+
+
+MUX_PISO : with state_mux select
+PISO_STALL <= '1' when HEADER,
+ TX_master_i.STALL when others;
+
+
+shift_hdr_chk_sum : piso_flag generic map( 96, 16)
+port map ( d_i => p_chk_vals,
+ q_o => s_chk_vals,
+ clk_i => clk_i,
+ nRST_i => nRST_i,
+ en_i => sh_chk_en,
+ ld_i => ld_p_chk_vals,
+ full_o => chksum_full,
+ empty_o => chksum_empty
+);
+
+p_chk_vals <= x"C511" & IPV4_TX.SRC & IPV4_TX.DST & IPV4_TX.TOL;
+
+chksum_generator: EB_checksum port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ en_i => calc_chk_en,
+ data_i => s_chk_vals,
+ done_o => chksum_done,
+ sum_o => IP_chk_sum );
+
+
+
+
+
+
+Shift_out: piso_flag generic map (c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN, 16)
+ port map ( d_i => TX_HDR_slv ,
+ q_o => TX_hdr_o.DAT,
+ clk_i => clk_i,
+ nRST_i => nRST_i,
+ en_i => sh_hdr_en ,
+ ld_i => ld_hdr,
+ full_o => hdr_full,
+ empty_o => hdr_empty
+ );
+
+
+
+
+
+
+-- convert streaming input from 16 to 32 bit data width
+uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
+ g_adr_width_B => 32,
+ g_dat_width_A => 32,
+ g_dat_width_B => 16,
+ g_pipeline => 3)
+ port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ A_CYC_i => wb_slave_i.CYC,
+ A_STB_i => wb_slave_i.STB,
+ A_ADR_i => wb_slave_i.ADR,
+ A_SEL_i => wb_slave_i.SEL,
+ A_WE_i => wb_slave_i.WE,
+ A_DAT_i => wb_slave_i.DAT,
+ A_ACK_o => conv_A.ACK,
+ A_ERR_o => conv_A.ERR,
+ A_RTY_o => conv_A.RTY,
+ A_STALL_o => conv_A.STALL,
+ A_DAT_o => conv_A.DAT,
+ B_CYC_o => conv_B.CYC,
+ B_STB_o => conv_B.STB,
+ B_ADR_o => conv_B.ADR,
+ B_SEL_o => conv_B.SEL,
+ B_WE_o => conv_B.WE,
+ B_DAT_o => conv_B.DAT,
+ B_ACK_i => TX_master_i.ACK,
+ B_ERR_i => TX_master_i.ERR,
+ B_RTY_i => TX_master_i.RTY,
+ B_STALL_i => PISO_STALL,
+ B_DAT_i => TX_master_i.DAT);
+
+
+
+
+
+TX_hdr_o.STB <= '1' when state_tx = HDR_SEND AND hdr_empty = '0'
+else '0';
+
+
+main_fsm : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+ --==========================================================================
+ if (nRST_i = '0') then
+ ETH_TX <= INIT_ETH_HDR(c_MY_MAC);
+ IPV4_TX <= INIT_IPV4_HDR(c_MY_IP);
+ UDP_TX <= INIT_UDP_HDR(c_EB_PORT);
+
+ IPV4_TX.TOL <= std_logic_vector(to_unsigned(112, 16));
+
+ TX_hdr_o.CYC <= '0';
+ --TX_hdr_o.STB <= '0';
+ TX_hdr_o.WE <= '1';
+ TX_hdr_o.ADR <= (others => '0');
+ TX_hdr_o.SEL <= (others => '1');
+
+ wb_payload_stall_o.STALL <= '1';
+ wb_payload_stall_o.ACK <= '0';
+ wb_payload_stall_o.DAT <= (others => '0');
+ wb_payload_stall_o.ERR <= '0';
+ wb_payload_stall_o.RTY <= '0';
+
+ state_mux <= HEADER;
+
+ sh_hdr_en <= '0';
+ ld_hdr <= '0';
+ stalled <= '0';
+ counter_ouput <= (others => '0');
+ counter_chksum <= (others => '0');
+ -- prepare chk sum field_tx_hdr, fill in reply IP and TOL field_tx_hdr when available
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+ else
+
+ --TX_hdr_o.STB <= '0';
+
+ ld_hdr <= '0';
+ sh_hdr_en <= '0';
+
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+
+ case state_tx is
+ when IDLE => ETH_TX <= INIT_ETH_HDR (c_MY_MAC);
+ IPV4_TX <= INIT_IPV4_HDR(c_MY_IP);
+ UDP_TX <= INIT_UDP_HDR (c_EB_PORT);
+ state_mux <= HEADER;
+ counter_chksum <= (others => '0');
+ counter_ouput <= (others => '0');
+
+ if(valid_i = '1') then
+ ETH_TX.DST <= reply_MAC_i;
+ IPV4_TX.DST <= reply_IP_i;
+ IPV4_TX.TOL <= TOL_i;
+ UDP_TX.MLEN <= std_logic_vector(unsigned(TOL_i)-((c_ETH_HLEN + c_IPV4_HLEN)/8));
+ UDP_TX.DST_PORT <= reply_PORT_i;
+ ld_p_chk_vals <= '1';
+ state_tx <= CALC_CHKSUM;
+ end if;
+
+ when CALC_CHKSUM => if(chksum_empty = '0') then
+ sh_chk_en <= '1';
+ calc_chk_en <= '1';
+ counter_chksum <= counter_chksum +1;
+ else
+ if(chksum_done = '1') then
+ DEBUG_cmp_chksum <= calc_ip_chksum(IPV4_TX);
+ IPV4_TX.SUM <= IP_chk_sum;
+ ld_hdr <= '1';
+ state_tx <= WAIT_SEND_REQ;
+ end if;
+ end if;
+
+ when WAIT_SEND_REQ => state_mux <= HEADER;
+ if(wb_slave_i.CYC = '1') then
+ TX_hdr_o.CYC <= '1';
+ --TX_hdr_o.STB <= '1';
+ sh_hdr_en <= '1';
+ state_tx <= HDR_SEND;
+ end if;
+
+
+ when HDR_SEND => if(hdr_empty = '0') then
+ --TX_hdr_o.STB <= '1';
+ if(TX_master_i.STALL = '0') then
+
+ sh_hdr_en <= '1';
+ counter_ouput <= counter_ouput +1;
+ end if;
+
+ -- if(TX_master_i.STALL = '1') then
+ -- stalled <= '1';
+
+ -- else
+ -- --TX_hdr_o.STB <= '1';
+ -- if(stalled = '1') then
+ -- stalled <= '0';
+ -- else
+ -- sh_TX_en <= '1';
+ -- counter_ouput <= counter_ouput +1;
+ -- end if;
+ -- end if;
+ else
+ --TX_hdr_o.STB <= '0';
+ state_mux <= PAYLOAD;
+ state_tx <= PAYLOAD_SEND;
+ end if;
+
+ when PAYLOAD_SEND => if(wb_slave_i.CYC = '0' AND conv_B.STB = '0' AND TX_master_i.STALL = '0') then
+ state_tx <= WAIT_IFGAP;
+ state_mux <= HEADER;
+ TX_hdr_o.CYC <= '0';
+ end if;
+
+ when WAIT_IFGAP => --ensure interframe gap
+ if(counter_ouput < 10) then
+ counter_ouput <= counter_ouput +1;
+ else
+ state_tx <= IDLE;
+ end if;
+
+ when others => state_tx <= IDLE;
+
+
+ end case;
+
+
+
+
+ end if;
+ end if;
+
+end process;
+
+
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_TX_CTRL.vhd.bak b/hdl/eb_testbench/EB_TX_CTRL.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..87c33343fc06f91e786985d3dd4078069f0f214c
--- /dev/null
+++ b/hdl/eb_testbench/EB_TX_CTRL.vhd.bak
@@ -0,0 +1,441 @@
+--! @file EB_TX_CTRL.vhd
+--! @brief EtherBone TX Packet/Frame Builder
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+use work.wb32_package.all;
+use work.wb16_package.all;
+
+entity EB_TX_CTRL is
+generic(g_eth_framer : STRING := "ACTIVE")
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ --Eth MAC WB Streaming signals
+ wb_slave_i : in wb32_slave_in;
+ wb_slave_o : out wb32_slave_out;
+
+ TX_master_o : out wb16_master_out; --! Wishbone master output lines
+ TX_master_i : in wb16_master_in; --!
+
+
+
+ reply_MAC_i : in std_logic_vector(47 downto 0);
+ reply_IP_i : in std_logic_vector(31 downto 0);
+ reply_PORT_i : in std_logic_vector(15 downto 0);
+
+ TOL_i : in std_logic_vector(15 downto 0);
+
+ valid_i : in std_logic
+
+);
+end entity;
+
+
+architecture behavioral of EB_TX_CTRL is
+
+component EB_checksum is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ en_i : in std_logic;
+ data_i : in std_logic_vector(15 downto 0);
+
+ done_o : out std_logic;
+ sum_o : out std_logic_vector(15 downto 0)
+);
+end component;
+
+component WB_bus_adapter_streaming_sg
+ generic(g_adr_width_A : natural := 32; g_adr_width_B : natural := 32;
+ g_dat_width_A : natural := 32; g_dat_width_B : natural := 16;
+ g_pipeline : natural
+ );
+ port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+ A_CYC_i : in std_logic;
+ A_STB_i : in std_logic;
+ A_ADR_i : in std_logic_vector(g_adr_width_A-1 downto 0);
+ A_SEL_i : in std_logic_vector(g_dat_width_A/8-1 downto 0);
+ A_WE_i : in std_logic;
+ A_DAT_i : in std_logic_vector(g_dat_width_A-1 downto 0);
+ A_ACK_o : out std_logic;
+ A_ERR_o : out std_logic;
+ A_RTY_o : out std_logic;
+ A_STALL_o : out std_logic;
+ A_DAT_o : out std_logic_vector(g_dat_width_A-1 downto 0);
+ B_CYC_o : out std_logic;
+ B_STB_o : out std_logic;
+ B_ADR_o : out std_logic_vector(g_adr_width_B-1 downto 0);
+ B_SEL_o : out std_logic_vector(g_dat_width_B/8-1 downto 0);
+ B_WE_o : out std_logic;
+ B_DAT_o : out std_logic_vector(g_dat_width_B-1 downto 0);
+ B_ACK_i : in std_logic;
+ B_ERR_i : in std_logic;
+ B_RTY_i : in std_logic;
+ B_STALL_i : in std_logic;
+ B_DAT_i : in std_logic_vector(g_dat_width_B-1 downto 0)
+ );
+ end component;
+
+component piso_flag is
+generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ ld_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+ full_o : out std_logic;
+ empty_o : out std_logic
+);
+ end component;
+
+signal conv_B : wb16_master_out; --! Wishbone master output lines
+signal conv_A : wb32_slave_out; --!
+
+-- main FSM
+type st is (IDLE, CALC_CHKSUM, WAIT_SEND_REQ, HDR_SEND, PAYLOAD_SEND, WAIT_IFGAP);
+signal state_tx : st := IDLE;
+
+-- convert shift register input from hdr records to standard logic vectors and join them
+signal ETH_TX : ETH_HDR;
+signal IPV4_TX : IPV4_HDR;
+signal UDP_TX : UDP_HDR;
+signal TX_HDR_slv : std_logic_vector(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto 0);
+alias ETH_TX_slv : std_logic_vector(c_ETH_HLEN-1 downto 0) is TX_HDR_slv(c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN-1 downto c_IPV4_HLEN + c_UDP_HLEN);
+alias IPV4_TX_slv : std_logic_vector(c_IPV4_HLEN-1 downto 0) is TX_HDR_slv(c_IPV4_HLEN + c_UDP_HLEN-1 downto c_UDP_HLEN);
+alias UDP_TX_slv : std_logic_vector(c_UDP_HLEN-1 downto 0) is TX_HDR_slv(c_UDP_HLEN-1 downto 0);
+
+--shift register output and control signals
+signal s_out : std_logic_vector(31 downto 0);
+signal sh_hdr_en : std_logic;
+signal ld_hdr : std_logic;
+signal counter_ouput : unsigned(7 downto 0);
+
+signal chksum_empty : std_logic;
+signal hdr_empty : std_logic;
+signal chksum_full : std_logic;
+signal hdr_full : std_logic;
+
+
+-- forking the bus
+type stmux is (HEADER, PAYLOAD);
+signal state_mux : stmux := HEADER;
+signal TX_hdr_o : wb16_master_out; --! Wishbone master output lines
+signal wb_payload_stall_o : wb32_slave_out;
+signal stalled : std_logic;
+
+-- IP checksum generator
+signal counter_chksum : unsigned(7 downto 0);
+signal p_chk_vals : std_logic_vector(95 downto 0);
+signal s_chk_vals : std_logic_vector(15 downto 0);
+signal IP_chk_sum : std_logic_vector(15 downto 0);
+signal sh_chk_en : std_logic;
+signal calc_chk_en : std_logic;
+signal ld_p_chk_vals : std_logic; --parallel load
+signal chksum_done : std_logic;
+
+signal DEBUG_cmp_chksum : IPV4_HDR;
+
+signal PISO_STALL : std_logic;
+
+function calc_ip_chksum(input : IPV4_HDR)
+return IPV4_HDR is
+ variable tmp : unsigned(c_IPV4_HLEN-1 downto 0);
+ variable output : IPV4_HDR;
+ variable tmp_sum : unsigned(31 downto 0) := (others => '0');
+ variable tmp_slice : unsigned(15 downto 0);
+ begin
+ tmp := unsigned(to_std_logic_vector(input));
+ for i in c_IPV4_HLEN/16-1 downto 0 loop
+ tmp_slice := tmp((i+1)*16-1 downto i*16);
+ tmp_sum := tmp_sum + (x"0000" & tmp_slice);
+ end loop;
+ tmp_sum := (x"0000" & tmp_sum(15 downto 0)) + (x"0000" + tmp_sum(31 downto 16));
+ output.SUM := std_logic_vector(NOT(tmp_sum(15 downto 0) + tmp_sum(31 downto 16)));
+ return output;
+end function calc_ip_chksum;
+
+begin
+
+ETH_TX_slv <= TO_STD_LOGIC_VECTOR(ETH_TX);
+IPV4_TX_slv <= TO_STD_LOGIC_VECTOR(IPV4_TX);
+UDP_TX_slv <= TO_STD_LOGIC_VECTOR(UDP_TX);
+
+
+MUX_TX : with state_mux select
+TX_master_o <= conv_B when PAYLOAD,
+ TX_hdr_o when others;
+
+MUX_WB : with state_mux select
+wb_slave_o <= conv_A when others; --wb_payload_stall_o when HEADER,
+
+
+
+MUX_PISO : with state_mux select
+PISO_STALL <= '1' when HEADER,
+ TX_master_i.STALL when others;
+
+
+shift_hdr_chk_sum : piso_flag generic map( 96, 16)
+port map ( d_i => p_chk_vals,
+ q_o => s_chk_vals,
+ clk_i => clk_i,
+ nRST_i => nRST_i,
+ en_i => sh_chk_en,
+ ld_i => ld_p_chk_vals,
+ full_o => chksum_full,
+ empty_o => chksum_empty
+);
+
+p_chk_vals <= x"C511" & IPV4_TX.SRC & IPV4_TX.DST & IPV4_TX.TOL;
+
+chksum_generator: EB_checksum port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ en_i => calc_chk_en,
+ data_i => s_chk_vals,
+ done_o => chksum_done,
+ sum_o => IP_chk_sum );
+
+
+
+
+
+
+Shift_out: piso_flag generic map (c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN, 16)
+ port map ( d_i => TX_HDR_slv ,
+ q_o => TX_hdr_o.DAT,
+ clk_i => clk_i,
+ nRST_i => nRST_i,
+ en_i => sh_hdr_en ,
+ ld_i => ld_hdr,
+ full_o => hdr_full,
+ empty_o => hdr_empty
+ );
+
+
+
+
+
+
+-- convert streaming input from 16 to 32 bit data width
+uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
+ g_adr_width_B => 32,
+ g_dat_width_A => 32,
+ g_dat_width_B => 16,
+ g_pipeline => 3)
+ port map ( clk_i => clk_i,
+ nRst_i => nRst_i,
+ A_CYC_i => wb_slave_i.CYC,
+ A_STB_i => wb_slave_i.STB,
+ A_ADR_i => wb_slave_i.ADR,
+ A_SEL_i => wb_slave_i.SEL,
+ A_WE_i => wb_slave_i.WE,
+ A_DAT_i => wb_slave_i.DAT,
+ A_ACK_o => conv_A.ACK,
+ A_ERR_o => conv_A.ERR,
+ A_RTY_o => conv_A.RTY,
+ A_STALL_o => conv_A.STALL,
+ A_DAT_o => conv_A.DAT,
+ B_CYC_o => conv_B.CYC,
+ B_STB_o => conv_B.STB,
+ B_ADR_o => conv_B.ADR,
+ B_SEL_o => conv_B.SEL,
+ B_WE_o => conv_B.WE,
+ B_DAT_o => conv_B.DAT,
+ B_ACK_i => TX_master_i.ACK,
+ B_ERR_i => TX_master_i.ERR,
+ B_RTY_i => TX_master_i.RTY,
+ B_STALL_i => PISO_STALL,
+ B_DAT_i => TX_master_i.DAT);
+
+
+
+
+
+TX_hdr_o.STB <= '1' when state_tx = HDR_SEND AND hdr_empty = '0'
+else '0';
+
+
+main_fsm : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+
+ --==========================================================================
+ -- SYNC RESET
+ --==========================================================================
+ if (nRST_i = '0') then
+ ETH_TX <= INIT_ETH_HDR(c_MY_MAC);
+ IPV4_TX <= INIT_IPV4_HDR(c_MY_IP);
+ UDP_TX <= INIT_UDP_HDR(c_EB_PORT);
+
+ IPV4_TX.TOL <= std_logic_vector(to_unsigned(112, 16));
+
+ TX_hdr_o.CYC <= '0';
+ --TX_hdr_o.STB <= '0';
+ TX_hdr_o.WE <= '1';
+ TX_hdr_o.ADR <= (others => '0');
+ TX_hdr_o.SEL <= (others => '1');
+
+ wb_payload_stall_o.STALL <= '1';
+ wb_payload_stall_o.ACK <= '0';
+ wb_payload_stall_o.DAT <= (others => '0');
+ wb_payload_stall_o.ERR <= '0';
+ wb_payload_stall_o.RTY <= '0';
+
+ state_mux <= HEADER;
+
+ sh_hdr_en <= '0';
+ ld_hdr <= '0';
+ stalled <= '0';
+ counter_ouput <= (others => '0');
+ counter_chksum <= (others => '0');
+ -- prepare chk sum field_tx_hdr, fill in reply IP and TOL field_tx_hdr when available
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+ else
+
+ --TX_hdr_o.STB <= '0';
+
+ ld_hdr <= '0';
+ sh_hdr_en <= '0';
+
+ ld_p_chk_vals <= '0';
+ sh_chk_en <= '0';
+ calc_chk_en <= '0';
+
+ case state_tx is
+ when IDLE => ETH_TX <= INIT_ETH_HDR (c_MY_MAC);
+ IPV4_TX <= INIT_IPV4_HDR(c_MY_IP);
+ UDP_TX <= INIT_UDP_HDR (c_EB_PORT);
+ state_mux <= HEADER;
+ counter_chksum <= (others => '0');
+ counter_ouput <= (others => '0');
+
+ if(valid_i = '1') then
+ ETH_TX.DST <= reply_MAC_i;
+ IPV4_TX.DST <= reply_IP_i;
+ IPV4_TX.TOL <= TOL_i;
+ UDP_TX.MLEN <= std_logic_vector(unsigned(TOL_i)-((c_ETH_HLEN + c_IPV4_HLEN)/8));
+ UDP_TX.DST_PORT <= reply_PORT_i;
+ ld_p_chk_vals <= '1';
+ state_tx <= CALC_CHKSUM;
+ end if;
+
+ when CALC_CHKSUM => if(chksum_empty = '0') then
+ sh_chk_en <= '1';
+ calc_chk_en <= '1';
+ counter_chksum <= counter_chksum +1;
+ else
+ if(chksum_done = '1') then
+ DEBUG_cmp_chksum <= calc_ip_chksum(IPV4_TX);
+ IPV4_TX.SUM <= IP_chk_sum;
+ ld_hdr <= '1';
+ state_tx <= WAIT_SEND_REQ;
+ end if;
+ end if;
+
+ when WAIT_SEND_REQ => state_mux <= HEADER;
+ if(wb_slave_i.CYC = '1') then
+ TX_hdr_o.CYC <= '1';
+ --TX_hdr_o.STB <= '1';
+ sh_hdr_en <= '1';
+ state_tx <= HDR_SEND;
+ end if;
+
+
+ when HDR_SEND => if(hdr_empty = '0') then
+ --TX_hdr_o.STB <= '1';
+ if(TX_master_i.STALL = '0') then
+
+ sh_hdr_en <= '1';
+ counter_ouput <= counter_ouput +1;
+ end if;
+
+ -- if(TX_master_i.STALL = '1') then
+ -- stalled <= '1';
+
+ -- else
+ -- --TX_hdr_o.STB <= '1';
+ -- if(stalled = '1') then
+ -- stalled <= '0';
+ -- else
+ -- sh_TX_en <= '1';
+ -- counter_ouput <= counter_ouput +1;
+ -- end if;
+ -- end if;
+ else
+ --TX_hdr_o.STB <= '0';
+ state_mux <= PAYLOAD;
+ state_tx <= PAYLOAD_SEND;
+ end if;
+
+ when PAYLOAD_SEND => if(wb_slave_i.CYC = '0' AND conv_B.STB = '0' AND TX_master_i.STALL = '0') then
+ state_tx <= WAIT_IFGAP;
+ state_mux <= HEADER;
+ TX_hdr_o.CYC <= '0';
+ end if;
+
+ when WAIT_IFGAP => --ensure interframe gap
+ if(counter_ouput < 10) then
+ counter_ouput <= counter_ouput +1;
+ else
+ state_tx <= IDLE;
+ end if;
+
+ when others => state_tx <= IDLE;
+
+
+ end case;
+
+
+
+
+ end if;
+ end if;
+
+end process;
+
+
+
+end behavioral;
diff --git a/hdl/eb_testbench/EB_checksum.vhd b/hdl/eb_testbench/EB_checksum.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..08e8ae7bc6484ca8a593164d29ad2804e2d6686b
--- /dev/null
+++ b/hdl/eb_testbench/EB_checksum.vhd
@@ -0,0 +1,116 @@
+--! @file EB_checksum.vhd
+--! @brief IP checksum generator for EtherBone
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--! Additional library
+library work;
+--! Additional packages
+use work.EB_HDR_PKG.all;
+
+entity EB_checksum is
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ en_i : in std_logic;
+ data_i : in std_logic_vector(15 downto 0);
+
+ done_o : out std_logic;
+ sum_o : out std_logic_vector(15 downto 0)
+);
+end EB_checksum;
+
+architecture behavioral of EB_checksum is
+
+constant c_width_int : integer := 28;
+
+type st is (IDLE, ADDUP, CARRIES, FINALISE, OUTPUT);
+
+signal state : st := IDLE;
+signal sum : unsigned(c_width_int-1 downto 0);
+signal data : std_logic_vector(15 downto 0);
+
+begin
+
+adder: process(clk_i)
+begin
+ if rising_edge(clk_i) then
+ --==========================================================================
+ -- SYNC RESET
+ --==========================================================================
+ if (nRST_i = '0') then
+ done_o <= '0';
+ sum <= (others => '0');
+ state <= IDLE;
+
+ else
+ --register input data
+ data <= data_i;
+ sum_o <= NOT(std_logic_vector(sum(15 downto 0)));
+
+ case state is
+ when IDLE => --clear internal states and output
+ done_o <= '0';
+ sum <= (others => '0');
+
+ -- if enable flag is set, start checksum generation
+ if(en_i = '1') then
+ state <= ADDUP;
+ end if;
+
+ when ADDUP => -- add up all incoming 16 bit words
+ sum <= sum + resize(unsigned(data), c_width_int);
+
+ -- end of data block. add carry bits from hi word to low word
+ if(en_i = '0') then
+ state <= CARRIES;
+ end if;
+
+ when CARRIES => sum <= resize(sum(15 downto 0), c_width_int) + resize(sum(c_width_int-1 downto 16), c_width_int);
+ state <= FINALISE;
+
+ when FINALISE => -- add carry bits from hi word to low word again, in case last sum produced overflow
+ sum <= resize(sum(15 downto 0), c_width_int) + resize(sum(c_width_int-1 downto 16), c_width_int);
+ state <= OUTPUT;
+
+ when OUTPUT => -- invert sum lo word, write to output. assert done flag
+ done_o <= '1';
+ state <= IDLE;
+
+ when others => state <= IDLE;
+ end case;
+ end if;
+ end if;
+
+end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/Makefile b/hdl/eb_testbench/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..3422519029d4721e8d0fce120f8b7f2a3a3e828b
--- /dev/null
+++ b/hdl/eb_testbench/Makefile
@@ -0,0 +1,1440 @@
+########################################
+# This file was generated by hdlmake #
+# http://ohwr.org/projects/hdl-make/ #
+########################################
+
+## variables #############################
+PWD := $(shell pwd)
+
+MODELSIM_INI_PATH := /opt/hdl/modeltech
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini
+VSIM_FLAGS :=
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini
+VERILOG_SRC := main.sv \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
+
+VERILOG_OBJ := work/main/.main_sv \
+work/sockit_owm/.sockit_owm_v \
+work/spi_clgen/.spi_clgen_v \
+work/spi_shift/.spi_shift_v \
+work/spi_top/.spi_top_v \
+work/lm32_allprofiles/.lm32_allprofiles_v \
+work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
+work/jtag_cores/.jtag_cores_v \
+work/lm32_adder/.lm32_adder_v \
+work/lm32_addsub/.lm32_addsub_v \
+work/lm32_dp_ram/.lm32_dp_ram_v \
+work/lm32_logic_op/.lm32_logic_op_v \
+work/lm32_ram/.lm32_ram_v \
+work/lm32_shifter/.lm32_shifter_v \
+work/lm32_multiplier/.lm32_multiplier_v \
+work/jtag_tap/.jtag_tap_v \
+
+VHDL_SRC := ../../modules/fabric/wr_fabric_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
+../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
+../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd \
+../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd \
+../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
+../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+../../modules/mini_bone/mini_bone.vhd \
+../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+../../modules/fabric/xwb_fabric_source.vhd \
+../../modules/wr_tbi_phy/dec_8b10b.vhd \
+../../modules/wr_tbi_phy/enc_8b10b.vhd \
+../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
+../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
+../../modules/timing/dmtd_phase_meas.vhd \
+../../modules/timing/dmtd_with_deglitcher.vhd \
+../../modules/timing/multi_dmtd_with_deglitcher.vhd \
+../../modules/timing/hpll_period_detect.vhd \
+../../modules/wr_mini_nic/minic_packet_buffer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+../../modules/wr_mini_nic/wr_mini_nic.vhd \
+../../modules/wr_mini_nic/xwr_mini_nic.vhd \
+../../modules/wr_softpll/softpll_wb.vhd \
+../../modules/wr_softpll/wr_softpll.vhd \
+../../modules/wr_softpll/xwr_softpll.vhd \
+../../modules/wr_endpoint/ep_registers_pkg.vhd \
+../../modules/wr_endpoint/endpoint_private_pkg.vhd \
+../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
+../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
+../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
+../../modules/wr_endpoint/ep_autonegotiation.vhd \
+../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
+../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
+../../modules/wr_endpoint/ep_rx_path.vhd \
+../../modules/wr_endpoint/ep_rx_wb_master.vhd \
+../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
+../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
+../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
+../../modules/wr_endpoint/ep_tx_framer.vhd \
+../../modules/wr_endpoint/ep_packet_filter.vhd \
+../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+../../modules/wr_endpoint/ep_ts_counter.vhd \
+../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+../../modules/wr_endpoint/ep_timestamping_unit.vhd \
+../../modules/wr_endpoint/ep_leds_controller.vhd \
+../../modules/wr_endpoint/ep_rtu_header_extract.vhd \
+../../modules/wr_endpoint/ep_rx_buffer.vhd \
+../../modules/wr_endpoint/ep_sync_detect.vhd \
+../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+../../modules/wr_endpoint/ep_wishbone_controller.vhd \
+../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
+../../modules/wr_endpoint/endpoint_pkg.vhd \
+../../modules/wr_endpoint/wr_endpoint.vhd \
+../../modules/wr_endpoint/xwr_endpoint.vhd \
+../../modules/wr_pps_gen/pps_gen_wb.vhd \
+../../modules/wr_pps_gen/wr_pps_gen.vhd \
+../../modules/wr_pps_gen/xwr_pps_gen.vhd \
+../../modules/wrc_core/wb_conmax/wbconmax_pkg.vhd \
+../../modules/wrc_core/wrc_dpram.vhd \
+../../modules/wrc_core/wrcore_pkg.vhd \
+../../modules/wrc_core/wrc_periph.vhd \
+../../modules/wrc_core/wb_reset.vhd \
+../../modules/wrc_core/wbp_mux.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_pri_dec.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_pri_enc.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_arb.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_msel.vhd \
+../../modules/wrc_core/wr_core.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_slave_if.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_master_if.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_rf.vhd \
+../../modules/wrc_core/wb_conmax/wb_conmax_top.vhd \
+../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd \
+../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
+../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
+../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../modules/fabric/xwb_fabric_sink.vhd \
+../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
+../../modules/mini_bone/xmini_bone.vhd \
+../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd \
+../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd \
+../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
+../../modules/wr_mini_nic/minic_wb_slave.vhd \
+
+VHDL_OBJ := work/wr_fabric_pkg/.wr_fabric_pkg_vhd \
+work/wishbone_pkg/.wishbone_pkg_vhd \
+work/gtp_bitslide/.gtp_bitslide_vhd \
+work/gtp_phase_align/.gtp_phase_align_vhd \
+work/gtp_phase_align_virtex6/.gtp_phase_align_virtex6_vhd \
+work/gtx_reset/.gtx_reset_vhd \
+work/whiterabbitgtx_wrapper_gtx/.whiterabbitgtx_wrapper_gtx_vhd \
+work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile_vhd \
+work/disparity_gen_pkg/.disparity_gen_pkg_vhd \
+work/gencores_pkg/.gencores_pkg_vhd \
+work/mini_bone/.mini_bone_vhd \
+work/genram_pkg/.genram_pkg_vhd \
+work/xwb_fabric_source/.xwb_fabric_source_vhd \
+work/dec_8b10b/.dec_8b10b_vhd \
+work/enc_8b10b/.enc_8b10b_vhd \
+work/wr_tbi_phy/.wr_tbi_phy_vhd \
+work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6_vhd \
+work/dmtd_phase_meas/.dmtd_phase_meas_vhd \
+work/dmtd_with_deglitcher/.dmtd_with_deglitcher_vhd \
+work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher_vhd \
+work/hpll_period_detect/.hpll_period_detect_vhd \
+work/minic_packet_buffer/.minic_packet_buffer_vhd \
+work/wbgen2_pkg/.wbgen2_pkg_vhd \
+work/minic_wbgen2_pkg/.minic_wbgen2_pkg_vhd \
+work/wr_mini_nic/.wr_mini_nic_vhd \
+work/xwr_mini_nic/.xwr_mini_nic_vhd \
+work/softpll_wb/.softpll_wb_vhd \
+work/wr_softpll/.wr_softpll_vhd \
+work/xwr_softpll/.xwr_softpll_vhd \
+work/ep_registers_pkg/.ep_registers_pkg_vhd \
+work/endpoint_private_pkg/.endpoint_private_pkg_vhd \
+work/ep_tx_pcs_8bit/.ep_tx_pcs_8bit_vhd \
+work/ep_tx_pcs_16bit/.ep_tx_pcs_16bit_vhd \
+work/ep_rx_pcs_16bit/.ep_rx_pcs_16bit_vhd \
+work/ep_autonegotiation/.ep_autonegotiation_vhd \
+work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb_vhd \
+work/ep_1000basex_pcs/.ep_1000basex_pcs_vhd \
+work/ep_rx_crc_size_check/.ep_rx_crc_size_check_vhd \
+work/ep_rx_bypass_queue/.ep_rx_bypass_queue_vhd \
+work/ep_rx_path/.ep_rx_path_vhd \
+work/ep_rx_wb_master/.ep_rx_wb_master_vhd \
+work/ep_rx_oob_insert/.ep_rx_oob_insert_vhd \
+work/ep_rx_early_address_match/.ep_rx_early_address_match_vhd \
+work/ep_clock_alignment_fifo/.ep_clock_alignment_fifo_vhd \
+work/ep_tx_framer/.ep_tx_framer_vhd \
+work/ep_packet_filter/.ep_packet_filter_vhd \
+work/ep_rx_vlan_unit/.ep_rx_vlan_unit_vhd \
+work/ep_ts_counter/.ep_ts_counter_vhd \
+work/ep_rx_status_reg_insert/.ep_rx_status_reg_insert_vhd \
+work/ep_timestamping_unit/.ep_timestamping_unit_vhd \
+work/ep_leds_controller/.ep_leds_controller_vhd \
+work/ep_rtu_header_extract/.ep_rtu_header_extract_vhd \
+work/ep_rx_buffer/.ep_rx_buffer_vhd \
+work/ep_sync_detect/.ep_sync_detect_vhd \
+work/ep_sync_detect_16bit/.ep_sync_detect_16bit_vhd \
+work/ep_wishbone_controller/.ep_wishbone_controller_vhd \
+work/ep_rx_pcs_8bit/.ep_rx_pcs_8bit_vhd \
+work/endpoint_pkg/.endpoint_pkg_vhd \
+work/wr_endpoint/.wr_endpoint_vhd \
+work/xwr_endpoint/.xwr_endpoint_vhd \
+work/pps_gen_wb/.pps_gen_wb_vhd \
+work/wr_pps_gen/.wr_pps_gen_vhd \
+work/xwr_pps_gen/.xwr_pps_gen_vhd \
+work/wbconmax_pkg/.wbconmax_pkg_vhd \
+work/wrc_dpram/.wrc_dpram_vhd \
+work/wrcore_pkg/.wrcore_pkg_vhd \
+work/wrc_periph/.wrc_periph_vhd \
+work/wb_reset/.wb_reset_vhd \
+work/wbp_mux/.wbp_mux_vhd \
+work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd \
+work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd \
+work/wb_conmax_arb/.wb_conmax_arb_vhd \
+work/wb_conmax_msel/.wb_conmax_msel_vhd \
+work/wr_core/.wr_core_vhd \
+work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd \
+work/wb_conmax_master_if/.wb_conmax_master_if_vhd \
+work/wb_conmax_rf/.wb_conmax_rf_vhd \
+work/wb_conmax_top/.wb_conmax_top_vhd \
+work/wr_gtx_phy_virtex6/.wr_gtx_phy_virtex6_vhd \
+work/gc_crc_gen/.gc_crc_gen_vhd \
+work/gc_moving_average/.gc_moving_average_vhd \
+work/gc_extend_pulse/.gc_extend_pulse_vhd \
+work/gc_delay_gen/.gc_delay_gen_vhd \
+work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd \
+work/gc_serial_dac/.gc_serial_dac_vhd \
+work/gc_sync_ffs/.gc_sync_ffs_vhd \
+work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
+work/gc_frequency_meter/.gc_frequency_meter_vhd \
+work/xwb_fabric_sink/.xwb_fabric_sink_vhd \
+work/memory_loader_pkg/.memory_loader_pkg_vhd \
+work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
+work/xmini_bone/.xmini_bone_vhd \
+work/generic_async_fifo/.generic_async_fifo_vhd \
+work/generic_dpram/.generic_dpram_vhd \
+work/generic_spram/.generic_spram_vhd \
+work/generic_sync_fifo/.generic_sync_fifo_vhd \
+work/wb_async_bridge/.wb_async_bridge_vhd \
+work/xwb_async_bridge/.xwb_async_bridge_vhd \
+work/wb_onewire_master/.wb_onewire_master_vhd \
+work/xwb_onewire_master/.xwb_onewire_master_vhd \
+work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd \
+work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd \
+work/i2c_master_top/.i2c_master_top_vhd \
+work/wb_i2c_master/.wb_i2c_master_vhd \
+work/xwb_i2c_master/.xwb_i2c_master_vhd \
+work/xwb_bus_fanout/.xwb_bus_fanout_vhd \
+work/xwb_dpram/.xwb_dpram_vhd \
+work/wb_gpio_port/.wb_gpio_port_vhd \
+work/xwb_gpio_port/.xwb_gpio_port_vhd \
+work/wb_tics/.wb_tics_vhd \
+work/xwb_tics/.xwb_tics_vhd \
+work/uart_async_rx/.uart_async_rx_vhd \
+work/uart_async_tx/.uart_async_tx_vhd \
+work/uart_baud_gen/.uart_baud_gen_vhd \
+work/simple_uart_pkg/.simple_uart_pkg_vhd \
+work/simple_uart_wb/.simple_uart_wb_vhd \
+work/wb_simple_uart/.wb_simple_uart_vhd \
+work/xwb_simple_uart/.xwb_simple_uart_vhd \
+work/vic_prio_enc/.vic_prio_enc_vhd \
+work/wb_slave_vic/.wb_slave_vic_vhd \
+work/wb_vic/.wb_vic_vhd \
+work/xwb_vic/.xwb_vic_vhd \
+work/wb_spi/.wb_spi_vhd \
+work/xwb_spi/.xwb_spi_vhd \
+work/xwb_crossbar/.xwb_crossbar_vhd \
+work/xwb_lm32/.xwb_lm32_vhd \
+work/wb_slave_adapter/.wb_slave_adapter_vhd \
+work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
+work/wbgen2_eic/.wbgen2_eic_vhd \
+work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
+work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
+work/minic_wb_slave/.minic_wb_slave_vhd \
+
+LIBS := work
+LIB_IND := work/.work
+## rules #################################
+sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ): $(VHDL_OBJ)
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+ cp $< .
+clean:
+ rm -rf ./modelsim.ini $(LIBS)
+.PHONY: clean
+
+work/.work:
+ (vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
+
+work/main/.main_sv: main.sv
+ vlog -work work $(VLOG_FLAGS) -sv +incdir+. +incdir+../../sim $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/sockit_owm/.sockit_owm_v: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/spi_clgen/.spi_clgen_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/spi_shift/.spi_shift_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/spi_top/.spi_top_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_allprofiles/.lm32_allprofiles_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/jtag_cores/.jtag_cores_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_adder/.lm32_adder_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_addsub/.lm32_addsub_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_dp_ram/.lm32_dp_ram_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_logic_op/.lm32_logic_op_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_ram/.lm32_ram_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_shifter/.lm32_shifter_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/lm32_multiplier/.lm32_multiplier_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/jtag_tap/.jtag_tap_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
+ vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+
+work/wr_fabric_pkg/.wr_fabric_pkg_vhd: ../../modules/fabric/wr_fabric_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wishbone_pkg/.wishbone_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gtp_bitslide/.gtp_bitslide_vhd: ../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gtp_phase_align/.gtp_phase_align_vhd: ../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gtp_phase_align_virtex6/.gtp_phase_align_virtex6_vhd: ../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gtx_reset/.gtx_reset_vhd: ../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/whiterabbitgtx_wrapper_gtx/.whiterabbitgtx_wrapper_gtx_vhd: ../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile_vhd: ../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/disparity_gen_pkg/.disparity_gen_pkg_vhd: ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/mini_bone/.mini_bone_vhd: ../../modules/mini_bone/mini_bone.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/mini_bone/.mini_bone: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_fabric_source/.xwb_fabric_source_vhd: ../../modules/fabric/xwb_fabric_source.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_fabric_source/.xwb_fabric_source: \
+work/genram_pkg/.genram_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/dec_8b10b/.dec_8b10b_vhd: ../../modules/wr_tbi_phy/dec_8b10b.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/enc_8b10b/.enc_8b10b_vhd: ../../modules/wr_tbi_phy/enc_8b10b.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_tbi_phy/.wr_tbi_phy_vhd: ../../modules/wr_tbi_phy/wr_tbi_phy.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_tbi_phy/.wr_tbi_phy: \
+work/gencores_pkg/.gencores_pkg
+
+work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6_vhd: ../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6: \
+work/gencores_pkg/.gencores_pkg \
+work/disparity_gen_pkg/.disparity_gen_pkg
+
+work/dmtd_phase_meas/.dmtd_phase_meas_vhd: ../../modules/timing/dmtd_phase_meas.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/dmtd_phase_meas/.dmtd_phase_meas: \
+work/gencores_pkg/.gencores_pkg
+
+work/dmtd_with_deglitcher/.dmtd_with_deglitcher_vhd: ../../modules/timing/dmtd_with_deglitcher.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/dmtd_with_deglitcher/.dmtd_with_deglitcher: \
+work/gencores_pkg/.gencores_pkg
+
+work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher_vhd: ../../modules/timing/multi_dmtd_with_deglitcher.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher: \
+work/gencores_pkg/.gencores_pkg
+
+work/hpll_period_detect/.hpll_period_detect_vhd: ../../modules/timing/hpll_period_detect.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/hpll_period_detect/.hpll_period_detect: \
+work/gencores_pkg/.gencores_pkg
+
+work/minic_packet_buffer/.minic_packet_buffer_vhd: ../../modules/wr_mini_nic/minic_packet_buffer.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/minic_packet_buffer/.minic_packet_buffer: \
+work/genram_pkg/.genram_pkg
+
+work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/minic_wbgen2_pkg/.minic_wbgen2_pkg_vhd: ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/minic_wbgen2_pkg/.minic_wbgen2_pkg: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wr_mini_nic/.wr_mini_nic_vhd: ../../modules/wr_mini_nic/wr_mini_nic.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_mini_nic/.wr_mini_nic: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/minic_wbgen2_pkg/.minic_wbgen2_pkg
+
+work/xwr_mini_nic/.xwr_mini_nic_vhd: ../../modules/wr_mini_nic/xwr_mini_nic.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwr_mini_nic/.xwr_mini_nic: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/softpll_wb/.softpll_wb_vhd: ../../modules/wr_softpll/softpll_wb.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/softpll_wb/.softpll_wb: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wr_softpll/.wr_softpll_vhd: ../../modules/wr_softpll/wr_softpll.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_softpll/.wr_softpll: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/xwr_softpll/.xwr_softpll_vhd: ../../modules/wr_softpll/xwr_softpll.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwr_softpll/.xwr_softpll: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/ep_registers_pkg/.ep_registers_pkg_vhd: ../../modules/wr_endpoint/ep_registers_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_registers_pkg/.ep_registers_pkg: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/endpoint_private_pkg/.endpoint_private_pkg_vhd: ../../modules/wr_endpoint/endpoint_private_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/endpoint_private_pkg/.endpoint_private_pkg: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/ep_tx_pcs_8bit/.ep_tx_pcs_8bit_vhd: ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_tx_pcs_8bit/.ep_tx_pcs_8bit: \
+work/genram_pkg/.genram_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_tx_pcs_16bit/.ep_tx_pcs_16bit_vhd: ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_tx_pcs_16bit/.ep_tx_pcs_16bit: \
+work/genram_pkg/.genram_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_pcs_16bit/.ep_rx_pcs_16bit_vhd: ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_pcs_16bit/.ep_rx_pcs_16bit: \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_autonegotiation/.ep_autonegotiation_vhd: ../../modules/wr_endpoint/ep_autonegotiation.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_autonegotiation/.ep_autonegotiation: \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb_vhd: ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_1000basex_pcs/.ep_1000basex_pcs_vhd: ../../modules/wr_endpoint/ep_1000basex_pcs.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_1000basex_pcs/.ep_1000basex_pcs: \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_crc_size_check/.ep_rx_crc_size_check_vhd: ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_crc_size_check/.ep_rx_crc_size_check: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_bypass_queue/.ep_rx_bypass_queue_vhd: ../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_path/.ep_rx_path_vhd: ../../modules/wr_endpoint/ep_rx_path.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_path/.ep_rx_path: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/genram_pkg/.genram_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/ep_rx_wb_master/.ep_rx_wb_master_vhd: ../../modules/wr_endpoint/ep_rx_wb_master.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_wb_master/.ep_rx_wb_master: \
+work/endpoint_private_pkg/.endpoint_private_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/ep_rx_oob_insert/.ep_rx_oob_insert_vhd: ../../modules/wr_endpoint/ep_rx_oob_insert.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_oob_insert/.ep_rx_oob_insert: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_early_address_match/.ep_rx_early_address_match_vhd: ../../modules/wr_endpoint/ep_rx_early_address_match.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_early_address_match/.ep_rx_early_address_match: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_clock_alignment_fifo/.ep_clock_alignment_fifo_vhd: ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_clock_alignment_fifo/.ep_clock_alignment_fifo: \
+work/genram_pkg/.genram_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_tx_framer/.ep_tx_framer_vhd: ../../modules/wr_endpoint/ep_tx_framer.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_tx_framer/.ep_tx_framer: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/genram_pkg/.genram_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_packet_filter/.ep_packet_filter_vhd: ../../modules/wr_endpoint/ep_packet_filter.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_packet_filter/.ep_packet_filter: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/genram_pkg/.genram_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_vlan_unit/.ep_rx_vlan_unit_vhd: ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_vlan_unit/.ep_rx_vlan_unit: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/ep_ts_counter/.ep_ts_counter_vhd: ../../modules/wr_endpoint/ep_ts_counter.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_ts_counter/.ep_ts_counter: \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_status_reg_insert/.ep_rx_status_reg_insert_vhd: ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_status_reg_insert/.ep_rx_status_reg_insert: \
+work/endpoint_private_pkg/.endpoint_private_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/ep_timestamping_unit/.ep_timestamping_unit_vhd: ../../modules/wr_endpoint/ep_timestamping_unit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_timestamping_unit/.ep_timestamping_unit: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_leds_controller/.ep_leds_controller_vhd: ../../modules/wr_endpoint/ep_leds_controller.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_leds_controller/.ep_leds_controller: \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rtu_header_extract/.ep_rtu_header_extract_vhd: ../../modules/wr_endpoint/ep_rtu_header_extract.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rtu_header_extract/.ep_rtu_header_extract: \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_rx_buffer/.ep_rx_buffer_vhd: ../../modules/wr_endpoint/ep_rx_buffer.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_buffer/.ep_rx_buffer: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/genram_pkg/.genram_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/ep_sync_detect/.ep_sync_detect_vhd: ../../modules/wr_endpoint/ep_sync_detect.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_sync_detect/.ep_sync_detect: \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_sync_detect_16bit/.ep_sync_detect_16bit_vhd: ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_sync_detect_16bit/.ep_sync_detect_16bit: \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/ep_wishbone_controller/.ep_wishbone_controller_vhd: ../../modules/wr_endpoint/ep_wishbone_controller.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_wishbone_controller/.ep_wishbone_controller: \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/ep_rx_pcs_8bit/.ep_rx_pcs_8bit_vhd: ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/ep_rx_pcs_8bit/.ep_rx_pcs_8bit: \
+work/genram_pkg/.genram_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/endpoint_pkg/.endpoint_pkg_vhd: ../../modules/wr_endpoint/endpoint_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/endpoint_pkg/.endpoint_pkg: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/wr_endpoint/.wr_endpoint_vhd: ../../modules/wr_endpoint/wr_endpoint.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_endpoint/.wr_endpoint: \
+work/wishbone_pkg/.wishbone_pkg \
+work/ep_registers_pkg/.ep_registers_pkg \
+work/gencores_pkg/.gencores_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/endpoint_private_pkg/.endpoint_private_pkg
+
+work/xwr_endpoint/.xwr_endpoint_vhd: ../../modules/wr_endpoint/xwr_endpoint.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwr_endpoint/.xwr_endpoint: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/endpoint_pkg/.endpoint_pkg
+
+work/pps_gen_wb/.pps_gen_wb_vhd: ../../modules/wr_pps_gen/pps_gen_wb.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_pps_gen/.wr_pps_gen_vhd: ../../modules/wr_pps_gen/wr_pps_gen.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_pps_gen/.wr_pps_gen: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/xwr_pps_gen/.xwr_pps_gen_vhd: ../../modules/wr_pps_gen/xwr_pps_gen.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwr_pps_gen/.xwr_pps_gen: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/wbconmax_pkg/.wbconmax_pkg_vhd: ../../modules/wrc_core/wb_conmax/wbconmax_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wrc_dpram/.wrc_dpram_vhd: ../../modules/wrc_core/wrc_dpram.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wrc_dpram/.wrc_dpram: \
+work/genram_pkg/.genram_pkg
+
+work/wrcore_pkg/.wrcore_pkg_vhd: ../../modules/wrc_core/wrcore_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wrcore_pkg/.wrcore_pkg: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wbconmax_pkg/.wbconmax_pkg \
+work/genram_pkg/.genram_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/wrc_periph/.wrc_periph_vhd: ../../modules/wrc_core/wrc_periph.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wrc_periph/.wrc_periph: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wrcore_pkg/.wrcore_pkg
+
+work/wb_reset/.wb_reset_vhd: ../../modules/wrc_core/wb_reset.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wbp_mux/.wbp_mux_vhd: ../../modules/wrc_core/wbp_mux.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wbp_mux/.wbp_mux: \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_pri_dec.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_pri_enc.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_arb/.wb_conmax_arb_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_arb.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_msel/.wb_conmax_msel_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_msel.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_core/.wr_core_vhd: ../../modules/wrc_core/wr_core.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_core/.wr_core: \
+work/wr_fabric_pkg/.wr_fabric_pkg \
+work/endpoint_pkg/.endpoint_pkg \
+work/wbconmax_pkg/.wbconmax_pkg \
+work/genram_pkg/.genram_pkg \
+work/wrcore_pkg/.wrcore_pkg \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_slave_if.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_slave_if/.wb_conmax_slave_if: \
+work/wbconmax_pkg/.wbconmax_pkg
+
+work/wb_conmax_master_if/.wb_conmax_master_if_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_master_if.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_master_if/.wb_conmax_master_if: \
+work/wbconmax_pkg/.wbconmax_pkg
+
+work/wb_conmax_rf/.wb_conmax_rf_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_rf.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_rf/.wb_conmax_rf: \
+work/wbconmax_pkg/.wbconmax_pkg
+
+work/wb_conmax_top/.wb_conmax_top_vhd: ../../modules/wrc_core/wb_conmax/wb_conmax_top.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_conmax_top/.wb_conmax_top: \
+work/wbconmax_pkg/.wbconmax_pkg
+
+work/wr_gtx_phy_virtex6/.wr_gtx_phy_virtex6_vhd: ../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wr_gtx_phy_virtex6/.wr_gtx_phy_virtex6: \
+work/gencores_pkg/.gencores_pkg \
+work/disparity_gen_pkg/.disparity_gen_pkg
+
+work/gc_crc_gen/.gc_crc_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_crc_gen/.gc_crc_gen: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_moving_average/.gc_moving_average_vhd: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_moving_average/.gc_moving_average: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_extend_pulse/.gc_extend_pulse: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_delay_gen/.gc_delay_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_delay_gen/.gc_delay_gen: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_dual_pi_controller/.gc_dual_pi_controller: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_serial_dac/.gc_serial_dac_vhd: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
+work/gencores_pkg/.gencores_pkg
+
+work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/gc_frequency_meter/.gc_frequency_meter: \
+work/gencores_pkg/.gencores_pkg
+
+work/xwb_fabric_sink/.xwb_fabric_sink_vhd: ../../modules/fabric/xwb_fabric_sink.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_fabric_sink/.xwb_fabric_sink: \
+work/genram_pkg/.genram_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/memory_loader_pkg/.memory_loader_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
+work/genram_pkg/.genram_pkg
+
+work/xmini_bone/.xmini_bone_vhd: ../../modules/mini_bone/xmini_bone.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xmini_bone/.xmini_bone: \
+work/wishbone_pkg/.wishbone_pkg \
+work/wr_fabric_pkg/.wr_fabric_pkg
+
+work/generic_async_fifo/.generic_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/generic_async_fifo/.generic_async_fifo: \
+work/genram_pkg/.genram_pkg
+
+work/generic_dpram/.generic_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/generic_dpram/.generic_dpram: \
+work/genram_pkg/.genram_pkg \
+work/memory_loader_pkg/.memory_loader_pkg
+
+work/generic_spram/.generic_spram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/generic_spram/.generic_spram: \
+work/genram_pkg/.genram_pkg
+
+work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/generic_sync_fifo/.generic_sync_fifo: \
+work/genram_pkg/.genram_pkg
+
+work/wb_async_bridge/.wb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_async_bridge/.wb_async_bridge: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/xwb_async_bridge/.xwb_async_bridge_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_async_bridge/.xwb_async_bridge: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_onewire_master/.wb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_onewire_master/.wb_onewire_master: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_onewire_master/.xwb_onewire_master: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/i2c_master_top/.i2c_master_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_i2c_master/.wb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_i2c_master/.wb_i2c_master: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_i2c_master/.xwb_i2c_master: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_bus_fanout/.xwb_bus_fanout: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_dpram/.xwb_dpram_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_dpram/.xwb_dpram: \
+work/wishbone_pkg/.wishbone_pkg \
+work/genram_pkg/.genram_pkg
+
+work/wb_gpio_port/.wb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_gpio_port/.wb_gpio_port: \
+work/wishbone_pkg/.wishbone_pkg \
+work/gencores_pkg/.gencores_pkg
+
+work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_gpio_port/.xwb_gpio_port: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_tics/.wb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_tics/.wb_tics: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_tics/.xwb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_tics/.xwb_tics: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/uart_async_rx/.uart_async_rx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/uart_async_tx/.uart_async_tx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/uart_baud_gen/.uart_baud_gen_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/simple_uart_pkg/.simple_uart_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/simple_uart_wb/.simple_uart_wb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/simple_uart_wb/.simple_uart_wb: \
+work/simple_uart_pkg/.simple_uart_pkg
+
+work/wb_simple_uart/.wb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_simple_uart/.wb_simple_uart: \
+work/wishbone_pkg/.wishbone_pkg \
+work/genram_pkg/.genram_pkg \
+work/simple_uart_pkg/.simple_uart_pkg
+
+work/xwb_simple_uart/.xwb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_simple_uart/.xwb_simple_uart: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_slave_vic/.wb_slave_vic: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_vic/.wb_vic: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_vic/.xwb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_vic/.xwb_vic: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_spi/.wb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_spi/.wb_spi: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_spi/.xwb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_spi/.xwb_spi: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_crossbar/.xwb_crossbar_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_crossbar/.xwb_crossbar: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/xwb_lm32/.xwb_lm32_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/xwb_lm32/.xwb_lm32: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wb_slave_adapter/.wb_slave_adapter: \
+work/wishbone_pkg/.wishbone_pkg
+
+work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wbgen2_dpssram/.wbgen2_dpssram: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wbgen2_eic/.wbgen2_eic_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wbgen2_eic/.wbgen2_eic: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wbgen2_fifo_async/.wbgen2_fifo_async: \
+work/genram_pkg/.genram_pkg \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
+work/wbgen2_pkg/.wbgen2_pkg
+
+work/minic_wb_slave/.minic_wb_slave_vhd: ../../modules/wr_mini_nic/minic_wb_slave.vhd
+ vcom $(VCOM_FLAGS) -work work $<
+ @mkdir -p $(dir $@) && touch $@
+
+
+work/minic_wb_slave/.minic_wb_slave: \
+work/minic_wbgen2_pkg/.minic_wbgen2_pkg \
+work/wbgen2_pkg/.wbgen2_pkg
+
diff --git a/hdl/eb_testbench/WB_bus_adapter_streaming_sg.vhd b/hdl/eb_testbench/WB_bus_adapter_streaming_sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..eec446f07a30401594613e66509c682891cfa08a
--- /dev/null
+++ b/hdl/eb_testbench/WB_bus_adapter_streaming_sg.vhd
@@ -0,0 +1,295 @@
+--! @file WB_bus_adapter_streaming_sg.vhd
+--! @brief WB adapters
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.vhdl_2008_workaround_pkg.all;
+
+entity WB_bus_adapter_streaming_sg is
+generic(g_adr_width_A : natural := 16; g_adr_width_B : natural := 32;
+ g_dat_width_A : natural := 16; g_dat_width_B : natural := 32;
+ g_pipeline : natural := 2
+ );
+ -- pipeline: 0 => A-x, 1 x-B, 2 A-B
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ A_CYC_i : in std_logic;
+ A_STB_i : in std_logic;
+ A_ADR_i : in std_logic_vector(g_adr_width_A-1 downto 0);
+ A_SEL_i : in std_logic_vector(g_dat_width_A/8-1 downto 0);
+ A_WE_i : in std_logic;
+ A_DAT_i : in std_logic_vector(g_dat_width_A-1 downto 0);
+ A_ACK_o : out std_logic;
+ A_ERR_o : out std_logic;
+ A_RTY_o : out std_logic;
+ A_STALL_o : out std_logic;
+ A_DAT_o : out std_logic_vector(g_dat_width_A-1 downto 0);
+
+
+ B_CYC_o : out std_logic;
+ B_STB_o : out std_logic;
+ B_ADR_o : out std_logic_vector(g_adr_width_B-1 downto 0);
+ B_SEL_o : out std_logic_vector(g_dat_width_B/8-1 downto 0);
+ B_WE_o : out std_logic;
+ B_DAT_o : out std_logic_vector(g_dat_width_B-1 downto 0);
+ B_ACK_i : in std_logic;
+ B_ERR_i : in std_logic;
+ B_RTY_i : in std_logic;
+ B_STALL_i : in std_logic;
+ B_DAT_i : in std_logic_vector(g_dat_width_B-1 downto 0)
+
+);
+end WB_bus_adapter_streaming_sg;
+
+
+
+
+architecture behavioral of WB_bus_adapter_streaming_sg is
+
+ constant c_adr_w_max : natural := maximum(g_adr_width_A, g_adr_width_B);
+ constant c_dat_w_max : natural := maximum(g_dat_width_A, g_dat_width_B);
+ constant c_sel_w_max : natural := maximum(g_dat_width_A, g_dat_width_B)/8;
+ constant c_adr_w_min : natural := minimum(g_adr_width_A, g_adr_width_B);
+ constant c_dat_w_min : natural := minimum(g_dat_width_A, g_dat_width_B);
+ constant c_sel_w_min : natural := minimum(g_dat_width_A, g_dat_width_B)/8;
+
+ signal sipo_d : std_logic_vector(c_dat_w_min-1 downto 0);
+ signal sipo_q : std_logic_vector(c_dat_w_max-1 downto 0);
+ signal piso_d : std_logic_vector(c_dat_w_max-1 downto 0);
+ signal piso_q : std_logic_vector(c_dat_w_min-1 downto 0);
+
+ -- direct adapter signals
+ constant c_adr_pad : std_logic_vector(c_adr_w_max-1 downto 0) := (others => '0');
+ constant c_sel_pad : std_logic_vector(c_sel_w_max-1 downto 0) := (others => '0');
+ constant c_dat_pad : std_logic_vector(c_dat_w_max-1 downto 0) := (others => '0');
+
+ signal adr : std_logic_vector(c_adr_w_max-1 downto 0);
+ signal slave_dat : std_logic_vector(c_dat_w_max-1 downto 0);
+ signal master_dat : std_logic_vector(c_dat_w_max-1 downto 0);
+ signal sel : std_logic_vector(c_sel_w_max-1 downto 0);
+ signal cyc : std_logic;
+
+ -- S/G adapter signals
+ signal sipo_sh_in : std_logic;
+ signal sipo_clr : std_logic;
+ signal sipo_full : std_logic;
+
+
+ signal piso_sh_out : std_logic;
+ signal piso_ld : std_logic;
+ signal piso_empty : std_logic;
+ signal piso_am_empty :std_logic;
+ signal piso_full : std_logic;
+ signal ld : std_logic;
+
+ signal get_adr : std_logic;
+ signal B_STB : std_logic;
+ signal ALLRDY_STROBED : std_logic;
+
+ component sipo_flag is
+ generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+ port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ clr_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+ full_o : out std_logic
+
+ );
+ end component;
+
+ component piso_flag is
+generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+ port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ ld_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+
+ full_o : out std_logic;
+ almost_empty_o : out std_logic;
+ empty_o : out std_logic
+
+);
+end component;
+
+begin
+
+assert not (g_dat_width_A = g_dat_width_B) report "WB streaming adapter superfluous, IO data widths are identical." severity error;
+
+---------------------------------------------------------------------------------------------------------------------------------
+PIPELINED: if(g_pipeline > 0) GENERATE
+
+A_LESSER_B: if(c_dat_w_min = g_dat_width_A) GENERATE
+
+ gather : sipo_flag -- MA ->-> => MB
+ generic map(g_width_IN => c_dat_w_min, g_width_OUT => c_dat_w_max)
+ port map(
+ clk_i => clk_i,
+ nRst_i => nRSt_i,
+
+ d_i => sipo_d,
+ en_i => sipo_sh_in,
+ clr_i => sipo_clr,
+
+ q_o => sipo_q,
+ full_o => sipo_full
+ );
+
+ --for(i
+
+ A_DAT_o <= (others => '0');
+ A_ERR_o <= B_ERR_i;
+ A_RTY_o <= B_RTY_i;
+
+ B_WE_o <= A_WE_i;
+
+ A_STALL_o <= '1' when sipo_full ='1' AND B_STALL_i = '1'
+ else '0';
+
+ sipo_sh_in <= '1' when (NOT(sipo_full = '1' AND B_STALL_i = '1') AND A_STB_i = '1')
+ else '0';
+
+ B_CYC_o <= '1' when (A_CYC_i = '1' OR sipo_full= '1')
+ else '0';
+
+
+
+
+ B_STB_o <= B_STB;
+ B_STB <= sipo_full AND NOT ALLRDY_STROBED;
+
+ sipo_d <= A_DAT_i;
+ B_DAT_o <= sipo_q;
+
+ process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+
+ A_ACK_o <= '0';
+ ALLRDY_STROBED <= '0';
+
+ else
+
+
+ if(sipo_full = '1') then
+ if(B_STALL_i = '0') then
+ ALLRDY_STROBED <= '1';
+ end if;
+ else
+ ALLRDY_STROBED <= '0';
+ end if;
+
+ ------- TODO
+ if(A_STB_i = '1' AND NOT (sipo_full ='1' AND B_STALL_i = '1')) then
+ A_ACK_o <= '1';
+ else
+ A_ACK_o <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+ END GENERATE;
+
+ --scatter
+A_GREATER_B: if(c_dat_w_max = g_dat_width_A) GENERATE
+
+
+ scatter : piso_flag -- SB => ->-> SA
+ generic map(g_width_IN => c_dat_w_max, g_width_OUT => c_dat_w_min)
+ port map(
+ clk_i => clk_i,
+ nRst_i => nRSt_i,
+
+ d_i => piso_d,
+ en_i => piso_sh_out,
+ ld_i => piso_ld,
+
+ q_o => piso_q,
+ full_o => piso_full,
+ almost_empty_o => piso_am_empty,
+ empty_o => piso_empty
+ );
+
+ A_DAT_o <= (others => '0');
+ piso_d <= A_DAT_i;
+ B_DAT_o <= piso_q;
+ A_ERR_o <= B_ERR_i;
+ A_RTY_o <= B_RTY_i;
+ B_WE_o <= A_WE_i;
+
+ piso_ld <= '1' when A_STB_i = '1' AND (piso_empty = '1' OR (piso_am_empty ='1' AND B_STALL_i = '0'))
+ else '0';
+
+ piso_sh_out <= '1' when B_STALL_i = '0' AND piso_empty = '0'
+ else '0';
+
+ B_CYC_o <= '1' when (A_CYC_i = '1' OR piso_empty = '0')
+ else '0';
+
+
+ B_STB_o <= '1' when (piso_empty = '0')
+ else '0';
+
+ A_STALL_o <= '1' when NOT (piso_empty = '1' OR (piso_am_empty ='1' AND B_STALL_i = '0'))
+ else '0';
+
+
+ process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+ A_ACK_o <= '0';
+ else
+ if(A_STB_i = '1' AND (piso_empty = '1' OR (piso_am_empty ='1' AND B_STALL_i = '0') )) then
+ A_ACK_o <= '1';
+ else
+ A_ACK_o <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+ end GENERATE; -- A_width < BA_width
+end GENERATE; --pipeline A-B
+end architecture;
diff --git a/hdl/eb_testbench/alt_FIFO_am_full_flag.vhd b/hdl/eb_testbench/alt_FIFO_am_full_flag.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..282ac0a25454188b260d1da5ce4c5f586d42b67c
--- /dev/null
+++ b/hdl/eb_testbench/alt_FIFO_am_full_flag.vhd
@@ -0,0 +1,244 @@
+--! @file alt_FIFO_am_full_flag.vhd
+--! @brief altera FIFO
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo
+
+-- ============================================================
+-- File Name: alt_FIFO_am_full_flag.vhd
+-- Megafunction Name(s):
+-- scfifo
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 153 11/29/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY alt_FIFO_am_full_flag IS
+ PORT
+ (
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ sclr : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ almost_empty : OUT STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+ );
+END alt_FIFO_am_full_flag;
+
+
+ARCHITECTURE SYN OF alt_fifo_am_full_flag IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC ;
+ SIGNAL sub_wire5 : STD_LOGIC ;
+
+
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ almost_empty_value : NATURAL;
+ almost_full_value : NATURAL;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ clock : IN STD_LOGIC ;
+ sclr : IN STD_LOGIC ;
+ usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ almost_empty : OUT STD_LOGIC ;
+ almost_full : OUT STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdreq : IN STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ usedw <= sub_wire0(3 DOWNTO 0);
+ empty <= sub_wire1;
+ full <= sub_wire2;
+ q <= sub_wire3(31 DOWNTO 0);
+ almost_empty <= sub_wire4;
+ almost_full <= sub_wire5;
+
+ scfifo_component : scfifo
+ GENERIC MAP (
+ add_ram_output_register => "OFF",
+ almost_empty_value => 1,
+ almost_full_value => 11,
+ intended_device_family => "Arria GX",
+ lpm_numwords => 16,
+ lpm_showahead => "ON",
+ lpm_type => "scfifo",
+ lpm_width => 32,
+ lpm_widthu => 4,
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => "ON"
+ )
+ PORT MAP (
+ clock => clock,
+ sclr => sclr,
+ wrreq => wrreq,
+ data => data,
+ rdreq => rdreq,
+ usedw => sub_wire0,
+ empty => sub_wire1,
+ full => sub_wire2,
+ q => sub_wire3,
+ almost_empty => sub_wire4,
+ almost_full => sub_wire5
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "11"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "16"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "32"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "32"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+-- Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "1"
+-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "11"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
+-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
+-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
+-- Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
+-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_FIFO_am_full_flag.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_FIFO_am_full_flag.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_FIFO_am_full_flag.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_FIFO_am_full_flag.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_FIFO_am_full_flag_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/hdl/eb_testbench/config_test.do b/hdl/eb_testbench/config_test.do
new file mode 100644
index 0000000000000000000000000000000000000000..045f3c5e80cb0fbcfa8bb40aedd32383f802d6af
--- /dev/null
+++ b/hdl/eb_testbench/config_test.do
@@ -0,0 +1,86 @@
+force -freeze sim:/eb_config/clk_i 1 0, 0 {5000000 fs} -r {10 ns}
+force -freeze sim:/eb_config/nRST_i 0 0
+force -freeze sim:/eb_config/status_i 1 0, 0 {22500000 fs} -r {45 ns}
+force -freeze sim:/eb_config/status_en 1 0, 0 {75000000 fs} -r {150 ns}
+force -freeze sim:/eb_config/status_clr 0 0
+run 20 ns
+force -freeze sim:/eb_config/nRST_i 1 0
+
+force -freeze sim:/eb_config/local_slave_i.CYC 0 0
+force -freeze sim:/eb_config/local_slave_i.STB 0 0
+force -freeze sim:/eb_config/local_slave_i.WE 0 0
+force -freeze sim:/eb_config/local_slave_i.SEL 0 0
+force -freeze sim:/eb_config/local_slave_i.DAT 0 0
+force -freeze sim:/eb_config/local_slave_i.ADR 0 0
+
+force -freeze sim:/eb_config/eb_slave_i.CYC 0 0
+force -freeze sim:/eb_config/eb_slave_i.STB 0 0
+force -freeze sim:/eb_config/eb_slave_i.WE 0 0
+force -freeze sim:/eb_config/eb_slave_i.SEL 0 0
+force -freeze sim:/eb_config/eb_slave_i.DAT 0 0
+force -freeze sim:/eb_config/eb_slave_i.ADR 0 0
+
+run 40 ns
+force -freeze sim:/eb_config/local_slave_i.CYC 1 0
+force -freeze sim:/eb_config/local_slave_i.STB 1 0
+force -freeze sim:/eb_config/local_slave_i.WE 1 0
+force -freeze sim:/eb_config/local_slave_i.SEL 0 0
+force -freeze sim:/eb_config/local_slave_i.DAT x"ABCDEF00" 0
+force -freeze sim:/eb_config/local_slave_i.ADR x"00000018" 0
+run 20 ns
+force -freeze sim:/eb_config/eb_slave_i.CYC 1 0
+force -freeze sim:/eb_config/eb_slave_i.STB 1 0
+force -freeze sim:/eb_config/eb_slave_i.WE 0 0
+force -freeze sim:/eb_config/eb_slave_i.SEL 0 0
+force -freeze sim:/eb_config/eb_slave_i.DAT 0 0
+force -freeze sim:/eb_config/eb_slave_i.ADR x"00000018" 0
+run 80 ns
+
+force -freeze sim:/eb_config/local_slave_i.CYC 1 0
+force -freeze sim:/eb_config/local_slave_i.STB 1 0
+force -freeze sim:/eb_config/local_slave_i.WE 1 0
+force -freeze sim:/eb_config/local_slave_i.SEL 0 0
+force -freeze sim:/eb_config/local_slave_i.DAT x"12345678" 0
+force -freeze sim:/eb_config/local_slave_i.ADR x"00000018" 0
+force -freeze sim:/eb_config/eb_slave_i.CYC 1 0
+force -freeze sim:/eb_config/eb_slave_i.STB 1 0
+force -freeze sim:/eb_config/eb_slave_i.WE 1 0
+force -freeze sim:/eb_config/eb_slave_i.SEL 0 0
+force -freeze sim:/eb_config/eb_slave_i.DAT x"FF00FFAA" 0
+force -freeze sim:/eb_config/eb_slave_i.ADR x"00000018" 0
+run 40 ns
+force -freeze sim:/eb_config/eb_slave_i.CYC 0 0
+force -freeze sim:/eb_config/eb_slave_i.STB 0 0
+force -freeze sim:/eb_config/eb_slave_i.WE 0 0
+force -freeze sim:/eb_config/eb_slave_i.SEL 0 0
+force -freeze sim:/eb_config/eb_slave_i.DAT x"FF00FFAA" 0
+force -freeze sim:/eb_config/eb_slave_i.ADR x"00000018" 0
+run 40 ns
+noforce sim:/eb_config/status_en
+force -freeze sim:/eb_config/status_en 0 0
+run 10 ns
+# read status reg locally ...
+force -freeze sim:/eb_config/local_slave_i.CYC 1 0
+force -freeze sim:/eb_config/local_slave_i.STB 1 0
+force -freeze sim:/eb_config/local_slave_i.WE 0 0
+force -freeze sim:/eb_config/local_slave_i.ADR x"00000000" 0
+run 10 ns
+force -freeze sim:/eb_config/local_slave_i.ADR x"00000004" 0
+run 10 ns
+force -freeze sim:/eb_config/local_slave_i.CYC 0 0
+force -freeze sim:/eb_config/local_slave_i.STB 0 0
+run 10 ns
+
+# and remotely ...
+force -freeze sim:/eb_config/eb_slave_i.CYC 1 0
+force -freeze sim:/eb_config/eb_slave_i.STB 1 0
+force -freeze sim:/eb_config/eb_slave_i.ADR x"00000000" 0
+run 10 ns
+force -freeze sim:/eb_config/eb_slave_i.ADR x"00000004" 0
+run 10 ns
+force -freeze sim:/eb_config/eb_slave_i.CYC 0 0
+force -freeze sim:/eb_config/eb_slave_i.STB 0 0
+
+
+
+
diff --git a/hdl/eb_testbench/eb_config.vhd b/hdl/eb_testbench/eb_config.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dc07c93330c8ab48b292b85a00f19a981046aee5
--- /dev/null
+++ b/hdl/eb_testbench/eb_config.vhd
@@ -0,0 +1,112 @@
+--! @file EB_config.vhd
+--! @brief EtherBone config space memory
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.wb32_package.all;
+
+entity eb_config is
+generic(g_cnt_width : natural := 32); -- MAX WIDTH 32
+ port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+ status_i : in std_logic;
+ status_en : in std_logic;
+ status_clr : in std_logic;
+
+ wb_master_i : in wb32_master_in;
+ wb_master_o : out wb32_master_out; --! local Wishbone master lines
+
+ wb_slave_o : out wb32_slave_out; --! EB Wishbone slave lines
+ wb_slave_i : in wb32_slave_in
+ );
+end eb_config;
+
+
+architecture behavioral of eb_config is
+
+subtype dword is std_logic_vector(31 downto 0);
+type mem is array (0 to 7) of dword ;
+signal my_mem : mem;
+
+signal wb_adr : natural;
+signal status_reg : std_logic_vector(31 downto 0);
+
+begin
+
+wb_adr <= to_integer(unsigned(wb_slave_i.ADR(8 downto 0)));
+
+wb32_if : process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+-- for i in 0 to 512 loop
+-- my_mem(i) <= x"11DEAD99";
+-- end loop;
+
+ status_reg <= (others => '1');
+
+ wb_slave_o <= (
+ ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ STALL => '0',
+ DAT => (others => '0'));
+
+ else
+ if(status_clr = '1') then
+ status_reg <= (others => '1');
+ elsif(status_en = '1') then
+ status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
+ end if;
+
+ wb_slave_o.ACK <= wb_slave_i.CYC AND wb_slave_i.STB;
+ wb_slave_o.DAT <= (others => '0');
+ if(wb_slave_i.STB = '1' AND wb_slave_i.CYC = '1') then
+
+ if(wb_slave_i.WE ='1') then
+ case wb_adr is
+ when 0 => null;
+ when others => my_mem(wb_adr) <= wb_slave_i.DAT;
+ end case;
+ else
+ case wb_adr is
+ when 0 => wb_slave_o.DAT <= status_reg;
+ when others => wb_slave_o.DAT <= my_mem(wb_adr);
+ end case;
+
+ end if;
+
+ end if;
+
+ end if;
+ end if;
+end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/eb_config.vhd.bak b/hdl/eb_testbench/eb_config.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..feee2377fea4b9d461b9398f3107fb76ecae98d5
--- /dev/null
+++ b/hdl/eb_testbench/eb_config.vhd.bak
@@ -0,0 +1,111 @@
+--! @file EB_config.vhd
+--! @brief EtherBone config space memory
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.wb32_package.all;
+
+entity eb_config is
+generic(g_cnt_width : natural := 32); -- MAX WIDTH 32
+ port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+ status_i : in std_logic;
+ status_en : in std_logic;
+ status_clr : in std_logic;
+
+ local_slave_o : in wb32_slave_out;
+ local_slave_i : out wb32_slave_in; --! local Wishbone master lines
+
+ eb_slave_o : out wb32_slave_out; --! EB Wishbone slave lines
+ eb_slave_i : in wb32_slave_in
+ );
+end eb_config;
+
+
+architecture behavioral of eb_config is
+
+subtype dword is std_logic_vector(31 downto 0);
+type mem is array (0 to 7) of dword ;
+signal my_mem : mem;
+
+signal wb_adr : natural;
+signal status_reg : std_logic_vector(31 downto 0);
+
+begin
+
+wb_adr <= to_integer(unsigned(eb_slave_i.ADR(8 downto 0)));
+
+wb32_if : process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+
+
+ status_reg <= (others => '1');
+
+ eb_slave_o <= (
+ ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ STALL => '0',
+ DAT => (others => '0'));
+
+ else
+ if(status_clr = '1') then
+ status_reg <= (others => '1');
+ elsif(status_en = '1') then
+ status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
+ end if;
+
+ eb_slave_o.ACK <= eb_slave_i.CYC AND eb_slave_i.STB;
+ eb_slave_o.DAT <= (others => '0');
+
+ if(eb_slave_i.STB = '1' AND eb_slave_i.CYC = '1') then
+
+ if(eb_slave_i.WE ='1') then
+ case wb_adr is
+ when 0 => null;
+ when others => my_mem(wb_adr) <= eb_slave_i.DAT;
+ end case;
+ else
+ case wb_adr is
+ when 0 => eb_slave_o.DAT <= status_reg;
+ when others => eb_slave_o.DAT <= my_mem(wb_adr);
+ end case;
+
+ end if;
+
+ end if;
+
+ end if;
+ end if;
+end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/eb_config_new.vhd b/hdl/eb_testbench/eb_config_new.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7abe322523df82814d28a7f8d49302bdac02dce1
--- /dev/null
+++ b/hdl/eb_testbench/eb_config_new.vhd
@@ -0,0 +1,194 @@
+--! @file EB_config.vhd
+--! @brief EtherBone config space memory
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.wb32_package.all;
+
+entity eb_config is
+ port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+ status_i : in std_logic;
+ status_en : in std_logic;
+ status_clr : in std_logic;
+
+ my_mac_address_o : out std_logic_vector(47 downto 0);
+ my_ip_address_o : out std_logic_vector(31 downto 0);
+
+ local_slave_o : out wb32_slave_out;
+ local_slave_i : in wb32_slave_in; --! local Wishbone master lines
+
+ eb_slave_o : out wb32_slave_out; --! EB Wishbone slave lines
+ eb_slave_i : in wb32_slave_in
+ );
+end eb_config;
+
+
+architecture behavioral of eb_config is
+
+subtype dword is std_logic_vector(31 downto 0);
+type mem is array (0 to 2) of dword ;
+signal my_mem : mem;
+
+
+
+signal eb_adr : natural;
+signal local_adr : natural;
+signal local_write_reg : std_logic_vector(31 downto 0);
+
+
+signal status_reg : std_logic_vector(63 downto 0);
+signal p_auto_cfg : std_logic_vector(63 downto 0);
+
+signal my_mac : std_logic_vector(47 downto 0);
+signal my_ip : std_logic_vector(31 downto 0);
+
+constant c_my_default_ip : std_logic_vector(31 downto 0) := x"C0A80064";
+constant c_my_default_mac : std_logic_vector(47 downto 0) := x"D15EA5EDBEEF";
+
+
+begin
+
+
+
+
+eb_adr <= to_integer(unsigned(eb_slave_i.ADR(7 downto 0)));
+local_adr <= to_integer(unsigned(local_slave_i.ADR(7 downto 0)));
+
+my_mac_address_o <= my_mac;
+my_ip_address_o <= my_ip;
+
+local_slave_o.STALL <= eb_slave_i.CYC;
+
+
+
+eb_if : process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+
+
+
+ eb_slave_o <= (
+ ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ STALL => '0',
+ DAT => (others => '0'));
+
+ local_slave_o.ACK <= '0';
+ local_slave_o.ERR <= '0';
+ local_slave_o.RTY <= '0';
+ local_slave_o.DAT <= (others => '0');
+
+ my_ip <= c_my_default_ip;
+ my_mac <= c_my_default_mac;
+ p_auto_cfg <= (others => '0');
+
+ else
+ eb_slave_o.ACK <= eb_slave_i.CYC AND eb_slave_i.STB;
+
+ if(eb_slave_i.STB = '1' AND eb_slave_i.CYC = '1') then
+
+ if(eb_slave_i.WE ='1') then
+ case eb_adr is
+ when 0 => null;
+ when 16 => my_mac(47 downto 16) <= eb_slave_i.DAT(31 downto 0);
+ when 20 => my_mac(15 downto 0) <= eb_slave_i.DAT(31 downto 16);
+ when 24 => my_ip <= eb_slave_i.DAT;
+ when others => null;
+ end case;
+ else
+ case eb_adr is
+ when 0 => eb_slave_o.DAT <= status_reg(63 downto 32);
+ when 4 => eb_slave_o.DAT <= status_reg(31 downto 0);
+ when 8 => eb_slave_o.DAT <= p_auto_cfg(63 downto 32);
+ when 12 => eb_slave_o.DAT <= p_auto_cfg(31 downto 0);
+ when 16 => eb_slave_o.DAT <= my_mac(47 downto 16);
+ when 20 => eb_slave_o.DAT <= (my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16)));
+ when 24 => eb_slave_o.DAT <= my_ip;
+
+ when others => eb_slave_o.DAT <= status_reg(63 downto 32);
+ end case;
+ end if;
+ end if;
+
+ if(local_slave_i.STB = '1' AND local_slave_i.CYC = '1' AND eb_slave_i.CYC = '0') then
+ local_slave_o.ACK <= '1';
+ if(local_slave_i.WE ='1') then
+ local_write_reg <= local_slave_i.DAT;
+
+ case local_adr is
+ when 8 => p_auto_cfg(63 downto 32) <= local_write_reg;
+ when 12 => p_auto_cfg(31 downto 0) <= local_write_reg;
+ when 16 => my_mac(47 downto 16) <= local_write_reg(31 downto 0);
+ when 20 => my_mac(15 downto 0) <= local_write_reg(31 downto 16);
+ when 24 => my_ip <= local_write_reg;
+ when others => null;
+ end case;
+ else
+ case local_adr is
+ when 0 => local_slave_o.DAT <= status_reg(63 downto 32);
+ when 4 => local_slave_o.DAT <= status_reg(31 downto 0);
+ when 8 => local_slave_o.DAT <= p_auto_cfg(63 downto 32);
+ when 12 => local_slave_o.DAT <= p_auto_cfg(31 downto 0);
+ when 16 => local_slave_o.DAT <= my_mac(47 downto 16);
+ when 20 => local_slave_o.DAT <= my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16));
+ when 24 => local_slave_o.DAT <= my_ip;
+
+ when others => local_slave_o.DAT <= status_reg(63 downto 32);
+ end case;
+ end if;
+ end if;
+ end if;
+
+ end if;
+
+end process;
+
+
+
+
+status_reg_sh : process(clk_i)
+begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+ status_reg <= (others => '1');
+ else
+ if(status_clr = '1') then
+ status_reg <= (others => '1');
+ elsif(status_en = '1') then
+ status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
+ end if;
+ end if;
+ end if;
+end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/eb_config_new.vhd.bak b/hdl/eb_testbench/eb_config_new.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..6c7689a6d5694c5827075867b3beb6bffb0b1f43
--- /dev/null
+++ b/hdl/eb_testbench/eb_config_new.vhd.bak
@@ -0,0 +1,194 @@
+--! @file EB_config.vhd
+--! @brief EtherBone config space memory
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+---------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.wb32_package.all;
+
+entity eb_config is
+ port(
+ clk_i : in std_logic; --clock
+ nRST_i : in std_logic;
+ status_i : in std_logic;
+ status_en : in std_logic;
+ status_clr : in std_logic;
+
+ my_mac_address_o : out std_logic_vector(47 downto 0);
+ my_ip_address_o : out std_logic_vector(31 downto 0);
+
+ local_slave_o : out wb32_slave_out;
+ local_slave_i : in wb32_slave_in; --! local Wishbone master lines
+
+ eb_slave_o : out wb32_slave_out; --! EB Wishbone slave lines
+ eb_slave_i : in wb32_slave_in
+ );
+end eb_config;
+
+
+architecture behavioral of eb_config is
+
+subtype dword is std_logic_vector(31 downto 0);
+type mem is array (0 to 2) of dword ;
+signal my_mem : mem;
+
+
+
+signal eb_adr : natural;
+signal local_adr : natural;
+signal local_write_reg : std_logic_vector(31 downto 0);
+
+
+signal status_reg : std_logic_vector(63 downto 0);
+signal p_auto_cfg : std_logic_vector(63 downto 0);
+
+signal my_mac : std_logic_vector(47 downto 0);
+signal my_ip : std_logic_vector(31 downto 0);
+
+constant c_my_default_ip : std_logic_vector(31 downto 0) := x"C0A80064";
+constant c_my_default_mac : std_logic_vector(47 downto 0) := x"D15EA5EDBEEF";
+
+
+begin
+
+
+
+
+eb_adr <= to_integer(unsigned(eb_slave_i.ADR(7 downto 0)));
+local_adr <= to_integer(unsigned(local_slave_i.ADR(7 downto 0)));
+
+my_mac_address_o <= my_mac;
+my_ip_address_o <= my_ip;
+
+local_slave_o.STALL <= eb_slave_i.CYC;
+
+
+
+eb_if : process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+
+
+
+ eb_slave_o <= (
+ ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ STALL => '0',
+ DAT => (others => '0'));
+ local_slave_o <= (
+ ACK => '0',
+ ERR => '0',
+ RTY => '0',
+ DAT => (others => '0'));
+
+ my_ip <= c_my_default_ip;
+ my_mac <= c_my_default_mac;
+ p_auto_cfg <= (others => '0');
+
+ else
+ eb_slave_o.ACK <= eb_slave_i.CYC AND eb_slave_i.STB;
+
+ if(eb_slave_i.STB = '1' AND eb_slave_i.CYC = '1') then
+
+ if(eb_slave_i.WE ='1') then
+ case eb_adr is
+ when 0 => null;
+ when 16 => my_mac(47 downto 16) <= eb_slave_i.DAT(31 downto 0);
+ when 20 => my_mac(15 downto 0) <= eb_slave_i.DAT(31 downto 16);
+ when 24 => my_ip <= eb_slave_i.DAT;
+ when others => null;
+ end case;
+ else
+ case eb_adr is
+ when 0 => eb_slave_o.DAT <= status_reg(63 downto 32);
+ when 4 => eb_slave_o.DAT <= status_reg(31 downto 0);
+ when 8 => eb_slave_o.DAT <= p_auto_cfg(63 downto 32);
+ when 12 => eb_slave_o.DAT <= p_auto_cfg(31 downto 0);
+ when 16 => eb_slave_o.DAT <= my_mac(47 downto 16);
+ when 20 => eb_slave_o.DAT <= (my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16)));
+ when 24 => eb_slave_o.DAT <= my_ip;
+
+ when others => eb_slave_o.DAT <= status_reg(63 downto 32);
+ end case;
+ end if;
+ end if;
+
+ if(local_slave_i.STB = '1' AND local_slave_i.CYC = '1' AND eb_slave_i.CYC = '0') then
+ local_slave_o.ACK <= '1';
+ if(local_slave_i.WE ='1') then
+ local_write_reg <= local_slave_i.DAT;
+
+ case local_adr is
+ when 8 => p_auto_cfg(63 downto 32) <= local_write_reg;
+ when 12 => p_auto_cfg(31 downto 0) <= local_write_reg;
+ when 16 => my_mac(47 downto 16) <= local_write_reg(31 downto 0);
+ when 20 => my_mac(15 downto 0) <= local_write_reg(31 downto 16);
+ when 24 => my_ip <= local_write_reg;
+ when others => null;
+ end case;
+ else
+ case local_adr is
+ when 0 => local_slave_o.DAT <= status_reg(63 downto 32);
+ when 4 => local_slave_o.DAT <= status_reg(31 downto 0);
+ when 8 => local_slave_o.DAT <= p_auto_cfg(63 downto 32);
+ when 12 => local_slave_o.DAT <= p_auto_cfg(31 downto 0);
+ when 16 => local_slave_o.DAT <= my_mac(47 downto 16);
+ when 20 => local_slave_o.DAT <= my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16));
+ when 24 => local_slave_o.DAT <= my_ip;
+
+ when others => local_slave_o.DAT <= status_reg(63 downto 32);
+ end case;
+ end if;
+ end if;
+ end if;
+
+ end if;
+
+end process;
+
+
+
+
+status_reg_sh : process(clk_i)
+begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+ status_reg <= (others => '1');
+ else
+ if(status_clr = '1') then
+ status_reg <= (others => '1');
+ elsif(status_en = '1') then
+ status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
+ end if;
+ end if;
+ end if;
+end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/eb_tb.cr.mti b/hdl/eb_testbench/eb_tb.cr.mti
new file mode 100644
index 0000000000000000000000000000000000000000..3e814346f56ae054704669c87f42faba5ec27dca
--- /dev/null
+++ b/hdl/eb_testbench/eb_tb.cr.mti
@@ -0,0 +1,251 @@
+/home/mkreider/hdlprojects/eb_testbench/wishbone_package16.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wishbone_package16.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling package wb16_package
+-- Compiling package body wb16_package
+-- Loading package wb16_package
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wb_master.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wb_master.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+-- Compiling interface IWishboneMaster
+-- Compiling package if_wb_master_svh_unit
+-- Compiling interface IWishboneMaster
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wb_packet_sink.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/wb_packet_sink.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/alt_FIFO_am_full_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/alt_FIFO_am_full_flag.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling entity alt_FIFO_am_full_flag
+-- Compiling architecture SYN of alt_fifo_am_full_flag
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/WB_bus_adapter_streaming_sg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/WB_bus_adapter_streaming_sg.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package vhdl_2008_workaround_pkg
+-- Compiling entity WB_bus_adapter_streaming_sg
+-- Compiling architecture behavioral of WB_bus_adapter_streaming_sg
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/eb_config_new.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/eb_config_new.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package wb32_package
+-- Compiling entity eb_config
+-- Compiling architecture behavioral of eb_config
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_TX_CTRL.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_TX_CTRL.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package EB_HDR_PKG
+-- Loading package wb32_package
+-- Loading package wb16_package
+-- Compiling entity EB_TX_CTRL
+-- Compiling architecture behavioral of EB_TX_CTRL
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_2_wb_converter.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_2_wb_converter.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package EB_HDR_PKG
+-- Loading package wb32_package
+-- Compiling entity eb_2_wb_converter
+-- Compiling architecture behavioral of eb_2_wb_converter
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_CORE.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_CORE.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package EB_HDR_PKG
+-- Loading package wb32_package
+-- Loading package wb16_package
+-- Compiling entity EB_CORE
+-- Compiling architecture behavioral of EB_CORE
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wb_fabric_defs.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/wb_fabric_defs.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/eth_packet.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/eth_packet.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling package wishbone_pkg
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling package wr_fabric_pkg
+-- Compiling package body wr_fabric_pkg
+-- Loading package wr_fabric_pkg
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_checksum.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_checksum.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package EB_HDR_PKG
+-- Compiling entity EB_checksum
+-- Compiling architecture behavioral of EB_checksum
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+-- Compiling interface IWishboneLink
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wb_binary_file_source.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/wb_binary_file_source.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling package vhdl_2008_workaround_pkg
+-- Compiling package body vhdl_2008_workaround_pkg
+-- Loading package vhdl_2008_workaround_pkg
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/main.sv {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/main.sv
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+-- Compiling interface IWishboneMaster
+-- Compiling interface IWishboneSlave
+-- Compiling package main_sv_unit
+-- Compiling interface IWishboneMaster
+-- Compiling interface IWishboneSlave
+-- Compiling module main
+
+Top level modules:
+ main
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/piso_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/piso_flag.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity piso_flag
+-- Compiling architecture behavioral of piso_flag
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package vhdl_2008_workaround_pkg
+-- Compiling entity sipo_flag
+-- Compiling architecture behavioral of sipo_flag
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling package EB_HDR_PKG
+-- Compiling package body EB_HDR_PKG
+-- Loading package EB_HDR_PKG
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wishbone_accessor.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wishbone_accessor.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wishbone_package32.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wishbone_package32.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling package wb32_package
+-- Compiling package body wb32_package
+-- Loading package wb32_package
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+-- Compiling interface IWishboneSlave
+-- Compiling package if_wb_slave_svh_unit
+-- Compiling interface IWishboneSlave
+
+Top level modules:
+ --none--
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package wishbone_pkg
+-- Loading package wr_fabric_pkg
+-- Compiling entity mini_bone
+-- Compiling architecture wrapper of mini_bone
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package wishbone_pkg
+-- Loading package wr_fabric_pkg
+-- Compiling entity xmini_bone
+-- Compiling architecture behavioral of xmini_bone
+
+} {} {}}
diff --git a/hdl/eb_testbench/eb_tb.mpf b/hdl/eb_testbench/eb_tb.mpf
new file mode 100644
index 0000000000000000000000000000000000000000..56da0d595d65ef3322e2de2c1514607342faa771
--- /dev/null
+++ b/hdl/eb_testbench/eb_tb.mpf
@@ -0,0 +1,1776 @@
+; Copyright 1991-2011 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+vital2000 = $MODEL_TECH/../vital2000
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+verilog = $MODEL_TECH/../verilog
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.2
+mtiUvm = $MODEL_TECH/../uvm-1.1
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+
+altera = $MODEL_TECH/../altera
+altera_mf = $MODEL_TECH/../altera_mf
+;work = $MODEL_TECH/../work
+cyclone = $MODEL_TECH/../cyclone
+cycloneii = $MODEL_TECH/../cycloneii
+lpm = $MODEL_TECH/../lpm
+max = $MODEL_TECH/../max
+maxii = $MODEL_TECH/../maxii
+sgate = $MODEL_TECH/../sgate
+stratix = $MODEL_TECH/../stratix
+stratixgx = $MODEL_TECH/../stratixgx
+stratixgx_gxb = $MODEL_TECH/../stratixgx_gxb
+stratixii = $MODEL_TECH/../stratixii
+secureip = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/secureip
+unisim = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/unisim
+unimacro = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/unimacro
+unisims_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/unisims_ver
+unimacro_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/unimacro_ver
+simprim = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/simprim
+simprims_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/simprims_ver
+xilinxcorelib = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/xilinxcorelib
+xilinxcorelib_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/xilinxcorelib_ver
+uni9000_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/uni9000_ver
+cpld = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/cpld
+cpld_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/cpld_ver
+
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is off.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, effects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance
+; SeparateConfigLibrary = 1;
+
+; Change how subprogram out parameter of type array and record are treated.
+; If 1, always initial the out parameter to its default value.
+; If 2, do not initialize the out parameter.
+; The value 0 indicates use the default for the langauge version being compiled.
+; Prior to 10.1 all langauge version did not initialize out composite parameters.
+; 10.1 and later files compile with -2008 initialize by default
+; InitOutCompositeParam = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = hexadecimal
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 20000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 20000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations. The default value is 1000. A
+; value of 0 indicates no limit.
+; SolveACTMaxOps = 1000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints. This
+; 'speculation' set is solved independently of the remaining constraints.
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set). If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+; 0 - no speculation
+; 1 - enable speculation that maintains LRM specified distribution
+; 2 - enable other speculation - may yield non-LRM distribution
+; Currently, distribution constraints and solve-before constraints are
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100.
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+; n = disable bit interleaving for all constraints (BDD engine)
+; r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+NumericStdNoWarnings = 1
+StdArithNoWarnings = 1
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 29
+Project_File_0 = /home/mkreider/hdlprojects/eb_testbench/wishbone_package16.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191040 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_1 = /home/mkreider/hdlprojects/eb_testbench/if_wb_master.svh
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = /home/mkreider/hdlprojects/eb_testbench/wb_packet_sink.svh
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = /home/mkreider/hdlprojects/eb_testbench/alt_FIFO_am_full_flag.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191766 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_4 = /home/mkreider/hdlprojects/eb_testbench/WB_bus_adapter_streaming_sg.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191114 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = /home/mkreider/hdlprojects/eb_testbench/EB_RX_CTRL.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328544471 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_6 = /home/mkreider/hdlprojects/eb_testbench/eb_config_new.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328541532 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_7 = /home/mkreider/hdlprojects/eb_testbench/EB_TX_CTRL.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328544433 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_8 = /home/mkreider/hdlprojects/eb_testbench/EB_2_wb_converter.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328542691 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_9 = /home/mkreider/hdlprojects/eb_testbench/EB_CORE.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328537542 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_10 = /home/mkreider/hdlprojects/eb_testbench/wb_fabric_defs.svh
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = /home/mkreider/hdlprojects/eb_testbench/eth_packet.svh
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328182231 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_14 = /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1327407856 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_15 = /home/mkreider/hdlprojects/eb_testbench/EB_checksum.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_16 = /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = /home/mkreider/hdlprojects/eb_testbench/wb_binary_file_source.svh
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1328266887 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_18 = /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191147 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_19 = /home/mkreider/hdlprojects/eb_testbench/main.sv
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1328522458 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_20 = /home/mkreider/hdlprojects/eb_testbench/piso_flag.vhd
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191255 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_21 = /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd
+Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191228 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_22 = /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328542499 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_24 = /home/mkreider/hdlprojects/eb_testbench/if_wishbone_accessor.svh
+Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_25 = /home/mkreider/hdlprojects/eb_testbench/wishbone_package32.vhd
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191023 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_26 = /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd
+Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1327407856 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_27 = /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd
+Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328197717 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_28 = /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh
+Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1328197801 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 1
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick =
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+Project_Major_Version = 10
+Project_Minor_Version = 0
diff --git a/hdl/eb_testbench/eth_packet.svh b/hdl/eb_testbench/eth_packet.svh
new file mode 100644
index 0000000000000000000000000000000000000000..565a76d8b92a3f86a401130780e41ca2da9f77c4
--- /dev/null
+++ b/hdl/eb_testbench/eth_packet.svh
@@ -0,0 +1,390 @@
+`ifndef __ETH_PACKET_SVH
+`define __ETH_PACKET_SVH
+
+`include "simdrv_defs.svh"
+
+typedef byte mac_addr_t[6];
+typedef bit[11:0] vid_t;
+typedef bit[2:0] pcp_t;
+
+typedef enum
+ {
+ NONE = 0,
+ TX_FID,
+ RX_TIMESTAMP
+ } oob_type_t;
+
+typedef struct {
+ bit [27:0] ts_r;
+ bit [3:0] ts_f;
+ bit [5:0] port_id;
+ bit [15:0] frame_id;
+} wr_timestamp_t;
+
+class EthPacket;
+
+ static const mac_addr_t dummy_mac = '{0,0,0,0,0,0} ;
+
+ static int _zero = 0;
+
+ static const int CMP_OOB = 1;
+ static const int CMP_STATUS = 2;
+
+ byte payload[];
+ int size;
+
+ mac_addr_t src, dst;
+ oob_type_t oob_type;
+
+ bit is_q;
+ bit is_hp;
+ bit has_smac;
+ bit has_crc;
+ bit error;
+
+ bit [15:0] ethertype;
+ bit [7:0] pclass;
+
+ vid_t vid;
+ pcp_t pcp;
+
+ oob_type_t oob;
+ wr_timestamp_t ts;
+
+
+ task set_size(int size);
+ payload = new[size](payload);
+ endtask
+
+ function new(int size = _zero);
+ size = 0;
+ src = dummy_mac;
+ dst = dummy_mac;
+ is_q = 0;
+ is_hp = 0;
+ has_crc = 0;
+ oob_type = NONE;
+ payload = new[size](payload);
+
+ endfunction // new
+
+ task deserialize(byte data[]);
+ int i, hsize, psize;
+
+ if(data.size < 14)
+ begin
+ error = 1;
+ return;
+ end
+
+ for(i=0; i<6;i++)
+ begin
+ dst[i] = data[i];
+ src[i] = data [i+6];
+ end
+
+ has_crc = 0;
+ if(data[12] == 'h81 && data[13] == 'h00)
+ begin
+ is_q = 1;
+ hsize = 18;
+ ethertype = {data[14], data[15]};
+ vid = ((int'(data[16]) << 8) | data[17]) & 12'hfff;
+ pcp = data[16] >> 5;
+ end else begin
+ is_q = 0;
+ hsize = 14;
+ ethertype = {data[12], data[13]};
+ end
+
+ psize = data.size() - hsize;
+
+ if(psize <= 0)
+ begin
+ error = 1;
+ return;
+ end
+
+ payload = new[psize];
+
+ for(i=0;i<data.size() - hsize;i++)
+ payload[i] = data[hsize + i];
+
+// error = 0;
+ endtask
+
+ task automatic serialize(ref byte data[]);
+ int i, hsize;
+
+ hsize = is_q ? 18 : 14;
+ data = new[payload.size() + hsize](data);
+
+ for(i=0; i<6;i++)
+ begin
+ data[i] = dst[i];
+ data[i + 6] = src[i];
+ end
+
+
+ if(is_q)
+ begin
+ data [12] = 8'h81;
+ data [13] = 8'h00;
+ data [14] = ethertype[15:8];
+ data [15] = ethertype[7:0];
+ data [16] = {pcp, 1'b0, vid[11:8]};
+ data [17] = vid[7:0];
+ end else begin
+ data[12] = ethertype [15:8];
+ data[13] = ethertype [7:0];
+ end
+
+ for (i=0; i<payload.size(); i++)
+ data[i + hsize] = payload[i];
+ endtask // serialize
+
+ function bit equal(ref EthPacket b, input int flags = 0);
+
+ if(src != b.src || dst != b.dst || ethertype != b.ethertype)
+ begin
+ $display("notequal: hdr");
+ return 0;
+ end
+
+ if(is_q ^ b.is_q)
+ begin
+ $display("notequal: q");
+ return 0;
+ end
+
+ if(is_q && (vid != b.vid || pcp != b.pcp))
+ return 0;
+
+ if(payload != b.payload)
+ begin
+ $display("notequal: payload");
+ return 0;
+ end
+// return 0;
+
+
+ if(flags & CMP_STATUS)
+ if(error ^ b.error)
+ return 0;
+
+ if(flags & CMP_OOB) begin
+ if (b.oob_type != oob_type)
+ return 0;
+
+ if(oob_type == TX_FID && (b.ts.frame_id != ts.frame_id))
+ return 0;
+ end
+
+ return 1;
+ endfunction // equal
+
+
+ task copy(ref EthPacket b);
+
+ endtask // copy
+
+ task hexdump(byte buffer []);
+ string str;
+ int size ;
+ int i;
+ int offset = 0;
+ const int per_row = 16;
+
+ size = buffer.size();
+
+
+ while(size > 0)
+ begin
+ int n;
+ n = (size > per_row ? per_row : size);
+ $sformat(str,"+%03x: ", offset);
+ for(i=0;i<n;i++) $sformat(str,"%s%s%02x", str, (i==(per_row/2)?"-":" "), buffer[offset + i]);
+ $display(str);
+
+ offset = offset + n;
+ size = size - n;
+ end
+
+
+ endtask // hexdump
+
+
+ task dump(int full = _zero);
+ string str, tmp;
+ int t;
+
+ if(is_q)
+ $sformat(str, "802.1q [VID %5d/PCP %d] ", vid, pcp);
+ else
+ str = "802.1 ";
+
+ $sformat(str, "%s DST [%02x:%02x:%02x:%02x:%02x:%02x] SRC: [%02x:%02x:%02x:%02x:%02x:%02x] Type = 0x%04x size = %d F:(%s%s)", str, dst[0],dst[1],dst[2],dst[3],dst[4],dst[5], src[0],src[1],src[2],src[3],src[4], src[5], ethertype, (is_q ? 18 : 14) + payload.size(),
+is_hp ? "H" : " ", has_crc ? "C" : " ");
+
+ if(oob_type == TX_FID)
+ begin
+ $sformat(tmp, "TxOOB: %x", ts.frame_id);
+ str = {str, tmp};
+ end
+
+ $display(str);
+ hexdump(payload);
+ endtask // dump
+
+
+endclass // EthPacket
+
+
+class EthPacketGenerator;
+
+ protected EthPacket template;
+ protected int min_size, max_size;
+ protected int seed;
+
+ static const int SMAC = (1<<0);
+ static const int DMAC = (1<<1);
+ static const int ETHERTYPE = (1<<2);
+ static const int VID = (1<<3);
+ static const int PCP = (1<<4);
+ static const int PAYLOAD = (1<<5);
+ static const int SEQ_PAYLOAD = (1<<7);
+ static const int SEQ_ID = (1<<10);
+ static const int TX_OOB = (1<<6);
+ static const int EVEN_LENGTH = (1<<8);
+ static const int RX_OOB = (1<<9);
+ static const int ALL = SMAC | DMAC | VID | ETHERTYPE | PCP | PAYLOAD ;
+
+
+ protected int r_flags;
+ protected int m_current_frame_id;
+ protected int cur_seq_id;
+
+ function new();
+ r_flags =ALL;
+ min_size = 64;
+ max_size = 128;
+ m_current_frame_id = 0;
+ template = new;
+ cur_seq_id = 0;
+
+ endfunction // new
+
+ task set_randomization(int flags);
+ r_flags = flags;
+ endtask // randomize
+
+
+ typedef byte dyn_array[];
+
+
+ protected function dyn_array random_bvec(int size);
+ byte v[];
+ int i;
+// $display("RandomBVEC %d", size);
+
+ v = new[size](v);
+ for(i=0;i<size;i++)
+ v[i] = $dist_uniform(seed, 0, 256);
+
+ return v;
+
+ endfunction // random_bvec
+
+ task set_seed(int seed_);
+ seed = seed_;
+ endtask // set_seed
+
+ function int get_seed();
+ return seed;
+ endfunction // get_seed
+
+
+
+
+ protected function dyn_array seq_payload(int size);
+ byte v[];
+ int i;
+
+ v = new[size](v);
+ for(i=0;i<size;i++)
+ v[i] = i;
+
+ return v;
+
+ endfunction // random_bvec
+
+
+ function automatic EthPacket gen();
+ EthPacket pkt;
+ int len;
+
+
+ pkt = new;
+
+
+ if (r_flags & SMAC) pkt.src = random_bvec(6); else pkt.src = template.src;
+ if (r_flags & DMAC) pkt.dst = random_bvec(6); else pkt.dst = template.dst;
+
+ pkt.ethertype = (r_flags & ETHERTYPE ? $dist_uniform(seed, 0, 1<<16) : template.ethertype);
+ pkt.is_q = template.is_q;
+ pkt.vid = template.vid;
+ pkt.pcp = template.pcp;
+ pkt.has_smac = template.has_smac;
+
+
+// $display("Size min %d max %d", min_size, max_size);
+
+ len = $dist_uniform(seed, min_size, max_size);
+
+ if((len & 1) && (r_flags & EVEN_LENGTH))
+ len++;
+
+
+ if(r_flags & PAYLOAD) pkt.payload = random_bvec(len);
+ else if(r_flags & SEQ_PAYLOAD) pkt.payload = seq_payload(len);
+ else pkt.payload = template.payload;
+
+ if(r_flags & SEQ_ID)
+ begin
+ pkt.payload[0] = cur_seq_id & 'hff;
+ pkt.payload[1] = (cur_seq_id>>8) & 'hff;
+ pkt.payload[2] = (cur_seq_id>>16) & 'hff;
+ pkt.payload[3] = (cur_seq_id>>24) & 'hff;
+ cur_seq_id++;
+ end
+
+ if(r_flags & TX_OOB)
+ begin
+ pkt.ts.frame_id = m_current_frame_id++;
+ pkt.oob_type = TX_FID;
+ end
+
+ return pkt;
+
+
+ endfunction
+
+ task set_template(EthPacket pkt);
+ template = pkt;
+ endtask // set_template
+
+ task set_size(int smin, int smax);
+ min_size = smin;
+ max_size = smax;
+ endtask // set_size
+
+
+
+endclass // EthPacketGenerator
+
+
+
+
+
+`endif
+
\ No newline at end of file
diff --git a/hdl/eb_testbench/if_wb_link.svh b/hdl/eb_testbench/if_wb_link.svh
new file mode 100644
index 0000000000000000000000000000000000000000..7ae928bf3cfbf8d3028ce45770784d9f9d86f4a5
--- /dev/null
+++ b/hdl/eb_testbench/if_wb_link.svh
@@ -0,0 +1,50 @@
+
+interface IWishboneLink;
+
+ parameter g_data_width = 32;
+ parameter g_addr_width = 32;
+
+
+ wire [g_addr_width - 1 : 0] adr;
+ wire [g_data_width - 1 : 0] dat_o;
+ wire [g_data_width - 1 : 0] dat_i;
+ wire [(g_data_width/8)-1 : 0] sel;
+ wire ack;
+ wire stall;
+ wire err;
+ wire rty;
+ wire cyc;
+ wire stb;
+ wire we;
+
+ modport slave
+ (
+ output adr,
+ output dat_o,
+ input dat_i,
+ output sel,
+ output cyc,
+ output stb,
+ output we,
+ input ack,
+ input stall,
+ input err,
+ input rty
+ );
+
+ modport master
+ (
+ input adr,
+ input dat_o,
+ output dat_i,
+ input sel,
+ input cyc,
+ input stb,
+ input we,
+ output ack,
+ output stall,
+ output err,
+ output rty
+ );
+
+endinterface // IWishboneLink
diff --git a/hdl/eb_testbench/if_wb_master.svh b/hdl/eb_testbench/if_wb_master.svh
new file mode 100644
index 0000000000000000000000000000000000000000..66dcc8c96b4afc5df7045b58bdea5db47854c86a
--- /dev/null
+++ b/hdl/eb_testbench/if_wb_master.svh
@@ -0,0 +1,438 @@
+//
+// Title : Software Wishbone master unit for testbenches
+//
+// File : if_wishbone.sv
+// Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+// Created : Tue Mar 23 12:19:36 2010
+// Standard : SystemVerilog
+//
+
+
+/* Todo:
+ pipelined reads
+ settings wrapped in the accessor object
+*/
+
+`include "simdrv_defs.svh"
+`include "if_wishbone_types.svh"
+`include "if_wishbone_accessor.svh"
+
+interface IWishboneMaster
+ (
+ input clk_i,
+ input rst_n_i
+ );
+
+ parameter g_addr_width = 32;
+ parameter g_data_width = 32;
+
+ logic [g_addr_width - 1 : 0] adr;
+ logic [g_data_width - 1 : 0] dat_o;
+ logic [(g_data_width/8)-1 : 0] sel;
+ wire [g_data_width - 1 : 0] dat_i;
+ wire ack;
+ wire stall;
+ wire err;
+ wire rty;
+ logic cyc;
+ logic stb;
+ logic we;
+
+ wire clk;
+ wire rst_n;
+
+ time last_access_t = 0;
+
+ struct {
+ int gen_random_throttling;
+ real throttle_prob;
+ int little_endian;
+ int cyc_on_stall;
+ wb_address_granularity_t addr_gran;
+ } settings;
+
+ modport master
+ (
+ output adr,
+ output dat_o,
+ output sel,
+ output cyc,
+ output stb,
+ output we,
+ input ack,
+ input dat_i,
+ input stall,
+ input err,
+ input rty
+ );
+
+ function automatic logic[g_addr_width-1:0] gen_addr(uint64_t addr, int xfer_size);
+ if(settings.addr_gran == WORD)
+ case(g_data_width)
+ 8: return addr;
+ 16: return addr >> 1;
+ 32: return addr >> 2;
+ 64: return addr >> 3;
+ default: $error("IWishbone: invalid WB data bus width [%d bits\n]", g_data_width);
+ endcase // case (xfer_size)
+ else
+ return addr;
+ endfunction
+
+ function automatic logic[63:0] rev_bits(logic [63:0] x, int nbits);
+ logic[63:0] tmp;
+ int i;
+
+ for (i=0;i<nbits;i++)
+ tmp[nbits-1-i] = x[i];
+
+ return tmp;
+ endfunction // rev_bits
+
+
+ //FIXME: little endian
+ function automatic logic[(g_data_width/8)-1:0] gen_sel(uint64_t addr, int xfer_size, int little_endian);
+ logic [(g_data_width/8)-1:0] sel;
+ const int dbytes = (g_data_width/8-1);
+
+
+ sel = ((1<<xfer_size) - 1);
+
+ return rev_bits(sel << (addr % xfer_size), g_data_width/8);
+ endfunction
+
+ function automatic logic[g_data_width-1:0] gen_data(uint64_t addr, uint64_t data, int xfer_size, int little_endian);
+ const int dbytes = (g_data_width/8-1);
+ logic[g_data_width-1:0] tmp;
+
+ tmp = data << (8 * (dbytes - (xfer_size - 1 - (addr % xfer_size))));
+
+// $display("GenData: xs %d dbytes %d %x", tmp, xfer_size, dbytes);
+
+
+ return tmp;
+
+ endfunction // gen_data
+
+ function automatic uint64_t decode_data(uint64_t addr, logic[g_data_width-1:0] data, int xfer_size);
+ int rem;
+
+ // $display("decode: a %x d %x xs %x", addr, data ,xfer_size);
+
+
+ rem = addr % xfer_size;
+ return (data >> (8*rem)) & ((1<<(xfer_size*8)) - 1);
+ endfunction // decode_data
+
+
+ task automatic classic_cycle
+ (
+ inout wb_xfer_t xfer[],
+ input bit rw,
+ input int n_xfers,
+ output wb_cycle_result_t result
+ );
+
+ int i;
+
+ if($time != last_access_t)
+ @(posedge clk_i); /* resynchronize, just in case */
+
+ for(i=0;i<n_xfers;i++)
+ begin
+
+ stb <= 1'b1;
+ cyc <= 1'b1;
+ adr <= gen_addr(xfer[i].a, xfer[i].size);
+ we <= rw;
+ sel <= gen_sel(xfer[i].a, xfer[i].size, settings.little_endian);
+//gen_sel(xfer[i].a, xfer[i].size);
+ dat_o <= gen_data(xfer[i].a, xfer[i].d, xfer[i].size, settings.little_endian);
+
+ @(posedge clk_i);
+
+ if(ack == 0) begin
+ while(ack == 0) begin @(posedge clk_i); end
+ end else if(err == 1'b1 || rty == 1'b1)
+ begin
+ cyc <= 0;
+ we <= 0;
+ stb <= 0;
+ result = (err ==1'b1 ? R_ERROR: R_RETRY);
+ break;
+ end
+
+ xfer[i].d = decode_data(xfer[i].a, dat_i, xfer[i].size);
+
+ cyc <= 0;
+ we <= 0;
+ stb <= 0;
+
+ end // if (ack == 0)
+
+ @(posedge clk_i);
+
+ result = R_OK;
+ last_access_t = $time;
+ endtask // automatic
+
+ reg xf_idle = 1;
+
+
+ int ack_cnt_int;
+
+ always@(posedge clk_i)
+ begin
+ if(!cyc)
+ ack_cnt_int <= 0;
+ else if(stb && !stall && !ack)
+ ack_cnt_int++;
+ else if((!stb || stall) && ack)
+ ack_cnt_int--;
+ end
+
+
+ task automatic count_ack(ref int ack_cnt);
+// if(stb && !stall && !ack)
+// ack_cnt++;
+ if (ack)
+ ack_cnt--;
+ endtask
+
+ task automatic handle_readback(ref wb_xfer_t xf [$], input int read, ref int cur_rdbk);
+ if(ack && read)
+ begin
+ xf[cur_rdbk].d = dat_i;
+ cur_rdbk++;
+ end
+ endtask // handle_readback
+
+
+ task automatic pipelined_cycle
+ (
+ ref wb_xfer_t xfer[$],
+ input int write,
+ input int n_xfers,
+ output wb_cycle_result_t result
+ );
+
+ int i;
+ int ack_count ;
+ int failure ;
+ int cur_rdbk;
+
+
+ ack_count = 0;
+ failure = 0;
+
+ xf_idle = 0;
+ cur_rdbk = 0;
+
+
+ if($time != last_access_t)
+ @(posedge clk_i); /* resynchronize, just in case */
+
+ while(stall && !settings.cyc_on_stall)
+ @(posedge clk_i);
+
+ cyc <= 1'b1;
+ i =0;
+
+ ack_count = n_xfers;
+
+ while(i<n_xfers)
+ begin
+ count_ack(ack_count);
+ handle_readback(xfer, !write, cur_rdbk);
+
+
+ if(err) begin
+ result = R_ERROR;
+ failure = 1;
+ break;
+ end
+
+ if(rty) begin
+ result = R_RETRY;
+ failure = 1;
+ break;
+ end
+
+
+ if (!stall && settings.gen_random_throttling && probability_hit(settings.throttle_prob)) begin
+ stb <= 1'b0;
+ we <= 1'b0;
+ @(posedge clk_i);
+
+
+ end else begin
+ adr <= gen_addr(xfer[i].a, xfer[i].size);
+ stb <= 1'b1;
+ if(write)
+ begin
+ we <= 1'b1;
+ sel <= gen_sel(xfer[i].a, xfer[i].size, settings.little_endian);
+ dat_o <= gen_data(xfer[i].a, xfer[i].d, xfer[i].size, settings.little_endian);
+ end else begin
+ we<=1'b0;
+ sel <= 'hffffffff;
+ end
+
+ @(posedge clk_i);
+ stb <= 1'b0;
+ we <= 1'b0;
+ if(stall)
+ begin
+ stb <= 1'b1;
+
+ if(write)
+ we <= 1'b1;
+
+ while(stall)
+ begin
+ count_ack(ack_count);
+ @(posedge clk_i);
+
+
+ end
+ stb <= 1'b0;
+ we <= 1'b0;
+ end
+ i++;
+ end
+
+ end // for (i =0;i<n_xfers;i++)
+
+
+ while((ack_count > 0) && !failure)
+ begin
+ // $display("AckCount %d", ack_count);
+
+ if(err) begin
+ result = R_ERROR;
+ failure = 1;
+ break;
+ end
+
+ if(rty) begin
+ result = R_RETRY;
+ failure = 1;
+ break;
+ end
+
+
+ count_ack(ack_count);
+ handle_readback(xfer, !write, cur_rdbk);
+
+ if(stb && !ack)
+ ack_count++;
+ else if(!stb && ack)
+ ack_count--;
+ @(posedge clk_i);
+ end
+
+
+
+ cyc <= 1'b0;
+ @(posedge clk_i);
+ if(!failure)
+ result = R_OK;
+ xf_idle = 1;
+ last_access_t = $time;
+ endtask // automatic
+
+
+ wb_cycle_t request_queue[$];
+ wb_cycle_t result_queue[$];
+
+class CIWBMasterAccessor extends CWishboneAccessor;
+
+ function automatic int poll();
+ return 0;
+ endfunction
+
+ task get(ref wb_cycle_t xfer);
+ while(!result_queue.size())
+ @(posedge clk_i);
+ xfer = result_queue.pop_front();
+ endtask
+
+ task clear();
+ endtask // clear
+
+ task put(ref wb_cycle_t xfer);
+ // $display("WBMaster[%d]: PutCycle",g_data_width);
+ request_queue.push_back(xfer);
+ endtask // put
+
+ function int idle();
+ return (request_queue.size() == 0) && xf_idle;
+ endfunction // idle
+endclass // CIWBMasterAccessor
+
+
+ function CIWBMasterAccessor get_accessor();
+ CIWBMasterAccessor tmp;
+ tmp = new;
+ return tmp;
+ endfunction // get_accessoror
+
+ always@(posedge clk_i)
+ if(!rst_n_i)
+ begin
+ request_queue = {};
+ result_queue = {};
+ xf_idle = 1;
+ cyc <= 0;
+ dat_o <= 0;
+ stb <= 0;
+ sel <= 0;
+ adr <= 0;
+ we <= 0;
+ end
+
+ initial begin
+ settings.gen_random_throttling = 0;
+ settings.throttle_prob = 0.1;
+ settings.cyc_on_stall = 0;
+ settings.addr_gran = WORD;
+ end
+
+
+ initial forever
+ begin
+ @(posedge clk_i);
+
+
+ if(request_queue.size() > 0)
+ begin
+
+
+ wb_cycle_t c;
+ wb_cycle_result_t res;
+
+ c = request_queue.pop_front();
+
+ case(c.ctype)
+ PIPELINED:
+ begin
+ pipelined_cycle(c.data, c.rw, c.data.size(), res);
+ c.result =res;
+ end
+ CLASSIC:
+ begin
+ // $display("WBMaster: got classic cycle [%d, rw %d]", c.data.size(), c.rw);
+ classic_cycle(c.data, c.rw, c.data.size, res);
+
+ c.result =res;
+
+
+ end
+ endcase // case (c.ctype)
+
+ result_queue.push_back(c);
+ end
+ end
+
+
+endinterface // IWishbone
diff --git a/hdl/eb_testbench/if_wb_slave.svh b/hdl/eb_testbench/if_wb_slave.svh
new file mode 100644
index 0000000000000000000000000000000000000000..8fdaea8a3f64ca9fc3236522f304fcc3f937b4a7
--- /dev/null
+++ b/hdl/eb_testbench/if_wb_slave.svh
@@ -0,0 +1,243 @@
+`ifndef __IF_WISHBONE_SLAVE_SVH
+`define __IF_WISHBONE_SLAVE_SVH
+
+`timescale 1ns/1ps
+
+`include "if_wishbone_types.svh"
+`include "if_wishbone_accessor.svh"
+
+
+
+interface IWishboneSlave
+ (
+ input clk_i,
+ input rst_n_i
+ );
+
+ parameter g_addr_width = 32;
+ parameter g_data_width = 32;
+
+
+ wire [g_addr_width - 1: 0] adr;
+ wire [g_data_width - 1: 0] dat_i;
+ wire [(g_data_width/8)-1 : 0] sel;
+ logic [g_data_width - 1 : 0] dat_o;
+ logic ack;
+ logic stall;
+ logic err;
+ logic rty;
+ wire cyc;
+ wire stb;
+ wire we;
+
+
+
+ time last_access_t = 0;
+
+ modport slave
+ (
+ input adr,
+ input dat_o,
+ input sel,
+ input cyc,
+ input stb,
+ input we,
+ output ack,
+ output dat_i,
+ output stall,
+ output err,
+ output rty
+ );
+
+ wb_cycle_t c_queue[$];
+ wb_cycle_t current_cycle;
+
+ reg cyc_prev;
+ int trans_index;
+ int first_transaction;
+
+ struct {
+ wb_cycle_type_t mode;
+ int gen_random_stalls;
+ int stall_min_duration;
+ int stall_max_duration;
+ real stall_prob;
+ } settings;
+
+
+ function automatic int _poll(); return poll(); endfunction
+ task automatic _get(ref wb_cycle_t xfer); get(xfer); endtask
+
+
+ class CIWBSlaveAccessor extends CWishboneAccessor;
+
+ function automatic int poll();
+ return _poll();
+ endfunction
+
+ task get(ref wb_cycle_t xfer);
+ _get(xfer);
+ endtask
+
+ task clear();
+ endtask // clear
+
+ endclass // CIWBSlaveAccessor
+
+
+ function CIWBSlaveAccessor get_accessor();
+ CIWBSlaveAccessor tmp;
+ tmp = new;
+ return tmp;
+ endfunction // get_accessor
+
+
+ function automatic int poll();
+ return c_queue.size() != 0;
+ endfunction // poll
+
+ task automatic get(ref wb_cycle_t xfer);
+ while(c_queue.size() <= 0)
+ @(posedge clk_i);
+
+ xfer = c_queue.pop_front();
+ endtask // pop_cycle
+
+
+ always@(posedge clk_i) cyc_prev <= cyc;
+ wire cyc_start = !cyc_prev && cyc;
+ wire cyc_end = cyc_prev && !cyc;
+
+
+ task gen_random_stalls();
+ static int stall_remaining = 0;
+ static int seed = 0;
+
+// $display("stallr: %d\n", stall_remaining);
+
+ if(settings.gen_random_stalls && (probability_hit(settings.stall_prob) || stall_remaining > 0))
+ begin
+
+ if(stall_remaining == 0)
+ stall_remaining = $dist_uniform(seed,
+ settings.stall_min_duration,
+ settings.stall_max_duration);
+ if(stall_remaining)
+ stall_remaining--;
+
+ stall <= 1;
+ end else
+ stall <= 0;
+
+
+ endtask // gen_random_stalls
+
+ function automatic int count_ones(int x, int n_bits);
+ int i, cnt;
+ cnt = 0;
+ for(i=0;i<n_bits;i++) if(x & (1<<i)) cnt ++;
+ return cnt;
+ endfunction
+
+ function automatic int count_leading_zeroes(int x, int n_bits);
+ int i;
+ for(i=0;i<n_bits && !(x & (1<<i)); i++);
+ return i;
+ endfunction // count_leading_zeroes
+
+ function automatic int count_trailing_zeroes(int x, int n_bits);
+ int i;
+ for(i=n_bits-1;i>=0 && !(x & (1<<i)); i--);
+ return (n_bits-1-i);
+ endfunction
+
+
+ task pipelined_fsm();
+
+ if(settings.gen_random_stalls)
+ gen_random_stalls();
+ else
+ stall <= 0;
+
+/* -----\/----- EXCLUDED -----\/-----
+ if(cyc) begin
+
+ end else
+ stall <= 0;
+ -----/\----- EXCLUDED -----/\----- */
+
+ if(cyc_start) begin
+ current_cycle.data = {};
+ trans_index <= 0;
+ first_transaction = 1;
+ end
+
+ if(cyc_end) begin
+ c_queue.push_back(current_cycle);
+ end
+
+ if(stb && we && !stall && cyc) begin
+ int oc, lzc, tzc;
+
+ wb_xfer_t d;
+
+ oc = count_ones(sel, g_data_width/8);
+ lzc = count_leading_zeroes(sel, g_data_width/8);
+ tzc = count_trailing_zeroes(sel, g_data_width/8);
+ d.a = adr * (g_data_width / 8);
+ d.size = oc;
+ d.d = (dat_i>>(8*lzc)) & ((1<<(oc*8)) -1);
+
+ if(lzc + tzc + oc != g_data_width/8)
+ $error("IWishboneSlave [write a %x d %x sel %x]: non-contiguous sel", adr, dat_i, sel);
+
+ d.sel [g_data_width/8-1:0] = sel;
+
+ current_cycle.data.push_back(d);
+
+// $display("ifWb:[%d] write a %x d %x sel %x",current_cycle.data.size(), adr, dat_i, sel);
+ ack <= 1;
+
+ end else if(stb && !we && !stall) begin
+// $error("Sorry, no pipelined read for slave yet implemented");
+ ack <= 0;
+ end else
+ ack <= 0;
+
+
+
+ endtask // pipelined_fsm
+
+ always@(posedge clk_i)
+ begin
+ if(!rst_n_i)
+ begin
+ c_queue = {};
+ current_cycle.data = {};
+ trans_index = 0;
+ ack <= 0;
+ rty <= 0;
+ err <= 0;
+ dat_o <= 0;
+ stall <= 0;
+
+ end else begin
+ if(settings.mode == PIPELINED)
+ pipelined_fsm();
+ end
+ end
+
+ initial begin
+ settings.mode = PIPELINED;
+ settings.gen_random_stalls = 1;
+ settings.stall_prob = 0.1;
+ settings.stall_min_duration = 1;
+ settings.stall_max_duration = 2;
+
+ end
+
+
+
+endinterface // IWishboneSlave
+
+`endif
\ No newline at end of file
diff --git a/hdl/eb_testbench/if_wb_slave.svh.bak b/hdl/eb_testbench/if_wb_slave.svh.bak
new file mode 100644
index 0000000000000000000000000000000000000000..9610fdcf757a26e8774c8cba5fa9345d4537b2c9
--- /dev/null
+++ b/hdl/eb_testbench/if_wb_slave.svh.bak
@@ -0,0 +1,242 @@
+`ifndef __IF_WISHBONE_SLAVE_SVH
+`define __IF_WISHBONE_SLAVE_SVH
+
+`timescale 1ns/1ps
+
+`include "if_wishbone_types.svh"
+
+
+
+interface IWishboneSlave
+ (
+ input clk_i,
+ input rst_n_i
+ );
+
+ parameter g_addr_width = 32;
+ parameter g_data_width = 32;
+
+
+ wire [g_addr_width - 1: 0] adr;
+ wire [g_data_width - 1: 0] dat_i;
+ wire [(g_data_width/8)-1 : 0] sel;
+ logic [g_data_width - 1 : 0] dat_o;
+ logic ack;
+ logic stall;
+ logic err;
+ logic rty;
+ wire cyc;
+ wire stb;
+ wire we;
+
+
+
+ time last_access_t = 0;
+
+ modport slave
+ (
+ input adr,
+ input dat_o,
+ input sel,
+ input cyc,
+ input stb,
+ input we,
+ output ack,
+ output dat_i,
+ output stall,
+ output err,
+ output rty
+ );
+
+ wb_cycle_t c_queue[$];
+ wb_cycle_t current_cycle;
+
+ reg cyc_prev;
+ int trans_index;
+ int first_transaction;
+
+ struct {
+ wb_cycle_type_t mode;
+ int gen_random_stalls;
+ int stall_min_duration;
+ int stall_max_duration;
+ real stall_prob;
+ } settings;
+
+
+ function automatic int _poll(); return poll(); endfunction
+ task automatic _get(ref wb_cycle_t xfer); get(xfer); endtask
+
+
+ class CIWBSlaveAccessor extends CWishboneAccessor;
+
+ function automatic int poll();
+ return _poll();
+ endfunction
+
+ task get(ref wb_cycle_t xfer);
+ _get(xfer);
+ endtask
+
+ task clear();
+ endtask // clear
+
+ endclass // CIWBSlaveAccessor
+
+
+ function CIWBSlaveAccessor get_accessor();
+ CIWBSlaveAccessor tmp;
+ tmp = new;
+ return tmp;
+ endfunction // get_accessor
+
+
+ function automatic int poll();
+ return c_queue.size() != 0;
+ endfunction // poll
+
+ task automatic get(ref wb_cycle_t xfer);
+ while(c_queue.size() <= 0)
+ @(posedge clk_i);
+
+ xfer = c_queue.pop_front();
+ endtask // pop_cycle
+
+
+ always@(posedge clk_i) cyc_prev <= cyc;
+ wire cyc_start = !cyc_prev && cyc;
+ wire cyc_end = cyc_prev && !cyc;
+
+
+ task gen_random_stalls();
+ static int stall_remaining = 0;
+ static int seed = 0;
+
+// $display("stallr: %d\n", stall_remaining);
+
+ if(settings.gen_random_stalls && (probability_hit(settings.stall_prob) || stall_remaining > 0))
+ begin
+
+ if(stall_remaining == 0)
+ stall_remaining = $dist_uniform(seed,
+ settings.stall_min_duration,
+ settings.stall_max_duration);
+ if(stall_remaining)
+ stall_remaining--;
+
+ stall <= 1;
+ end else
+ stall <= 0;
+
+
+ endtask // gen_random_stalls
+
+ function automatic int count_ones(int x, int n_bits);
+ int i, cnt;
+ cnt = 0;
+ for(i=0;i<n_bits;i++) if(x & (1<<i)) cnt ++;
+ return cnt;
+ endfunction
+
+ function automatic int count_leading_zeroes(int x, int n_bits);
+ int i;
+ for(i=0;i<n_bits && !(x & (1<<i)); i++);
+ return i;
+ endfunction // count_leading_zeroes
+
+ function automatic int count_trailing_zeroes(int x, int n_bits);
+ int i;
+ for(i=n_bits-1;i>=0 && !(x & (1<<i)); i--);
+ return (n_bits-1-i);
+ endfunction
+
+
+ task pipelined_fsm();
+
+ if(settings.gen_random_stalls)
+ gen_random_stalls();
+ else
+ stall <= 0;
+
+/* -----\/----- EXCLUDED -----\/-----
+ if(cyc) begin
+
+ end else
+ stall <= 0;
+ -----/\----- EXCLUDED -----/\----- */
+
+ if(cyc_start) begin
+ current_cycle.data = {};
+ trans_index <= 0;
+ first_transaction = 1;
+ end
+
+ if(cyc_end) begin
+ c_queue.push_back(current_cycle);
+ end
+
+ if(stb && we && !stall && cyc) begin
+ int oc, lzc, tzc;
+
+ wb_xfer_t d;
+
+ oc = count_ones(sel, g_data_width/8);
+ lzc = count_leading_zeroes(sel, g_data_width/8);
+ tzc = count_trailing_zeroes(sel, g_data_width/8);
+ d.a = adr * (g_data_width / 8);
+ d.size = oc;
+ d.d = (dat_i>>(8*lzc)) & ((1<<(oc*8)) -1);
+
+ if(lzc + tzc + oc != g_data_width/8)
+ $error("IWishboneSlave [write a %x d %x sel %x]: non-contiguous sel", adr, dat_i, sel);
+
+ d.sel [g_data_width/8-1:0] = sel;
+
+ current_cycle.data.push_back(d);
+
+// $display("ifWb:[%d] write a %x d %x sel %x",current_cycle.data.size(), adr, dat_i, sel);
+ ack <= 1;
+
+ end else if(stb && !we && !stall) begin
+// $error("Sorry, no pipelined read for slave yet implemented");
+ ack <= 0;
+ end else
+ ack <= 0;
+
+
+
+ endtask // pipelined_fsm
+
+ always@(posedge clk_i)
+ begin
+ if(!rst_n_i)
+ begin
+ c_queue = {};
+ current_cycle.data = {};
+ trans_index = 0;
+ ack <= 0;
+ rty <= 0;
+ err <= 0;
+ dat_o <= 0;
+ stall <= 0;
+
+ end else begin
+ if(settings.mode == PIPELINED)
+ pipelined_fsm();
+ end
+ end
+
+ initial begin
+ settings.mode = PIPELINED;
+ settings.gen_random_stalls = 1;
+ settings.stall_prob = 0.1;
+ settings.stall_min_duration = 1;
+ settings.stall_max_duration = 2;
+
+ end
+
+
+
+endinterface // IWishboneSlave
+
+`endif
\ No newline at end of file
diff --git a/hdl/eb_testbench/if_wishbone_accessor.svh b/hdl/eb_testbench/if_wishbone_accessor.svh
new file mode 100644
index 0000000000000000000000000000000000000000..b0f789719d420305c934cf6589576cde971b3eb4
--- /dev/null
+++ b/hdl/eb_testbench/if_wishbone_accessor.svh
@@ -0,0 +1,137 @@
+`ifndef IF_WISHBONE_ACCESSOR_SV
+`define IF_WISHBONE_ACCESSOR_SV
+
+`include "if_wishbone_types.svh"
+
+virtual class CWishboneAccessor extends CBusAccessor;
+
+ static int _null = 0;
+ protected wb_cycle_type_t m_cycle_type;
+
+ function new();
+ m_cycle_type = CLASSIC;
+ endfunction // new
+
+ virtual task set_mode(wb_cycle_type_t mode);
+ m_cycle_type = mode;
+ endtask // set_mode
+
+
+ // [slave only] checks if there are any transactions in the queue
+ virtual function automatic int poll();
+ return 0;
+ endfunction // poll
+
+ // [slave only] adds a simulation event (e.g. a forced STALL, RETRY, ERROR)
+ // evt = event type (STALL, ERROR, RETRY)
+ // behv = event behavior: DELAYED - event occurs after a predefined delay (dly_start)
+ // RANDOM - event occurs randomly with probability (prob)
+ // These two can be combined (random events occuring after a certain initial delay)
+ // DELAYED events can be repeated (rep_rate parameter)
+ virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);
+
+ endtask // add_event
+
+
+ // [slave only] gets a cycle from the queue
+ virtual task get(ref wb_cycle_t xfer);
+
+ endtask // get
+
+ // [master only] executes a cycle and returns its result
+ virtual task put(ref wb_cycle_t xfer);
+
+ endtask // put
+
+ virtual function int idle();
+ return 1;
+ endfunction // idle
+
+ // [master only] generic write(s), blocking
+ virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);
+ wb_cycle_t cycle;
+ int i;
+
+ cycle.ctype = m_cycle_type;
+ cycle.rw = 1'b1;
+
+ for(i=0;i < addr.size(); i++)
+ begin
+ wb_xfer_t xfer;
+ xfer.a = addr[i];
+ xfer.d = data[i];
+ xfer.size = size;
+ cycle.data.push_back(xfer);
+ end
+
+// $display("DS: %d", cycle.data.size());
+
+ put(cycle);
+ get(cycle);
+ result = cycle.result;
+
+ endtask // write
+
+ // [master only] generic read(s), blocking
+ virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);
+ wb_cycle_t cycle;
+ int i;
+
+ cycle.ctype = m_cycle_type;
+ cycle.rw = 1'b0;
+
+ for(i=0;i < addr.size(); i++)
+ begin
+ wb_xfer_t xfer;
+ xfer.a = addr[i];
+ xfer.size = size;
+ cycle.data.push_back(xfer);
+ end
+
+ put(cycle);
+ get(cycle);
+
+ for(i=0;i < addr.size(); i++)
+ data[i] = cycle.data[i].d;
+
+ result = cycle.result;
+
+ endtask // readm
+
+ virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
+ uint64_t aa[], da[];
+ aa = new[1];
+ da = new[1];
+ aa[0] = addr;
+ readm(aa, da, size, result);
+ data = da[0];
+ endtask
+
+ virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);
+ uint64_t aa[], da[];
+ aa = new[1];
+ da = new[1];
+
+ aa[0] = addr;
+ da[0] = data;
+ writem(aa, da, size, result);
+ endtask
+
+endclass // CWishboneAccessor
+
+static int seed = 0;
+
+function automatic int probability_hit(real prob);
+ real rand_val;
+ rand_val = real'($dist_uniform(seed, 0, 1000)) / 1000.0;
+
+ if(rand_val < prob)
+ return 1;
+ else
+ return 0;
+
+endfunction // probability_hit
+
+
+`endif // `ifndef IF_WISHBONE_ACCESSOR_SV
+
diff --git a/hdl/eb_testbench/if_wishbone_defs.svh b/hdl/eb_testbench/if_wishbone_defs.svh
new file mode 100644
index 0000000000000000000000000000000000000000..3b13f1101a61edcba86bf9ece25bd184dab5b874
--- /dev/null
+++ b/hdl/eb_testbench/if_wishbone_defs.svh
@@ -0,0 +1,77 @@
+//
+// Title : Software Wishbone master unit for testbenches
+//
+// File : wishbone_master_tb.v
+// Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+// Created : Tue Mar 23 12:19:36 2010
+// Standard : Verilog 2001
+//
+
+`ifndef __IF_WB_DEFS_SV
+`define __IF_WB_DEFS_SV
+
+`include "simdrv_defs.sv"
+
+typedef enum
+{
+ R_OK = 0,
+ R_ERROR,
+ R_RETRY
+} wb_cycle_result_t;
+
+typedef enum
+{
+ CLASSIC = 0,
+ PIPELINED = 1
+} wb_cycle_type_t;
+
+typedef struct {
+ uint64_t a;
+ uint64_t d;
+ bit[7:0] sel;
+ int size;
+} wb_xfer_t;
+
+typedef struct {
+ int rw;
+ wb_cycle_type_t ctype;
+ wb_xfer_t data[$];
+ wb_cycle_result_t result;
+} wb_cycle_t;
+
+
+virtual class CWishboneAccessor;
+
+ virtual function automatic int poll();
+ return 0;
+ endfunction // poll
+
+ virtual task get(output wb_cycle_t xfer);
+ endtask // get
+
+ virtual task put(input wb_cycle_t xfer);
+ endtask // put
+
+ virtual function int idle();
+ return 0;
+ endfunction // idle
+
+ virtual task clear(); endtask
+
+endclass // CWishboneAccessor
+
+int seed = 0;
+
+ function automatic int probability_hit(real prob);
+ real rand_val;
+ rand_val = real'($dist_uniform(seed, 0, 1000)) / 1000.0;
+
+ if(rand_val < prob)
+ return 1;
+ else
+ return 0;
+
+ endfunction // probability_hit
+
+
+`endif // `ifndef __IF_WB_DEFS_SV
diff --git a/hdl/eb_testbench/if_wishbone_types.svh b/hdl/eb_testbench/if_wishbone_types.svh
new file mode 100644
index 0000000000000000000000000000000000000000..5849afe7a12241f1ca2aa5bbfb60b5091b2ee03d
--- /dev/null
+++ b/hdl/eb_testbench/if_wishbone_types.svh
@@ -0,0 +1,61 @@
+//
+// Title : Pipelined Wishbone BFM - type definitions
+//
+// File : if_wishbone_types.sv
+// Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+// Created : Tue Mar 23 12:19:36 2010
+// Standard : Verilog 2001
+//
+
+`ifndef __IF_WB_TYPES_SVH
+`define __IF_WB_TYPES_SVH
+
+`include "simdrv_defs.svh"
+
+typedef enum
+{
+ R_OK = 0,
+ R_ERROR,
+ R_RETRY
+} wb_cycle_result_t;
+
+typedef enum
+{
+ CLASSIC = 0,
+ PIPELINED = 1
+} wb_cycle_type_t;
+
+typedef enum {
+ WORD = 0,
+ BYTE = 1
+} wb_address_granularity_t;
+
+typedef struct {
+ uint64_t a;
+ uint64_t d;
+ int size;
+ bit [7:0] sel;
+} wb_xfer_t;
+
+typedef struct {
+ int rw;
+ wb_cycle_type_t ctype;
+ wb_xfer_t data[$];
+ wb_cycle_result_t result;
+} wb_cycle_t;
+
+typedef enum
+ {
+ RETRY = 0,
+ STALL,
+ ERROR
+} wba_sim_event_t;
+
+typedef enum
+{
+ RANDOM = (1<<0),
+ DELAYED = (1<<1)
+ } wba_sim_behavior_t;
+
+`endif // `ifndef __IF_WB_TYPES_SVH
+
diff --git a/hdl/eb_testbench/license.vhd b/hdl/eb_testbench/license.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..27414dc25cb4fe76daa20d7e200ba0770cc20313
--- /dev/null
+++ b/hdl/eb_testbench/license.vhd
@@ -0,0 +1,20 @@
+/* Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH.
+ *
+ * Author: M. Kreider
+ *
+ */
+
+
+This library is free software; you can redistribute it and/or modify it
+under the terms of the GNU Library General Public License as published
+by the Free Software Foundation; either version 2 of the License, or (at
+your option) any later version.
+
+This library is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with this library. If not, see <http://www.gnu.org/licenses/>.
+
diff --git a/hdl/eb_testbench/main.sv b/hdl/eb_testbench/main.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0fb73dcfe29a91fdd0b33a60bcbbfe9c216f5569
--- /dev/null
+++ b/hdl/eb_testbench/main.sv
@@ -0,0 +1,251 @@
+/* Some basic definitions: types, abstract BusAccessor class */
+`include "simdrv_defs.svh"
+
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+`include "wb_binary_file_source.svh"
+`include "wb_packet_sink.svh"
+
+
+module main;
+
+ wire m_cyc,m_we,m_stb;
+ wire[3:0]m_sel;
+ wire[31:0]m_adr,m_wrdat;
+ logic [31:0] m_rddat;
+ logic m_ack;
+
+/* clock & reset generator */
+ reg clk_sys = 1'b0;
+ reg rst_n = 1'b0;
+
+ always #5ns clk_sys <= ~clk_sys;
+ initial begin
+ repeat(3) @(posedge clk_sys);
+ rst_n <= 1'b1;
+ end
+
+/* A wishbone master, sending the packets to the MiniBone.
+ Controlled via child CWishboneAccessor object. */
+ IWishboneMaster
+ #(
+ .g_data_width(16),
+ .g_addr_width(2))
+ U_source
+ (
+ .clk_i(clk_sys),
+ .rst_n_i(rst_n)
+ );
+
+ /* A Wishbone slave. Receives the packets produced by the MiniBone. */
+ IWishboneSlave
+ #(
+ .g_data_width(16),
+ .g_addr_width(2))
+ U_sink
+ (
+ .clk_i(clk_sys),
+ .rst_n_i(rst_n)
+ );
+
+ EB_CORE
+ #(
+ .g_master_slave(0))
+ DUT
+ (
+ .clk_i (clk_sys),
+ .nRst_i (rst_n),
+
+ /* Packet I/O - from the Endpoint to the MB */
+
+ .snk_cyc_i (U_source.master.cyc),
+ .snk_stb_i (U_source.master.stb),
+ .snk_dat_i (U_source.master.dat_o),
+ .snk_sel_i (U_source.master.sel),
+ .snk_adr_i (U_source.master.adr),
+ .snk_we_i (U_source.master.we),
+ .snk_stall_o(U_source.master.stall),
+ .snk_ack_o (U_source.master.ack),
+
+ /* Packet I/O - from the MB to the Endpoint */
+ .src_cyc_o (U_sink.slave.cyc),
+ .src_stb_o (U_sink.slave.stb),
+ .src_dat_o (U_sink.slave.dat_i),
+ .src_adr_o (U_sink.slave.adr),
+ .src_sel_o (U_sink.slave.sel),
+ .src_we_o (U_sink.slave.we),
+ .src_ack_i (U_sink.slave.ack),
+ .src_stall_i (U_sink.slave.stall),
+
+ /* WB Master driving the memory */
+ .master_cyc_o (m_cyc),
+ .master_we_o (m_we),
+ .master_stb_o (m_stb),
+ .master_sel_o (m_sel),
+ .master_adr_o (m_adr),
+ .master_dat_o (m_wrdat),
+ .master_dat_i (m_rddat),
+ .master_ack_i (m_ack),
+ .master_stall_i (1'b0)
+ );
+
+ logic [31:0] mem[65536];
+
+ /* a trivial wishbone memory model */
+ always@(posedge clk_sys)
+ if(!rst_n) begin
+ m_ack <= 0;
+ m_rddat <= 0;
+ end else begin
+ if(m_cyc && m_stb) begin
+ if(m_we)
+ begin
+ /* $display("MemWrite: addr %x data %x", m_adr, m_wrdat); */
+ mem[m_adr[15:0]] <= m_wrdat;
+ end
+ m_rddat <= mem[m_adr[15:0]];
+ m_ack <= 1;
+ end
+ else m_ack <= 0;
+
+ end
+
+ /* Packet Source and Sink objects - these objects translate Ethernet packets into/from
+ Wishbone bus transactions, extracting the statuses and OOB */
+ WBPacketSource src;
+ WBPacketSink sink;
+
+ /* Executes a write cycle using minibone */
+ task mbone_write(uint32_t addr, uint32_t data);
+ EthPacket pkt;
+ pkt = new;
+
+ /* some dummy addresses */
+ pkt.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
+ pkt.src = '{1,2,3,4,5,6};
+ pkt.ethertype = 'ha0a0;
+
+ /* set the payload size to the minimum acceptable value:
+ (46 bytes payload + 14 bytes header + 4 bytes CRC) */
+ pkt.set_size(46);
+
+ /* .. and fill in the packet structure */
+ pkt.payload[0] = 0;
+ pkt.payload[1] = 'h1f; /* Flags (write = 1, SEL = 0xf) */
+
+ pkt.payload[2] = (addr >> 24) & 'hff;
+ pkt.payload[3] = (addr >> 16) & 'hff;
+ pkt.payload[4] = (addr >> 8) & 'hff;
+ pkt.payload[5] = (addr >> 0) & 'hff;
+
+ pkt.payload[6] = (data >> 24) & 'hff;
+ pkt.payload[7] = (data >> 16) & 'hff;
+ pkt.payload[8] = (data >> 8) & 'hff;
+ pkt.payload[9] = (data >> 0) & 'hff;
+
+ /* send the packet */
+ src.send(pkt);
+ /* and receive the reply. No error handling yet. */
+ sink.recv(pkt);
+ endtask // mbone_write
+
+
+ /* The same thing, but for reads */
+ task mbone_read(uint32_t addr, output uint32_t data);
+ EthPacket pkt;
+ pkt = new;
+
+
+ pkt.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
+ pkt.src = '{1,2,3,4,5,6};
+ pkt.ethertype = 'h0800;
+ pkt.set_size(46);
+
+ pkt.payload[0] = 0;
+ pkt.payload[1] = 'h0f;
+
+ pkt.payload[2] = (addr >> 24) & 'hff;
+ pkt.payload[3] = (addr >> 16) & 'hff;
+ pkt.payload[4] = (addr >> 8) & 'hff;
+ pkt.payload[5] = (addr >> 0) & 'hff;
+
+ src.send(pkt);
+ sink.recv(pkt);
+
+ // pkt.dump();
+
+ if((pkt.payload[1] & 3) == 1)
+ begin
+ reg[31:0] d;
+ d[31:24] = pkt.payload[2];
+ d[23:16] = pkt.payload[3];
+ d[15:8] = pkt.payload[4];
+ d[7:0] = pkt.payload[5];
+ data = d;
+ end
+
+ endtask // mbone_read
+
+
+
+
+ initial begin
+ int i, retries;
+ uint32_t rval;
+ int seed;
+
+
+ #1us;
+
+ /* Create the sink/source objects - they communicate with the WB Master/Slave using an Accessor
+ object:
+ Ethernet Packet (eth_packet_t) -> src->send() -> serialization -> sequence of reads/writes -> accessor -> IWishboneMaster -> device under test */
+ src = new(U_source.get_accessor());
+ sink = new(U_sink.get_accessor());
+
+ /* Make the things not ideal */
+ U_source.settings.throttle_prob = 0.1;
+ U_source.settings.gen_random_throttling = 1; /* 10% probability of STB going low */
+
+ U_sink.settings.stall_prob = 0.1;
+ U_sink.settings.gen_random_stalls = 1; /* 10 % probability of STALL event, stalls 1-3 cycles long */
+ U_sink.settings.stall_min_duration = 1;
+ U_sink.settings.stall_max_duration = 3;
+
+
+ /* try executing a bunch of random writes and verify if the written data is where it should be */
+
+ for(retries = 0; retries <10; retries++)
+ begin
+ const int n_writes = 100;
+
+ $display("Iteration %d", retries);
+
+
+ seed = retries;
+
+ for(i=0;i<n_writes;i++)
+ mbone_write(i, $dist_uniform(seed, 0, (1<<31)-1));
+
+ seed = retries;
+ for(i=0;i<n_writes;i++)
+ begin
+ mbone_read(i, rval);
+ if(rval != $dist_uniform(seed, 0, (1<<31)-1))
+
+ begin
+ $error("Inconsistency at %d", i);
+ $stop;
+ end
+ end
+
+ end
+
+ $display("Test passed");
+ $stop;
+
+ end
+
+endmodule // main
+
+
diff --git a/hdl/eb_testbench/main.sv.bak b/hdl/eb_testbench/main.sv.bak
new file mode 100644
index 0000000000000000000000000000000000000000..bd36d07b8f80465c85700ff1ecc18dcccf89616c
--- /dev/null
+++ b/hdl/eb_testbench/main.sv.bak
@@ -0,0 +1,251 @@
+/* Some basic definitions: types, abstract BusAccessor class */
+`include "simdrv_defs.svh"
+
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+`include "wb_binary_file_source.svh"
+`include "wb_packet_sink.svh"
+
+
+module main;
+
+ wire m_cyc,m_we,m_stb;
+ wire[3:0]m_sel;
+ wire[31:0]m_adr,m_wrdat;
+ logic [31:0] m_rddat;
+ logic m_ack;
+
+/* clock & reset generator */
+ reg clk_sys = 1'b0;
+ reg rst_n = 1'b0;
+
+ always #5ns clk_sys <= ~clk_sys;
+ initial begin
+ repeat(3) @(posedge clk_sys);
+ rst_n <= 1'b1;
+ end
+
+/* A wishbone master, sending the packets to the MiniBone.
+ Controlled via child CWishboneAccessor object. */
+ IWishboneMaster
+ #(
+ .g_data_width(16),
+ .g_addr_width(2))
+ U_source
+ (
+ .clk_i(clk_sys),
+ .rst_n_i(rst_n)
+ );
+
+ /* A Wishbone slave. Receives the packets produced by the MiniBone. */
+ IWishboneSlave
+ #(
+ .g_data_width(16),
+ .g_addr_width(2))
+ U_sink
+ (
+ .clk_i(clk_sys),
+ .rst_n_i(rst_n)
+ );
+
+ EB_CORE
+ #(
+ .g_master_slave(0))
+ DUT
+ (
+ .clk_i (clk_sys),
+ .nRst_i (rst_n),
+
+ /* Packet I/O - from the Endpoint to the MB */
+
+ .snk_cyc_i (U_source.master.cyc),
+ .snk_stb_i (U_source.master.stb),
+ .snk_dat_i (U_source.master.dat_o),
+ .snk_sel_i (U_source.master.sel),
+ .snk_adr_i (U_source.master.adr),
+ .snk_we_i (U_source.master.we),
+ .snk_stall_o(U_source.master.stall),
+ .snk_ack_o (U_source.master.ack),
+
+ /* Packet I/O - from the MB to the Endpoint */
+ .src_cyc_o (U_sink.slave.cyc),
+ .src_stb_o (U_sink.slave.stb),
+ .src_dat_o (U_sink.slave.dat_i),
+ .src_adr_o (U_sink.slave.adr),
+ .src_sel_o (U_sink.slave.sel),
+ .src_we_o (U_sink.slave.we),
+ .src_ack_i (U_sink.slave.ack),
+ .src_stall_i (U_sink.slave.stall),
+
+ /* WB Master driving the memory */
+ .master_cyc_o (m_cyc),
+ .master_we_o (m_we),
+ .master_stb_o (m_stb),
+ .master_sel_o (m_sel),
+ .master_adr_o (m_adr),
+ .master_dat_o (m_wrdat),
+ .master_dat_i (m_rddat),
+ .master_ack_i (m_ack),
+ .master_stall_i (1'b0)
+ );
+
+ logic [31:0] mem[65536];
+
+ /* a trivial wishbone memory model */
+ always@(posedge clk_sys)
+ if(!rst_n) begin
+ m_ack <= 0;
+ m_rddat <= 0;
+ end else begin
+ if(m_ack)
+ m_ack <= 0;
+ else if(m_cyc && m_stb) begin
+ if(m_we)
+ begin
+ /* $display("MemWrite: addr %x data %x", m_adr, m_wrdat); */
+ mem[m_adr[15:0]] <= m_wrdat;
+ end
+ m_rddat <= mem[m_adr[15:0]];
+ m_ack <= 1;
+ end
+ end
+
+ /* Packet Source and Sink objects - these objects translate Ethernet packets into/from
+ Wishbone bus transactions, extracting the statuses and OOB */
+ WBPacketSource src;
+ WBPacketSink sink;
+
+ /* Executes a write cycle using minibone */
+ task mbone_write(uint32_t addr, uint32_t data);
+ EthPacket pkt;
+ pkt = new;
+
+ /* some dummy addresses */
+ pkt.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
+ pkt.src = '{1,2,3,4,5,6};
+ pkt.ethertype = 'ha0a0;
+
+ /* set the payload size to the minimum acceptable value:
+ (46 bytes payload + 14 bytes header + 4 bytes CRC) */
+ pkt.set_size(46);
+
+ /* .. and fill in the packet structure */
+ pkt.payload[0] = 0;
+ pkt.payload[1] = 'h1f; /* Flags (write = 1, SEL = 0xf) */
+
+ pkt.payload[2] = (addr >> 24) & 'hff;
+ pkt.payload[3] = (addr >> 16) & 'hff;
+ pkt.payload[4] = (addr >> 8) & 'hff;
+ pkt.payload[5] = (addr >> 0) & 'hff;
+
+ pkt.payload[6] = (data >> 24) & 'hff;
+ pkt.payload[7] = (data >> 16) & 'hff;
+ pkt.payload[8] = (data >> 8) & 'hff;
+ pkt.payload[9] = (data >> 0) & 'hff;
+
+ /* send the packet */
+ src.send(pkt);
+ /* and receive the reply. No error handling yet. */
+ sink.recv(pkt);
+ endtask // mbone_write
+
+
+ /* The same thing, but for reads */
+ task mbone_read(uint32_t addr, output uint32_t data);
+ EthPacket pkt;
+ pkt = new;
+
+
+ pkt.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
+ pkt.src = '{1,2,3,4,5,6};
+ pkt.ethertype = 'h0800;
+ pkt.set_size(46);
+
+ pkt.payload[0] = 0;
+ pkt.payload[1] = 'h0f;
+
+ pkt.payload[2] = (addr >> 24) & 'hff;
+ pkt.payload[3] = (addr >> 16) & 'hff;
+ pkt.payload[4] = (addr >> 8) & 'hff;
+ pkt.payload[5] = (addr >> 0) & 'hff;
+
+ src.send(pkt);
+ sink.recv(pkt);
+
+ // pkt.dump();
+
+ if((pkt.payload[1] & 3) == 1)
+ begin
+ reg[31:0] d;
+ d[31:24] = pkt.payload[2];
+ d[23:16] = pkt.payload[3];
+ d[15:8] = pkt.payload[4];
+ d[7:0] = pkt.payload[5];
+ data = d;
+ end
+
+ endtask // mbone_read
+
+
+
+
+ initial begin
+ int i, retries;
+ uint32_t rval;
+ int seed;
+
+
+ #1us;
+
+ /* Create the sink/source objects - they communicate with the WB Master/Slave using an Accessor
+ object:
+ Ethernet Packet (eth_packet_t) -> src->send() -> serialization -> sequence of reads/writes -> accessor -> IWishboneMaster -> device under test */
+ src = new(U_source.get_accessor());
+ sink = new(U_sink.get_accessor());
+
+ /* Make the things not ideal */
+ U_source.settings.throttle_prob = 0.1;
+ U_source.settings.gen_random_throttling = 1; /* 10% probability of STB going low */
+
+ U_sink.settings.stall_prob = 0.1;
+ U_sink.settings.gen_random_stalls = 1; /* 10 % probability of STALL event, stalls 1-3 cycles long */
+ U_sink.settings.stall_min_duration = 1;
+ U_sink.settings.stall_max_duration = 3;
+
+
+ /* try executing a bunch of random writes and verify if the written data is where it should be */
+
+ for(retries = 0; retries <10; retries++)
+ begin
+ const int n_writes = 100;
+
+ $display("Iteration %d", retries);
+
+
+ seed = retries;
+
+ for(i=0;i<n_writes;i++)
+ mbone_write(i, $dist_uniform(seed, 0, (1<<31)-1));
+
+ seed = retries;
+ for(i=0;i<n_writes;i++)
+ begin
+ mbone_read(i, rval);
+ if(rval != $dist_uniform(seed, 0, (1<<31)-1))
+
+ begin
+ $error("Inconsistency at %d", i);
+ $stop;
+ end
+ end
+
+ end
+
+ $display("Test passed");
+ $stop;
+
+ end
+
+endmodule // main
+
+
diff --git a/hdl/eb_testbench/mini_bone.vhd b/hdl/eb_testbench/mini_bone.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3f0a7eaa116b9dbddea830fed3b4a01d8c6754e1
--- /dev/null
+++ b/hdl/eb_testbench/mini_bone.vhd
@@ -0,0 +1,150 @@
+--! @file console.vhd
+--! @brief A console macro.
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Foo Bar <f.bar@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.Wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+
+
+
+entity mini_bone is
+ generic(
+ g_class_mask : std_logic_vector(7 downto 0) := x"ff";
+ g_our_ethertype : std_logic_vector(15 downto 0) := x"a0a0");
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ snk_cyc_i : in std_logic;
+ snk_stb_i : in std_logic;
+ snk_sel_i : in std_logic_vector(1 downto 0);
+ snk_adr_i : in std_logic_vector(1 downto 0);
+ snk_dat_i : in std_logic_vector(15 downto 0);
+ snk_we_i : in std_logic;
+ snk_stall_o : out std_logic;
+ snk_ack_o : out std_logic;
+ snk_err_o : out std_logic;
+
+ src_cyc_o : out std_logic;
+ src_stb_o : out std_logic;
+ src_dat_o : out std_logic_vector(15 downto 0);
+ src_adr_o : out std_logic_vector(1 downto 0);
+ src_we_o : out std_logic;
+ src_ack_i : in std_logic;
+ src_err_i : in std_logic;
+ src_sel_o : out std_logic_vector(1 downto 0);
+ src_stall_i : in std_logic;
+
+ master_cyc_o : out std_logic;
+ master_we_o : out std_logic;
+ master_stb_o : out std_logic;
+ master_sel_o : out std_logic_vector(3 downto 0);
+ master_adr_o : out std_logic_vector(31 downto 0);
+ master_dat_o : out std_logic_vector(31 downto 0);
+ master_dat_i : in std_logic_vector(31 downto 0);
+ master_ack_i : in std_logic
+ );
+
+end mini_bone;
+
+
+architecture wrapper of mini_bone is
+
+ component xmini_bone
+ generic (
+ g_class_mask : std_logic_vector(7 downto 0);
+ g_our_ethertype : std_logic_vector(15 downto 0));
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ src_o : out t_wrf_source_out;
+ src_i : in t_wrf_source_in;
+ snk_o : out t_wrf_sink_out;
+ snk_i : in t_wrf_sink_in;
+ master_o : out t_wishbone_master_out;
+ master_i : in t_wishbone_master_in);
+ end component;
+
+
+ signal src_out : t_wrf_source_out;
+ signal src_in : t_wrf_source_in;
+ signal snk_out : t_wrf_sink_out;
+ signal snk_in : t_wrf_sink_in;
+ signal master_out : t_wishbone_master_out;
+ signal master_in : t_wishbone_master_in;
+
+begin -- wrapper
+
+ U_Wrapped_MB : xmini_bone
+ generic map (
+ g_class_mask => g_class_mask,
+ g_our_ethertype => g_our_ethertype)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ src_o => src_out,
+ src_i => src_in,
+ snk_o => snk_out,
+ snk_i => snk_in,
+ master_o => master_out,
+ master_i => master_in);
+
+ src_cyc_o <= src_out.cyc;
+ src_stb_o <= src_out.stb;
+ src_we_o <= src_out.we;
+ src_adr_o <= src_out.adr;
+ src_dat_o <= src_out.dat;
+ src_sel_o <= src_out.sel;
+
+ src_in.ack <= src_ack_i;
+ src_in.stall <= src_stall_i;
+
+
+ snk_in.cyc <= snk_cyc_i;
+ snk_in.stb <= snk_stb_i;
+ snk_in.we <= snk_we_i;
+ snk_in.sel <= snk_sel_i;
+ snk_in.adr <= snk_adr_i;
+ snk_in.dat <= snk_dat_i;
+
+ snk_ack_o <= snk_out.ack;
+ snk_stall_o <= snk_out.stall;
+
+ master_cyc_o <= master_out.cyc;
+ master_stb_o <= master_out.stb;
+ master_we_o <= master_out.we;
+ master_sel_o <= master_out.sel;
+ master_adr_o <= master_out.adr;
+ master_dat_o <= master_out.dat;
+
+ master_in.dat <= master_dat_i;
+ master_in.ack <= master_ack_i;
+
+end wrapper;
diff --git a/hdl/eb_testbench/mini_bone.vhd.bak b/hdl/eb_testbench/mini_bone.vhd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..074413934c49662b752170b40d7fcffc828b0f84
--- /dev/null
+++ b/hdl/eb_testbench/mini_bone.vhd.bak
@@ -0,0 +1,120 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.Wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity mini_bone is
+ generic(
+ g_class_mask : std_logic_vector(7 downto 0) := x"ff";
+ g_our_ethertype : std_logic_vector(15 downto 0) := x"a0a0");
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ snk_cyc_i : in std_logic;
+ snk_stb_i : in std_logic;
+ snk_sel_i : in std_logic_vector(1 downto 0);
+ snk_adr_i : in std_logic_vector(1 downto 0);
+ snk_dat_i : in std_logic_vector(15 downto 0);
+ snk_we_i : in std_logic;
+ snk_stall_o : out std_logic;
+ snk_ack_o : out std_logic;
+ snk_err_o : out std_logic;
+
+ src_cyc_o : out std_logic;
+ src_stb_o : out std_logic;
+ src_dat_o : out std_logic_vector(15 downto 0);
+ src_adr_o : out std_logic_vector(1 downto 0);
+ src_we_o : out std_logic;
+ src_ack_i : in std_logic;
+ src_err_i : in std_logic;
+ src_sel_o : out std_logic_vector(1 downto 0);
+ src_stall_i : in std_logic;
+
+ master_cyc_o : out std_logic;
+ master_we_o : out std_logic;
+ master_stb_o : out std_logic;
+ master_sel_o : out std_logic_vector(3 downto 0);
+ master_adr_o : out std_logic_vector(31 downto 0);
+ master_dat_o : out std_logic_vector(31 downto 0);
+ master_dat_i : in std_logic_vector(31 downto 0);
+ master_ack_i : in std_logic
+ );
+
+end mini_bone;
+
+
+architecture wrapper of mini_bone is
+
+ component xmini_bone
+ generic (
+ g_class_mask : std_logic_vector(7 downto 0);
+ g_our_ethertype : std_logic_vector(15 downto 0));
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ src_o : out t_wrf_source_out;
+ src_i : in t_wrf_source_in;
+ snk_o : out t_wrf_sink_out;
+ snk_i : in t_wrf_sink_in;
+ master_o : out t_wishbone_master_out;
+ master_i : in t_wishbone_master_in);
+ end component;
+
+
+ signal src_out : t_wrf_source_out;
+ signal src_in : t_wrf_source_in;
+ signal snk_out : t_wrf_sink_out;
+ signal snk_in : t_wrf_sink_in;
+ signal master_out : t_wishbone_master_out;
+ signal master_in : t_wishbone_master_in;
+
+begin -- wrapper
+
+ U_Wrapped_MB : xmini_bone
+ generic map (
+ g_class_mask => g_class_mask,
+ g_our_ethertype => g_our_ethertype)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ src_o => src_out,
+ src_i => src_in,
+ snk_o => snk_out,
+ snk_i => snk_in,
+ master_o => master_out,
+ master_i => master_in);
+
+ src_cyc_o <= src_out.cyc;
+ src_stb_o <= src_out.stb;
+ src_we_o <= src_out.we;
+ src_adr_o <= src_out.adr;
+ src_dat_o <= src_out.dat;
+ src_sel_o <= src_out.sel;
+
+ src_in.ack <= src_ack_i;
+ src_in.stall <= src_stall_i;
+
+
+ snk_in.cyc <= snk_cyc_i;
+ snk_in.stb <= snk_stb_i;
+ snk_in.we <= snk_we_i;
+ snk_in.sel <= snk_sel_i;
+ snk_in.adr <= snk_adr_i;
+ snk_in.dat <= snk_dat_i;
+
+ snk_ack_o <= snk_out.ack;
+ snk_stall_o <= snk_out.stall;
+
+ master_cyc_o <= master_out.cyc;
+ master_stb_o <= master_out.stb;
+ master_we_o <= master_out.we;
+ master_sel_o <= master_out.sel;
+ master_adr_o <= master_out.adr;
+ master_dat_o <= master_out.dat;
+
+ master_in.dat <= master_dat_i;
+ master_in.ack <= master_ack_i;
+
+end wrapper;
diff --git a/hdl/eb_testbench/modelsim.ini b/hdl/eb_testbench/modelsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..8a896cd94cd39483e9c1d229462e6bce2c6d9fb8
--- /dev/null
+++ b/hdl/eb_testbench/modelsim.ini
@@ -0,0 +1,1664 @@
+; Copyright 1991-2011 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+vital2000 = $MODEL_TECH/../vital2000
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+verilog = $MODEL_TECH/../verilog
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.2
+mtiUvm = $MODEL_TECH/../uvm-1.1
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+
+altera = $MODEL_TECH/../altera
+altera_mf = $MODEL_TECH/../altera_mf
+;work = $MODEL_TECH/../work
+cyclone = $MODEL_TECH/../cyclone
+cycloneii = $MODEL_TECH/../cycloneii
+lpm = $MODEL_TECH/../lpm
+max = $MODEL_TECH/../max
+maxii = $MODEL_TECH/../maxii
+sgate = $MODEL_TECH/../sgate
+stratix = $MODEL_TECH/../stratix
+stratixgx = $MODEL_TECH/../stratixgx
+stratixgx_gxb = $MODEL_TECH/../stratixgx_gxb
+stratixii = $MODEL_TECH/../stratixii
+secureip = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/secureip
+unisim = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/unisim
+unimacro = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/unimacro
+unisims_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/unisims_ver
+unimacro_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/unimacro_ver
+simprim = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/simprim
+simprims_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/simprims_ver
+xilinxcorelib = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/xilinxcorelib
+xilinxcorelib_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/xilinxcorelib_ver
+uni9000_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/uni9000_ver
+cpld = /opt/hdl/ISE_DS/ISE/vhdl/mti_se/10.0c/lin64/cpld
+cpld_ver = /opt/hdl/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/cpld_ver
+
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is off.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, effects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance
+; SeparateConfigLibrary = 1;
+
+; Change how subprogram out parameter of type array and record are treated.
+; If 1, always initial the out parameter to its default value.
+; If 2, do not initialize the out parameter.
+; The value 0 indicates use the default for the langauge version being compiled.
+; Prior to 10.1 all langauge version did not initialize out composite parameters.
+; 10.1 and later files compile with -2008 initialize by default
+; InitOutCompositeParam = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 20000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 20000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations. The default value is 1000. A
+; value of 0 indicates no limit.
+; SolveACTMaxOps = 1000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints. This
+; 'speculation' set is solved independently of the remaining constraints.
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set). If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+; 0 - no speculation
+; 1 - enable speculation that maintains LRM specified distribution
+; 2 - enable other speculation - may yield non-LRM distribution
+; Currently, distribution constraints and solve-before constraints are
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100.
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+; n = disable bit interleaving for all constraints (BDD engine)
+; r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
diff --git a/hdl/eb_testbench/piso_flag.vhd b/hdl/eb_testbench/piso_flag.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..115c86c85414c157fb506aa86a838aa5d34ad8cf
--- /dev/null
+++ b/hdl/eb_testbench/piso_flag.vhd
@@ -0,0 +1,96 @@
+--! @file piso_flag.vhd
+--! @brief Parallel-In-Serial-Out shiftregister with flags
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity piso_flag is
+generic(g_width_IN : natural := 16; g_width_OUT : natural := 32);
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ ld_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+
+ full_o : out std_logic;
+ almost_empty_o : out std_logic;
+ empty_o : out std_logic
+
+);
+end piso_flag;
+
+
+
+
+architecture behavioral of piso_flag is
+
+signal sh_cnt : unsigned(8 downto 0);
+alias empty : std_logic is sh_cnt(sh_cnt'LEFT);
+
+signal sh_reg : std_logic_vector(g_width_in -1 downto 0);
+constant zero_insert : std_logic_vector(g_width_out-1 downto 0) := (others => '0');
+signal full : std_logic;
+
+
+begin
+almost_empty_o <= '1' when sh_cnt = to_unsigned(0, 9)
+ else '0';
+q_o <= sh_reg(sh_reg'left downto sh_reg'length-q_o'length);
+empty_o <= empty;
+full_o <= full;
+
+ -- Your VHDL code defining the model goes here
+ process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0') then
+ full <= '0';
+ sh_cnt <= (others => '1');
+
+ else
+ if(ld_i = '1' AND full = '0') then
+ full <= '1';
+ sh_cnt <= to_unsigned((g_width_IN/g_width_OUT)-1,9);
+ sh_reg <= d_i;
+ elsif(en_i = '1' AND empty = '0') then
+ full <= '0';
+ sh_cnt <= sh_cnt-1;
+ sh_reg <= sh_reg(g_width_in - g_width_out -1 downto 0) & zero_insert;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/run.do b/hdl/eb_testbench/run.do
new file mode 100644
index 0000000000000000000000000000000000000000..fc3a7d40c341e22cd79ef0d72842fa3839441141
--- /dev/null
+++ b/hdl/eb_testbench/run.do
@@ -0,0 +1,9 @@
+
+vsim -L unisim -t 10fs work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 10ms
+wave zoomfull
+radix -hexadecimal
diff --git a/hdl/eb_testbench/simdrv_defs.svh b/hdl/eb_testbench/simdrv_defs.svh
new file mode 100644
index 0000000000000000000000000000000000000000..e7e04bc799491fe528f0dad39eca62781e9014f3
--- /dev/null
+++ b/hdl/eb_testbench/simdrv_defs.svh
@@ -0,0 +1,104 @@
+`ifndef SIMDRV_DEFS_SV
+ `define SIMDRV_DEFS_SV 1
+
+typedef longint unsigned uint64_t;
+typedef int unsigned uint32_t;
+typedef shortint unsigned uint16_t;
+
+
+
+typedef uint64_t u64_array_t[];
+typedef byte byte_array_t[];
+
+
+
+
+virtual class CBusAccessor;
+ static int _null = 0;
+
+ pure virtual task writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
+ pure virtual task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
+
+ virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
+ int res;
+ uint64_t aa[1], da[];
+
+ da= new[1];
+
+ aa[0] = addr;
+ readm(aa, da, size, res);
+ data = da[0];
+ endtask
+
+
+ virtual task write(uint64_t addr, uint64_t data, input int size = 4, ref int result = _null);
+ uint64_t aa[1], da[1];
+ aa[0] = addr;
+ da[0] = data;
+ writem(aa, da, size, result);
+ endtask
+
+endclass // CBusAccessor
+
+class CSimUtils;
+
+ static function automatic u64_array_t pack(byte x[], int size, int big_endian = 1);
+ u64_array_t tmp;
+ int i, j;
+ int nwords, nbytes;
+
+ nwords = (x.size() + size - 1) / size;
+ tmp = new [nwords];
+
+ for(i=0;i<nwords;i++)
+ begin
+ uint64_t d;
+ d =0;
+ nbytes = (x.size() - i * nbytes > size ? size : x.size() - i*nbytes);
+
+ for(j=0;j<nbytes;j++)
+ begin
+ if(big_endian)
+ d = d | ((x[i*size+j] << (8*(size-1-j))));
+ else
+ d = d | ((x[i*size+j] << (8*j)));
+ end
+
+
+ tmp[i] = d;
+ end
+ return tmp;
+ endfunction // pack
+
+
+ static function automatic byte_array_t unpack(u64_array_t x, int entry_size, int size, int big_endian = 1);
+ byte_array_t tmp;
+ int i, n;
+
+ tmp = new[size];
+ n = 0;
+ i = 0;
+
+
+ while(n < size)
+ begin
+ tmp[n] = x[i] >> (8*(entry_size-1 - (n % entry_size)));
+
+ n++;
+ if(n % entry_size == 0)
+ i++;
+ end
+
+ return tmp;
+ endfunction // unpack
+
+
+
+
+endclass // CSimUtils
+
+static CSimUtils SimUtils;
+
+
+
+`endif
\ No newline at end of file
diff --git a/hdl/eb_testbench/sipo_flag.vhd b/hdl/eb_testbench/sipo_flag.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cbb59942e4a2190810b4c36c2ba36760beee3a82
--- /dev/null
+++ b/hdl/eb_testbench/sipo_flag.vhd
@@ -0,0 +1,96 @@
+--! @file sipo_flag.vhd
+--! @brief Serial-In-Parallel-Out shiftregister with flags
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+---! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.vhdl_2008_workaround_pkg.all;
+
+entity sipo_flag is
+generic(g_width_IN : natural := 8; g_width_OUT : natural := 32);
+port(
+ clk_i : in std_logic;
+ nRst_i : in std_logic;
+
+ d_i : in std_logic_vector(g_width_IN-1 downto 0);
+ en_i : in std_logic;
+ clr_i : in std_logic;
+
+ q_o : out std_logic_vector(g_width_OUT-1 downto 0);
+ full_o : out std_logic;
+ empty_o : out std_logic
+);
+end sipo_flag;
+
+
+
+
+architecture behavioral of sipo_flag is
+
+signal sh_reg : std_logic_vector(g_width_OUT-1 downto 0); -- length + 1 for flag
+signal full : std_logic;
+signal empty : std_logic;
+
+constant check_full : natural := maximum(0, g_width_OUT/g_width_IN-1);
+signal cnt : unsigned(ld(g_width_OUT/g_width_IN) downto 0);
+
+begin
+
+q_o <= sh_reg(sh_reg'left downto 0);
+full_o <= full;
+empty_o <= empty;
+
+ -- Your VHDL code defining the model goes here
+ process (clk_i)
+ begin
+ if (clk_i'event and clk_i = '1') then
+ if(nRSt_i = '0' OR clr_i = '1') then
+ sh_reg <= (others => '0');
+ full <= '0';
+ empty <= '1';
+ cnt <= (others => '0');
+ else
+ if(en_i = '1') then
+ sh_reg <= sh_reg(g_width_OUT-1 - g_width_IN downto 0) & d_i;
+ empty <= '0';
+ full <= '0';
+ cnt <= cnt +1;
+
+ if(cnt = check_full) then -- writing to last space
+ full <= '1';
+ cnt <= (others => '0');
+ end if;
+
+ end if;
+ end if;
+ end if;
+ end process;
+
+end behavioral;
diff --git a/hdl/eb_testbench/test_V4.pcap b/hdl/eb_testbench/test_V4.pcap
new file mode 100644
index 0000000000000000000000000000000000000000..ad5c93ec42d7a59a1f324b5c15e7eb4d6e04b989
Binary files /dev/null and b/hdl/eb_testbench/test_V4.pcap differ
diff --git a/hdl/eb_testbench/vhdl_2008_workaround_pkg.vhd b/hdl/eb_testbench/vhdl_2008_workaround_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a46bc6a7990344af6724df39cf557cbce46b3b65
--- /dev/null
+++ b/hdl/eb_testbench/vhdl_2008_workaround_pkg.vhd
@@ -0,0 +1,113 @@
+--! @file vhdl_2008_workaround_pkg.vhd
+--! @brief VHDL 2008 alike functions
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package vhdl_2008_workaround_pkg is
+
+
+
+function minimum(A : integer; B : integer)
+return integer;
+
+function maximum(A : integer; B : integer)
+return integer;
+
+function ld(X : natural)
+return natural;
+
+function sign(X : integer)
+return integer;
+
+end vhdl_2008_workaround_pkg;
+
+ package body vhdl_2008_workaround_pkg is
+
+function minimum(A : integer; B : integer)
+return integer is
+ variable tmp : integer;
+ begin
+ if(A < B) then
+ tmp := A;
+ else
+ tmp := B;
+ end if;
+ return tmp;
+end function minimum;
+
+function maximum(A : integer; B : integer)
+return integer is
+ variable tmp : integer;
+ begin
+ if(A > B) then
+ tmp := A;
+ else
+ tmp := B;
+ end if;
+
+ return tmp;
+end function maximum;
+
+function ld(X : natural)
+return natural is
+ variable tmp : natural := 32;
+ variable search : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(X, 32));
+ variable found : std_logic := '0';
+ begin
+ if(X = 0) then
+ tmp := 1;
+ else
+ while(tmp > 0 AND found = '0') loop
+ if(found = '0') then
+ tmp := tmp -1;
+ end if;
+ found := search(tmp);
+
+ end loop;
+ end if;
+ return tmp;
+end function ld;
+
+function sign(X : integer)
+return integer is
+ variable tmp : integer := 0;
+ begin
+ if(X = 0) then
+ tmp := 0;
+ elsif(X > 0) then
+ tmp := 1;
+ else
+ tmp := -1;
+ end if;
+ return tmp;
+end function sign;
+
+
+
+end package body;
diff --git a/hdl/eb_testbench/wave.do b/hdl/eb_testbench/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..8db3742908f19d62d55ae24866ce9f79c6e241ac
--- /dev/null
+++ b/hdl/eb_testbench/wave.do
@@ -0,0 +1,55 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/g_class_mask
+add wave -noupdate /main/DUT/g_our_ethertype
+add wave -noupdate /main/DUT/clk_sys_i
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/snk_cyc_i
+add wave -noupdate /main/DUT/snk_stb_i
+add wave -noupdate /main/DUT/snk_sel_i
+add wave -noupdate /main/DUT/snk_adr_i
+add wave -noupdate /main/DUT/snk_dat_i
+add wave -noupdate /main/DUT/snk_we_i
+add wave -noupdate /main/DUT/snk_stall_o
+add wave -noupdate /main/DUT/snk_ack_o
+add wave -noupdate /main/DUT/snk_err_o
+add wave -noupdate /main/DUT/src_cyc_o
+add wave -noupdate /main/DUT/src_stb_o
+add wave -noupdate /main/DUT/src_dat_o
+add wave -noupdate /main/DUT/src_adr_o
+add wave -noupdate /main/DUT/src_we_o
+add wave -noupdate /main/DUT/src_ack_i
+add wave -noupdate /main/DUT/src_err_i
+add wave -noupdate /main/DUT/src_sel_o
+add wave -noupdate /main/DUT/src_stall_i
+add wave -noupdate /main/DUT/master_cyc_o
+add wave -noupdate /main/DUT/master_we_o
+add wave -noupdate /main/DUT/master_stb_o
+add wave -noupdate /main/DUT/master_sel_o
+add wave -noupdate /main/DUT/master_adr_o
+add wave -noupdate /main/DUT/master_dat_o
+add wave -noupdate /main/DUT/master_dat_i
+add wave -noupdate /main/DUT/master_ack_i
+add wave -noupdate /main/DUT/src_out
+add wave -noupdate /main/DUT/src_in
+add wave -noupdate /main/DUT/snk_out
+add wave -noupdate /main/DUT/snk_in
+add wave -noupdate /main/DUT/master_out
+add wave -noupdate /main/DUT/master_in
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {67408050000 fs} 0}
+configure wave -namecolwidth 183
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {125312500 ps} {256562500 ps}
diff --git a/hdl/eb_testbench/wb_binary_file_source.svh b/hdl/eb_testbench/wb_binary_file_source.svh
new file mode 100644
index 0000000000000000000000000000000000000000..c0dff36f736eebfed70938aca25d44b219df50c7
--- /dev/null
+++ b/hdl/eb_testbench/wb_binary_file_source.svh
@@ -0,0 +1,94 @@
+`ifndef __WB_PACKET_SOURCE_SVH
+ `define __WB_PACKET_SOURCE_SVH
+
+`include "simdrv_defs.svh"
+`include "eth_packet.svh"
+`include "if_wishbone_accessor.svh"
+
+`include "wb_fabric_defs.svh"
+
+virtual class EthPacketSource;
+ static int _null = 0;
+
+ pure virtual task send(ref EthPacket pkt, ref int result = _null);
+endclass // PacketSource
+
+
+class WBPacketSource extends EthPacketSource;
+ protected CWishboneAccessor m_acc;
+
+ function new(CWishboneAccessor acc);
+ m_acc = acc;
+ endfunction // new
+
+
+
+
+ task send(ref EthPacket pkt, ref int result = _null);
+
+`define EOF 16'HFFFF
+`define MEM_SIZE 750
+
+
+
+reg [15:0] pdata[0:`MEM_SIZE];
+reg [80*8:1] file_name;
+int r, i, j, len, file;
+ wb_cycle_t cyc;
+ wb_xfer_t xf;
+
+ file_name = "test_V4.pcap";
+ file = $fopen(file_name, "rb");
+ i = $fgetc(file);
+ $display("test char %0d \n", i);
+
+ i = $fseek(file, 40, 0);
+ i = $ftell(file);
+ $display("ftell %0d\n", i);
+ len = $fread(pdata[0], file);
+ $display("Loaded %0d entries \n", len);
+ i = $fcloser(file);
+
+
+
+
+ cyc.ctype = PIPELINED;
+ cyc.rw = 1;
+
+
+
+
+ j = 0;
+ for(i=0; j < len; i++)
+ begin
+ xf.a = WRF_DATA;
+ if(i==len-1 && (len&1))
+ begin
+ xf.size = 1;
+ xf.d = pdata[i] >> 8;
+ end else begin
+ xf.size = 2;
+ xf.d = pdata[i];
+ end
+ j += xf.size;
+ cyc.data.push_back(xf);
+
+ end
+
+
+ m_acc.put(cyc);
+ m_acc.get(cyc);
+
+ result = cyc.result;
+
+ endtask // send
+
+
+
+
+
+endclass // WBPacketSource
+
+
+
+`endif
diff --git a/hdl/eb_testbench/wb_binary_file_source.svh.bak b/hdl/eb_testbench/wb_binary_file_source.svh.bak
new file mode 100644
index 0000000000000000000000000000000000000000..43f5fe287f3b53073f593894adce500f58d4d4b6
--- /dev/null
+++ b/hdl/eb_testbench/wb_binary_file_source.svh.bak
@@ -0,0 +1,94 @@
+`ifndef __WB_PACKET_SOURCE_SVH
+ `define __WB_PACKET_SOURCE_SVH
+
+`include "simdrv_defs.svh"
+`include "eth_packet.svh"
+`include "if_wishbone_accessor.svh"
+
+`include "wb_fabric_defs.svh"
+
+virtual class EthPacketSource;
+ static int _null = 0;
+
+ pure virtual task send(ref EthPacket pkt, ref int result = _null);
+endclass // PacketSource
+
+
+class WBPacketSource extends EthPacketSource;
+ protected CWishboneAccessor m_acc;
+
+ function new(CWishboneAccessor acc);
+ m_acc = acc;
+ endfunction // new
+
+
+
+
+ task send(ref EthPacket pkt, ref int result = _null);
+
+`define EOF 16'HFFFF
+`define MEM_SIZE 750
+
+
+
+reg [15:0] pdata[0:`MEM_SIZE];
+reg [80*8:1] file_name;
+int r, i, len, file;
+ wb_cycle_t cyc;
+ wb_xfer_t xf;
+
+ file_name = "test_V4.pcap";
+ file = $fopen(file_name, "rb");
+ i = $fgetc(file);
+ $display("test char %0d \n", i);
+
+ i = $fseek(file, 40, 0);
+ i = $ftell(file);
+ $display("ftell %0d\n", i);
+ len = $fread(pdata[0], file);
+ $display("Loaded %0d entries \n", len);
+ i = $fcloser(file);
+
+
+
+
+ cyc.ctype = PIPELINED;
+ cyc.rw = 1;
+
+
+
+
+
+ for(i=0; i < len; i += 0)
+ begin
+ xf.a = WRF_DATA;
+ if(i==len-1 && (len&1))
+ begin
+ xf.size = 1;
+ xf.d = pdata[i] >> 8;
+ end else begin
+ xf.size = 2;
+ xf.d = pdata[i];
+ end
+ i += xf.size;
+ cyc.data.push_back(xf);
+
+ end
+
+
+ m_acc.put(cyc);
+ m_acc.get(cyc);
+
+ result = cyc.result;
+
+ endtask // send
+
+
+
+
+
+endclass // WBPacketSource
+
+
+
+`endif
diff --git a/hdl/eb_testbench/wb_fabric_defs.svh b/hdl/eb_testbench/wb_fabric_defs.svh
new file mode 100644
index 0000000000000000000000000000000000000000..907d97e349ba28ec18bc2ab3f293d646d235e613
--- /dev/null
+++ b/hdl/eb_testbench/wb_fabric_defs.svh
@@ -0,0 +1,13 @@
+`ifndef __WB_FABRIC_DEFS_SVH
+ `define __WB_FABRIC_DEFS_SVH
+
+const bit [2:0] WRF_STATUS = 3'b100;
+const bit [2:0] WRF_DATA = 3'b000;
+const bit [2:0] WRF_OOB = 3'b010;
+const bit [2:0] WRF_USER = 3'b110;
+
+const bit [3:0] WRF_OOB_TX_FID = 4'b0001;
+const bit [3:0] WRF_OOB_RX_TIMESTAMP = 4'b0000;
+
+`endif // `ifndef __WB_FABRIC_DEFS_SVH
+
diff --git a/hdl/eb_testbench/wb_packet_sink.svh b/hdl/eb_testbench/wb_packet_sink.svh
new file mode 100644
index 0000000000000000000000000000000000000000..7107c060f98090ea6fdba08712a507bb2e98a9a7
--- /dev/null
+++ b/hdl/eb_testbench/wb_packet_sink.svh
@@ -0,0 +1,130 @@
+`ifndef __WB_PACKET_SINK_SVH
+ `define __WB_PACKET_SINK_SVH
+
+`include "simdrv_defs.svh"
+`include "eth_packet.svh"
+`include "if_wishbone_accessor.svh"
+
+`include "wb_fabric_defs.svh"
+
+virtual class EthPacketSink;
+
+ static int _null = 0;
+
+ pure virtual function int poll();
+ pure virtual task recv(ref EthPacket pkt, ref int result = _null);
+
+ endclass // EthPacketSink
+
+
+class WBPacketSink extends EthPacketSink;
+ protected CWishboneAccessor m_acc;
+
+
+ function new(CWishboneAccessor acc);
+ m_acc = acc;
+ endfunction // new
+
+ function int poll();
+ return m_acc.poll();
+ endfunction // poll
+
+ protected task decode_status(uint64_t stat, ref EthPacket pkt);
+ if(stat & 'h2)
+ pkt.error = 1'b1;
+ else begin
+ pkt.has_smac = (stat & 'h4 ? 1'b1 : 1'b0);
+ pkt.has_crc = (stat & 'h8 ? 1'b1 : 1'b0);
+ pkt.pclass = (stat>>8) & 'hff;
+
+ end
+ endtask // decode_status
+
+ protected task decode_oob(uint64_t oob, int size, ref EthPacket pkt);
+ if(!size)
+ return;
+ else if(size == 2 && (oob >> 28) == WRF_OOB_TX_FID)
+ begin
+ // $display("GotTxOOB");
+ pkt.oob_type = TX_FID;
+ pkt.ts.frame_id = oob & 'hffff;
+ end
+ else if (size == 3 && (oob >> 46) == WRF_OOB_RX_TIMESTAMP)
+ begin
+ $display("GotRXOOB");
+
+ end else begin
+ $error("Invalid OOB!");
+ $stop;
+ end
+
+
+ endtask // decode_oob
+
+
+ task recv(ref EthPacket pkt, ref int result = _null);
+ uint64_t oob = 0;
+ byte tmp[];
+ wb_cycle_t cyc;
+ int i, size = 0, n = 0, n_oob = 0;
+ int oob_size = 0;
+
+
+
+ pkt = new;
+ m_acc.get(cyc);
+
+
+ for(i=0;i<cyc.data.size(); i++)
+ if (cyc.data[i].a == WRF_DATA)
+ size = size + cyc.data[i].size;
+
+ tmp = new[size];
+
+// $display("CDS %d size: %d\n", cyc.data.size(), size);
+
+
+ for(i=0;i<cyc.data.size(); i++)
+ begin
+ wb_xfer_t xf = cyc.data[i];
+
+ case(xf.a)
+ WRF_STATUS:
+ begin
+ decode_status(xf.d, pkt);
+ if(pkt.error)
+ break;
+ end
+
+ WRF_DATA:
+ begin
+ if(xf.size == 1)
+ tmp[n++] = (xf.d & 'hff);
+ else if(xf.size == 2)begin
+ tmp[n++] = ((xf.d >> 8) & 'hff);
+ tmp[n++] = (xf.d & 'hff);
+ end
+ end
+
+ WRF_OOB:
+ begin
+ oob = (oob << 16) | xf.d;
+ oob_size ++;
+ end
+
+ endcase // case (xf.a)
+ end
+ pkt.deserialize(tmp);
+ decode_oob(oob, oob_size, pkt);
+
+
+
+endtask // recv
+
+
+
+endclass // WBPacketSink
+
+
+
+`endif
diff --git a/hdl/eb_testbench/wb_packet_source.svh b/hdl/eb_testbench/wb_packet_source.svh
new file mode 100644
index 0000000000000000000000000000000000000000..066f2c24ab26fdc3a7d41aec80bee454ad1dd306
--- /dev/null
+++ b/hdl/eb_testbench/wb_packet_source.svh
@@ -0,0 +1,141 @@
+`ifndef __WB_PACKET_SOURCE_SVH
+ `define __WB_PACKET_SOURCE_SVH
+
+`include "simdrv_defs.svh"
+`include "eth_packet.svh"
+`include "if_wishbone_accessor.svh"
+
+`include "wb_fabric_defs.svh"
+
+virtual class EthPacketSource;
+ static int _null = 0;
+
+ pure virtual task send(ref EthPacket pkt, ref int result = _null);
+endclass // PacketSource
+
+
+class WBPacketSource extends EthPacketSource;
+ protected CWishboneAccessor m_acc;
+
+ function new(CWishboneAccessor acc);
+ m_acc = acc;
+ endfunction // new
+
+ function bit[15:0] pack_status(ref EthPacket pkt, input bit error = 0);
+ bit [15:0] st;
+ st[0] = (pkt.is_hp ? 1'b1: 1'b0);
+ st[1] = 1'b0;
+ st[2] = (pkt.has_smac ? 1'b1: 1'b0);
+ st[3] = error;
+ st[15:8] = pkt.pclass; // FIXME: add packet classes
+ st[7:4]= 0;
+
+ return st;
+ endfunction // pack_status
+
+ task unpack_status(bit[15:0] status, ref EthPacket pkt);
+
+ endtask // unpack_status
+
+ typedef bit[15:0] oob_array16[];
+
+ function u64_array_t pack_oob(ref EthPacket pkt);
+ u64_array_t oob;
+
+ case(pkt.oob_type)
+ TX_FID: begin
+ oob = new[2];
+ oob[0] = {WRF_OOB_TX_FID, 12'b0};
+ oob[1] = pkt.ts.frame_id;
+ end
+ endcase // case (pkt.oob_type)
+ return oob;
+
+ endfunction // pack_oob
+
+
+ task send(ref EthPacket pkt, ref int result = _null);
+ byte pdata[]; // FIXME: dynamic allocation would be better...
+ u64_array_t pdata_p;
+ u64_array_t oob_p;
+
+ int i, len;
+
+ wb_cycle_t cyc;
+ wb_xfer_t xf;
+
+ cyc.ctype = PIPELINED;
+ cyc.rw = 1;
+
+
+ /* First, the status register */
+
+ xf.a = WRF_STATUS;
+ xf.d = pack_status(pkt);
+ xf.size = 2;
+
+ cyc.data.push_back(xf);
+
+ pkt.serialize(pdata);
+
+ pdata_p = SimUtils.pack(pdata, 2, 1);
+ len = pdata_p.size();
+
+ for(i=0; i < len; i++)
+ begin
+ xf.a = WRF_DATA;
+ if(i==len-1 && (pdata.size()&1))
+ begin
+ xf.size = 1;
+ xf.d = pdata_p[i] >> 8;
+ end else begin
+ xf.size = 2;
+ xf.d = pdata_p[i];
+ end
+
+ cyc.data.push_back(xf);
+
+ end
+
+ if(pkt.error)
+ begin
+
+ xf.a = WRF_STATUS;
+ xf.d = pack_status(pkt, 1);
+ xf.size = 2;
+ cyc.data.push_back(xf);
+
+
+ end else begin
+
+// $display("WBPacketSource::send(): DataSize: %d\n", cyc.data.size());
+
+ oob_p = pack_oob(pkt);
+
+ for (i=0;i<oob_p.size(); i++)
+ begin
+ xf.a = WRF_OOB;
+ xf.d = oob_p[i] & 'hffff;
+ xf.size = 2;
+ cyc.data.push_back(xf);
+
+ end
+ end // else: !if(pkt.error)
+
+ m_acc.put(cyc);
+ m_acc.get(cyc);
+
+ result = cyc.result;
+
+ endtask // send
+
+
+
+
+
+
+endclass // WBPacketSource
+
+
+
+`endif
diff --git a/hdl/eb_testbench/wishbone_package16.vhd b/hdl/eb_testbench/wishbone_package16.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2893fc1db24e604d4874fef5e7b9cd6fa3bfad4c
--- /dev/null
+++ b/hdl/eb_testbench/wishbone_package16.vhd
@@ -0,0 +1,109 @@
+--! @file wishbone_package16.vhd
+--! @brief 16b wide WB records
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wb16_package is
+
+ constant wishbone_address_width : integer := 32;
+ constant wishbone_data_width : integer := 16;
+
+ subtype wishbone_address is
+ std_logic_vector(wishbone_address_width-1 downto 0);
+ subtype wishbone_data is
+ std_logic_vector(wishbone_data_width-1 downto 0);
+ subtype wishbone_byte_select is
+ std_logic_vector((wishbone_data_width/8)-1 downto 0);
+ subtype wishbone_cycle_type is
+ std_logic_vector(2 downto 0);
+ subtype wishbone_burst_type is
+ std_logic_vector(1 downto 0);
+
+ -- A B.4 Wishbone pipelined master
+ -- Pipelined wishbone is always LOCKed during CYC (else ACKs would get lost)
+ type wb16_master_out is record
+ CYC : std_logic;
+ STB : std_logic;
+ ADR : wishbone_address;
+ SEL : wishbone_byte_select;
+ WE : std_logic;
+ DAT : wishbone_data;
+ end record wb16_master_out;
+ subtype wb16_slave_in is wb16_master_out;
+
+ type wb16_slave_out is record
+ ACK : std_logic;
+ ERR : std_logic;
+ RTY : std_logic;
+ STALL : std_logic;
+ DAT : wishbone_data;
+ end record wb16_slave_out;
+ subtype wb16_master_in is wb16_slave_out;
+
+ type wishbone_v3_master_out is record
+ CYC : std_logic;
+ STB : std_logic;
+ ADR : wishbone_address;
+ SEL : wishbone_byte_select;
+ WE : std_logic;
+ LOCK : std_logic;
+ DAT : wishbone_data;
+ CTI : wishbone_cycle_type;
+ BTE : wishbone_burst_type;
+ end record wishbone_v3_master_out;
+ subtype wishbone_v3_slave_in is wishbone_v3_master_out;
+
+ type wishbone_v3_slave_out is record
+ ACK : std_logic;
+ ERR : std_logic;
+ RTY : std_logic;
+ DAT : wishbone_data;
+ end record wishbone_v3_slave_out;
+ subtype wishbone_v3_master_in is wishbone_v3_slave_out;
+
+ type wb16_master_out_vector is array (natural range <>) of wb16_master_out;
+ type wb16_slave_out_vector is array (natural range <>) of wb16_slave_out;
+ subtype wb16_slave_in_vector is wb16_master_out_vector;
+ subtype wb16_master_in_vector is wb16_slave_out_vector;
+
+ type wishbone_v3_master_out_vector is array (natural range <>) of wishbone_v3_master_out;
+ type wishbone_v3_slave_out_vector is array (natural range <>) of wishbone_v3_slave_out;
+ subtype wishbone_v3_slave_in_vector is wishbone_v3_master_out_vector;
+ subtype wishbone_v3_master_in_vector is wishbone_v3_slave_out_vector;
+
+ type wishbone_address_vector is array (natural range <>) of wishbone_address;
+ type wishbone_data_vector is array (natural range <>) of wishbone_data;
+
+
+
+
+ end wb16_package;
+
+ package body wb16_package is
+ end package body;
diff --git a/hdl/eb_testbench/wishbone_package32.vhd b/hdl/eb_testbench/wishbone_package32.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b7050888ab36203530e5ed0c9e638844da55a362
--- /dev/null
+++ b/hdl/eb_testbench/wishbone_package32.vhd
@@ -0,0 +1,219 @@
+--! @file wishbone_package32.vhd
+--! @brief 32b wide WB records
+--!
+--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
+--!
+--! Important details about its implementation
+--! should go in these comments.
+--!
+--! @author Mathias Kreider <m.kreider@gsi.de>
+--!
+--! @bug No know bugs.
+--!
+--------------------------------------------------------------------------------
+--! This library is free software; you can redistribute it and/or
+--! modify it under the terms of the GNU Lesser General Public
+--! License as published by the Free Software Foundation; either
+--! version 3 of the License, or (at your option) any later version.
+--!
+--! This library is distributed in the hope that it will be useful,
+--! but WITHOUT ANY WARRANTY; without even the implied warranty of
+--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+--! Lesser General Public License for more details.
+--!
+--! You should have received a copy of the GNU Lesser General Public
+--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wb32_package is
+
+ constant wishbone_address_width : integer := 32;
+ constant wishbone_data_width : integer := 32;
+
+ subtype wishbone_address is
+ std_logic_vector(wishbone_address_width-1 downto 0);
+ subtype wishbone_data is
+ std_logic_vector(wishbone_data_width-1 downto 0);
+ subtype wishbone_byte_select is
+ std_logic_vector((wishbone_address_width/8)-1 downto 0);
+ subtype wishbone_cycle_type is
+ std_logic_vector(2 downto 0);
+ subtype wishbone_burst_type is
+ std_logic_vector(1 downto 0);
+
+ -- A B.4 Wishbone pipelined master
+ -- Pipelined wishbone is always LOCKed during CYC (else ACKs would get lost)
+ type wb32_master_out is record
+ CYC : std_logic;
+ STB : std_logic;
+ ADR : wishbone_address;
+ SEL : wishbone_byte_select;
+ WE : std_logic;
+ DAT : wishbone_data;
+ end record wb32_master_out;
+ subtype wb32_slave_in is wb32_master_out;
+
+ type wb32_slave_out is record
+ ACK : std_logic;
+ ERR : std_logic;
+ RTY : std_logic;
+ STALL : std_logic;
+ DAT : wishbone_data;
+ end record wb32_slave_out;
+ subtype wb32_master_in is wb32_slave_out;
+
+ type wishbone_v3_master_out is record
+ CYC : std_logic;
+ STB : std_logic;
+ ADR : wishbone_address;
+ SEL : wishbone_byte_select;
+ WE : std_logic;
+ LOCK : std_logic;
+ DAT : wishbone_data;
+ CTI : wishbone_cycle_type;
+ BTE : wishbone_burst_type;
+ end record wishbone_v3_master_out;
+ subtype wishbone_v3_slave_in is wishbone_v3_master_out;
+
+ type wishbone_v3_slave_out is record
+ ACK : std_logic;
+ ERR : std_logic;
+ RTY : std_logic;
+ DAT : wishbone_data;
+ end record wishbone_v3_slave_out;
+ subtype wishbone_v3_master_in is wishbone_v3_slave_out;
+
+ type wb32_master_out_vector is array (natural range <>) of wb32_master_out;
+ type wb32_slave_out_vector is array (natural range <>) of wb32_slave_out;
+ subtype wb32_slave_in_vector is wb32_master_out_vector;
+ subtype wb32_master_in_vector is wb32_slave_out_vector;
+
+ type wishbone_v3_master_out_vector is array (natural range <>) of wishbone_v3_master_out;
+ type wishbone_v3_slave_out_vector is array (natural range <>) of wishbone_v3_slave_out;
+ subtype wishbone_v3_slave_in_vector is wishbone_v3_master_out_vector;
+ subtype wishbone_v3_master_in_vector is wishbone_v3_slave_out_vector;
+
+ type wishbone_address_vector is array (natural range <>) of wishbone_address;
+ type wishbone_data_vector is array (natural range <>) of wishbone_data;
+
+ function TO_STD_LOGIC_VECTOR(X : wb32_slave_out)
+return std_logic_vector;
+
+function TO_wb32_slave_out(X : std_logic_vector)
+return wb32_slave_out;
+
+ function TO_STD_LOGIC_VECTOR(X : wb32_master_out)
+return std_logic_vector;
+
+function TO_wb32_master_out(X : std_logic_vector)
+return wb32_master_out;
+
+
+
+ -- function TO_STD_LOGIC_VECTOR(X : wb32_master_in)
+-- return std_logic_vector;
+
+function TO_wb32_master_in(X : std_logic_vector)
+return wb32_master_in;
+
+ -- function TO_STD_LOGIC_VECTOR(X : wb32_slave_in)
+-- return std_logic_vector;
+
+function TO_wb32_slave_in(X : std_logic_vector)
+return wb32_slave_in;
+
+ end wb32_package;
+
+ package body wb32_package is
+
+ function TO_STD_LOGIC_VECTOR(X : wb32_slave_out)
+return std_logic_vector is
+ variable tmp : std_logic_vector(35 downto 0) := (others => '0');
+ begin
+ tmp := X.ACK & X.ERR & X.RTY & X.STALL & X.DAT;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function TO_wb32_slave_out(X : std_logic_vector)
+return wb32_slave_out is
+ variable tmp : wb32_slave_out;
+ begin
+ tmp.ACK := X(35);
+ tmp.ERR := X(34);
+ tmp.RTY := X(33);
+ tmp.STALL := X(32);
+ tmp.DAT := X(31 downto 0);
+
+ return tmp;
+end function TO_wb32_slave_out;
+
+
+ function TO_STD_LOGIC_VECTOR(X : wb32_master_out)
+return std_logic_vector is
+ variable tmp : std_logic_vector(70 downto 0) := (others => '0');
+ begin
+ tmp := X.CYC & X.STB & X.ADR & X.SEL & X.WE & X.DAT;
+ return tmp;
+end function TO_STD_LOGIC_VECTOR;
+
+function TO_wb32_master_out(X : std_logic_vector)
+return wb32_master_out is
+ variable tmp : wb32_master_out;
+ begin
+ tmp.CYC := X(70);
+ tmp.STB := X(69);
+ tmp.ADR := X(68 downto 37);
+ tmp.SEL := X(36 downto 33);
+ tmp.WE := X(32);
+ tmp.DAT := X(31 downto 0);
+ return tmp;
+end function TO_wb32_master_out;
+
+ -- function TO_STD_LOGIC_VECTOR(X : wb32_master_in)
+-- return std_logic_vector is
+ -- variable tmp : std_logic_vector(35 downto 0) := (others => '0');
+ -- begin
+ -- tmp := X.ACK & X.ERR & X.RTY & X.STALL & X.DAT;
+ -- return tmp;
+-- end function TO_STD_LOGIC_VECTOR;
+
+function TO_wb32_master_in(X : std_logic_vector)
+return wb32_master_in is
+ variable tmp : wb32_master_in;
+ begin
+ tmp.ACK := X(35);
+ tmp.ERR := X(34);
+ tmp.RTY := X(33);
+ tmp.STALL := X(32);
+ tmp.DAT := X(31 downto 0);
+
+ return tmp;
+end function TO_wb32_master_in;
+
+
+ -- function TO_STD_LOGIC_VECTOR(X : wb32_slave_in)
+-- return std_logic_vector is
+ -- variable tmp : std_logic_vector(70 downto 0) := (others => '0');
+ -- begin
+ -- tmp := X.CYC & X.STB & X.ADR & X.SEL & X.WE & X.DAT;
+ -- return tmp;
+-- end function TO_STD_LOGIC_VECTOR;
+
+function TO_wb32_slave_in(X : std_logic_vector)
+return wb32_slave_in is
+ variable tmp : wb32_slave_in;
+ begin
+ tmp.CYC := X(70);
+ tmp.STB := X(69);
+ tmp.ADR := X(68 downto 37);
+ tmp.SEL := X(36 downto 33);
+ tmp.WE := X(32);
+ tmp.DAT := X(31 downto 0);
+ return tmp;
+end function TO_wb32_slave_in;
+
+end package body;
diff --git a/hdl/eb_testbench/wishbone_pkg.vhd b/hdl/eb_testbench/wishbone_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8985a1ef49dc8ae4c7b5854019abf15b99c64194
--- /dev/null
+++ b/hdl/eb_testbench/wishbone_pkg.vhd
@@ -0,0 +1,497 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+package wishbone_pkg is
+
+ constant c_wishbone_address_width : integer := 32;
+ constant c_wishbone_data_width : integer := 32;
+
+ subtype t_wishbone_address is
+ std_logic_vector(c_wishbone_address_width-1 downto 0);
+ subtype t_wishbone_data is
+ std_logic_vector(c_wishbone_data_width-1 downto 0);
+ subtype t_wishbone_byte_select is
+ std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
+ subtype t_wishbone_cycle_type is
+ std_logic_vector(2 downto 0);
+ subtype t_wishbone_burst_type is
+ std_logic_vector(1 downto 0);
+
+ type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
+ type t_wishbone_address_granularity is (BYTE, WORD);
+
+ type t_wishbone_master_out is record
+ cyc : std_logic;
+ stb : std_logic;
+ adr : t_wishbone_address;
+ sel : t_wishbone_byte_select;
+ we : std_logic;
+ dat : t_wishbone_data;
+ end record t_wishbone_master_out;
+
+ subtype t_wishbone_slave_in is t_wishbone_master_out;
+
+ type t_wishbone_slave_out is record
+ ack : std_logic;
+ err : std_logic;
+ rty : std_logic;
+ stall : std_logic;
+ int : std_logic;
+ dat : t_wishbone_data;
+ end record t_wishbone_slave_out;
+ subtype t_wishbone_master_in is t_wishbone_slave_out;
+
+ subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
+
+
+
+ type t_wishbone_address_array is array(integer range <>) of t_wishbone_address;
+ type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
+ type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
+ type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
+ type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
+
+
+ constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0):=
+ (others => 'X');
+ constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
+ (others => 'X');
+ constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
+ (others => 'X');
+ constant cc_dummy_slave_in : t_wishbone_slave_in :=
+ ('X', 'X', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
+ constant cc_dummy_slave_out : t_wishbone_slave_out :=
+ ('X', 'X', 'X', 'X', 'X', cc_dummy_data);
+
+
+------------------------------------------------------------------------------
+-- Components declaration
+-------------------------------------------------------------------------------
+
+ component wb_slave_adapter
+ generic (
+ g_master_use_struct : boolean;
+ g_master_mode : t_wishbone_interface_mode;
+ g_master_granularity : t_wishbone_address_granularity;
+ g_slave_use_struct : boolean;
+ g_slave_mode : t_wishbone_interface_mode;
+ g_slave_granularity : t_wishbone_address_granularity);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
+ sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
+ sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
+ sl_cyc_i : in std_logic := '0';
+ sl_stb_i : in std_logic := '0';
+ sl_we_i : in std_logic := '0';
+ sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ sl_err_o : out std_logic;
+ sl_rty_o : out std_logic;
+ sl_ack_o : out std_logic;
+ sl_stall_o : out std_logic;
+ sl_int_o : out std_logic;
+ slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+ ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ ma_cyc_o : out std_logic;
+ ma_stb_o : out std_logic;
+ ma_we_o : out std_logic;
+ ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
+ ma_err_i : in std_logic := '0';
+ ma_rty_i : in std_logic := '0';
+ ma_ack_i : in std_logic := '0';
+ ma_stall_i : in std_logic := '0';
+ ma_int_i : in std_logic := '0';
+ master_i : in t_wishbone_master_in := cc_dummy_slave_out;
+ master_o : out t_wishbone_master_out);
+ end component;
+
+ component wb_async_bridge
+ generic (
+ g_simulation : integer;
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_cpu_address_width : integer);
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ cpu_cs_n_i : in std_logic;
+ cpu_wr_n_i : in std_logic;
+ cpu_rd_n_i : in std_logic;
+ cpu_bs_n_i : in std_logic_vector(3 downto 0);
+ cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
+ cpu_data_b : inout std_logic_vector(31 downto 0);
+ cpu_nwait_o : out std_logic;
+ wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_stb_o : out std_logic;
+ wb_we_o : out std_logic;
+ wb_sel_o : out std_logic_vector(3 downto 0);
+ wb_cyc_o : out std_logic;
+ wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
+ wb_ack_i : in std_logic;
+ wb_stall_i : in std_logic := '0');
+ end component;
+
+ component xwb_async_bridge
+ generic (
+ g_simulation : integer;
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_cpu_address_width : integer);
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ cpu_cs_n_i : in std_logic;
+ cpu_wr_n_i : in std_logic;
+ cpu_rd_n_i : in std_logic;
+ cpu_bs_n_i : in std_logic_vector(3 downto 0);
+ cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
+ cpu_data_b : inout std_logic_vector(31 downto 0);
+ cpu_nwait_o : out std_logic;
+ master_o : out t_wishbone_master_out;
+ master_i : in t_wishbone_master_in);
+ end component;
+
+ component xwb_bus_fanout
+ generic (
+ g_num_outputs : natural;
+ g_bits_per_slave : integer;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
+ master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
+ end component;
+
+ component xwb_crossbar
+ generic (
+ g_num_masters : integer;
+ g_num_slaves : integer;
+ g_registered : boolean);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
+ slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+ master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
+ master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
+ cfg_address_i : in t_wishbone_address_array(g_num_slaves-1 downto 0);
+ cfg_mask_i : in t_wishbone_address_array(g_num_slaves-1 downto 0));
+ end component;
+
+ component xwb_dpram
+ generic (
+ g_size : natural;
+ g_init_file : string := "";
+ g_must_have_init_file : boolean := true;
+ g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_slave1_granularity : t_wishbone_address_granularity := WORD;
+ g_slave2_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave1_i : in t_wishbone_slave_in;
+ slave1_o : out t_wishbone_slave_out;
+ slave2_i : in t_wishbone_slave_in;
+ slave2_o : out t_wishbone_slave_out);
+ end component;
+
+ component wb_gpio_port
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_num_pins : natural range 1 to 256;
+ g_with_builtin_tristates : boolean := false);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_adr_i : in std_logic_vector(7 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
+ gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
+ gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
+ gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
+ end component;
+
+ component xwb_gpio_port
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_num_pins : natural range 1 to 256;
+ g_with_builtin_tristates : boolean);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
+ gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
+ gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
+ gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
+ end component;
+
+ component wb_i2c_master
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_adr_i : in std_logic_vector(4 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_cyc_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_int_o : out std_logic;
+ wb_stall_o : out std_logic;
+ scl_pad_i : in std_logic;
+ scl_pad_o : out std_logic;
+ scl_padoen_o : out std_logic;
+ sda_pad_i : in std_logic;
+ sda_pad_o : out std_logic;
+ sda_padoen_o : out std_logic);
+ end component;
+
+ component xwb_i2c_master
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ scl_pad_i : in std_logic;
+ scl_pad_o : out std_logic;
+ scl_padoen_o : out std_logic;
+ sda_pad_i : in std_logic;
+ sda_pad_o : out std_logic;
+ sda_padoen_o : out std_logic);
+ end component;
+
+ component xwb_lm32
+ generic (
+ g_profile : string);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ irq_i : in std_logic_vector(31 downto 0);
+ dwb_o : out t_wishbone_master_out;
+ dwb_i : in t_wishbone_master_in;
+ iwb_o : out t_wishbone_master_out;
+ iwb_i : in t_wishbone_master_in);
+ end component;
+
+ component wb_onewire_master
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_num_ports : integer;
+ g_ow_btp_normal : string := "1.0";
+ g_ow_btp_overdrive : string := "5.0");
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_adr_i : in std_logic_vector(2 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_ack_o : out std_logic;
+ wb_int_o : out std_logic;
+ wb_stall_o : out std_logic;
+ owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_i : in std_logic_vector(g_num_ports -1 downto 0));
+ end component;
+
+ component xwb_onewire_master
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_num_ports : integer;
+ g_ow_btp_normal : string := "5.0";
+ g_ow_btp_overdrive : string := "1.0");
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_i : in std_logic_vector(g_num_ports -1 downto 0));
+ end component;
+
+ component wb_spi
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_adr_i : in std_logic_vector(4 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_cyc_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_err_o : out std_logic;
+ wb_int_o : out std_logic;
+ wb_stall_o : out std_logic;
+ pad_cs_o : out std_logic_vector(7 downto 0);
+ pad_sclk_o : out std_logic;
+ pad_mosi_o : out std_logic;
+ pad_miso_i : in std_logic);
+ end component;
+
+ component xwb_spi
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ pad_cs_o : out std_logic_vector(7 downto 0);
+ pad_sclk_o : out std_logic;
+ pad_mosi_o : out std_logic;
+ pad_miso_i : in std_logic);
+ end component;
+
+ component wb_simple_uart
+ generic (
+ g_with_virtual_uart : boolean := false;
+ g_with_physical_uart : boolean := true;
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_adr_i : in std_logic_vector(4 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ uart_rxd_i : in std_logic := '1';
+ uart_txd_o : out std_logic);
+ end component;
+
+ component xwb_simple_uart
+ generic (
+ g_with_virtual_uart : boolean := false;
+ g_with_physical_uart : boolean := true;
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ uart_rxd_i : in std_logic := '1';
+ uart_txd_o : out std_logic);
+ end component;
+
+ component wb_tics
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_period : integer);
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic);
+ end component;
+
+ component xwb_tics
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_period : integer);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor);
+ end component;
+
+ component wb_vic
+ generic (
+ g_interface_mode : t_wishbone_interface_mode;
+ g_address_granularity : t_wishbone_address_granularity;
+ g_num_interrupts : natural);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
+ irq_master_o : out std_logic);
+ end component;
+
+ component xwb_vic
+ generic (
+ g_interface_mode : t_wishbone_interface_mode;
+ g_address_granularity : t_wishbone_address_granularity;
+ g_num_interrupts : natural);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
+ irq_master_o : out std_logic);
+ end component;
+end wishbone_pkg;
diff --git a/hdl/eb_testbench/wr_fabric_pkg.vhd b/hdl/eb_testbench/wr_fabric_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8b355246a3ddaaf04cb16eb0698cda63539701ed
--- /dev/null
+++ b/hdl/eb_testbench/wr_fabric_pkg.vhd
@@ -0,0 +1,92 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+package wr_fabric_pkg is
+
+ constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
+ constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
+ constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
+ constant c_WRF_USER : std_logic_vector(1 downto 0) := "11";
+
+ constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
+ constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
+
+ type t_wrf_status_reg is record
+ is_hp : std_logic;
+ has_smac : std_logic;
+ has_crc : std_logic;
+ error : std_logic;
+ tag_me : std_logic;
+ match_class : std_logic_vector(7 downto 0);
+ end record;
+
+ type t_wrf_source_out is record
+ adr : std_logic_vector(1 downto 0);
+ dat : std_logic_vector(15 downto 0);
+ cyc : std_logic;
+ stb : std_logic;
+ we : std_logic;
+ sel : std_logic_vector(1 downto 0);
+ end record;
+
+ type t_wrf_source_in is record
+ ack : std_logic;
+ stall : std_logic;
+ err : std_logic;
+ rty : std_logic;
+ end record;
+
+
+ type t_wrf_oob is record
+ valid: std_logic;
+ oob_type : std_logic_vector(3 downto 0);
+ ts_r : std_logic_vector(27 downto 0);
+ ts_f : std_logic_vector(3 downto 0);
+ frame_id : std_logic_vector(15 downto 0);
+ port_id : std_logic_vector(5 downto 0);
+ end record;
+
+ subtype t_wrf_sink_in is t_wrf_source_out;
+ subtype t_wrf_sink_out is t_wrf_source_in;
+
+ type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
+ type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
+
+ subtype t_wrf_sink_in_array is t_wrf_source_out_array;
+ subtype t_wrf_sink_out_array is t_wrf_source_in_array;
+
+ function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
+ function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
+
+
+end wr_fabric_pkg;
+
+package body wr_fabric_pkg is
+
+ function f_marshall_wrf_status(stat : t_wrf_status_reg)
+ return std_logic_vector is
+ variable tmp : std_logic_vector(15 downto 0);
+ begin
+ tmp(0) := stat.is_hp;
+ tmp(1) := stat.error;
+ tmp(2) := stat.has_smac;
+ tmp(3) := stat.has_crc;
+ tmp(15 downto 8) := stat.match_class;
+ return tmp;
+ end function;
+
+ function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
+ variable tmp : t_wrf_status_reg;
+ begin
+ tmp.is_hp := stat(0);
+ tmp.error := stat(1);
+ tmp.has_smac := stat(2);
+ tmp.has_crc := stat(3);
+ tmp.match_class := stat(15 downto 8);
+ return tmp;
+
+ end function;
+
+
+end wr_fabric_pkg;
diff --git a/hdl/eb_testbench/xmini_bone.vhd b/hdl/eb_testbench/xmini_bone.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8acdc2f4060b79ff5bf9b24a2a8b80b25b83842b
--- /dev/null
+++ b/hdl/eb_testbench/xmini_bone.vhd
@@ -0,0 +1,355 @@
+-- A crude Ethernet controlled WB master, for demonstrating
+-- testbenching in SystemVerilog
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity xmini_bone is
+ generic(
+ g_class_mask : std_logic_vector(7 downto 0);
+
+-- packets matching g_our_ethertype will only be accepted
+ g_our_ethertype : std_logic_vector(15 downto 0));
+
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ -- Packets come here
+ src_o : out t_wrf_source_out;
+ src_i : in t_wrf_source_in;
+
+ -- Packets are sent out from here
+ snk_o : out t_wrf_sink_out;
+ snk_i : in t_wrf_sink_in;
+
+ --
+ master_o : out t_wishbone_master_out;
+ master_i : in t_wishbone_master_in
+ );
+
+end xmini_bone;
+
+architecture behavioral of xmini_bone is
+
+ type t_state is (IDLE, RX_DATA, RX_CHECK, RX_DROP, RX_WAIT_EOP, WB_ISSUE, TX_START_PACKET, TX_STATUS, TX_DATA, TX_FINISH_PACKET, TX_STALL);
+
+
+ signal snk_out : t_wrf_sink_out;
+ signal src_out : t_wrf_source_out;
+
+
+ signal trans_addr : std_logic_vector(31 downto 0);
+ signal trans_wdata : std_logic_vector(31 downto 0);
+ signal trans_rdata : std_logic_vector(31 downto 0);
+
+ signal trans_rx_hdr : std_logic_vector(15 downto 0);
+
+ alias trans_sel is trans_rx_hdr(3 downto 0);
+ alias trans_we is trans_rx_hdr(4);
+
+ signal trans_tx_hdr : std_logic_vector(15 downto 0);
+
+ alias trans_readback is trans_tx_hdr(0);
+ alias trans_error is trans_tx_hdr(1);
+
+ signal rx_remote_mac : std_logic_vector(47 downto 0);
+ signal rx_ethertype : std_logic_vector(15 downto 0);
+
+ signal state : t_state;
+ signal snk_offset : std_logic_vector(31 downto 0);
+ signal src_offset : std_logic_vector(31 downto 0);
+
+ signal d_valid : std_logic;
+ signal d_status : std_logic;
+ signal d_rx_error : std_logic;
+
+ signal decoded_status : t_wrf_status_reg;
+
+ signal stall_int : std_logic;
+
+ signal src_ack_count : unsigned(4 downto 0);
+
+ signal s_zeroes : std_logic_vector(15 downto 0) := x"0000";
+ signal s_our_ethertype : std_logic_vector(15 downto 0) := g_our_ethertype;
+
+
+ function f_sl(x : boolean) return std_logic is
+ begin
+ if(x) then
+ return '1';
+ else
+ return '0';
+ end if;
+ end f_sl;
+
+ procedure f_extract_rx(signal q : out std_logic_vector;
+ signal d : in std_logic_vector;
+ signal d_valid : in std_logic;
+ offset : integer) is
+ begin
+
+ if(snk_offset(offset) = '1' and d_valid = '1') then
+ q <= d;
+ end if;
+ end f_extract_rx;
+
+
+ signal tx_ser_counter : unsigned(6 downto 0);
+
+ procedure f_serialize_tx(
+ signal q : out std_logic_vector;
+ signal x : in std_logic_vector;
+ offset : integer;
+ cnt: unsigned) is
+ begin
+ if (offset >= 0 and cnt = to_unsigned(offset, cnt'length)) then
+ q <= x;
+ end if;
+ end f_serialize_tx;
+
+begin -- behavioral
+
+ trans_tx_hdr(15 downto 2) <= (others => '0');
+
+ decoded_status <= f_unmarshall_wrf_status(snk_i.dat);
+
+ d_valid <= '1' when (snk_i.cyc and snk_i.we and snk_i.stb) = '1' and (snk_i.adr = c_WRF_DATA) else '0';
+ d_status <= '1' when (snk_i.cyc and snk_i.we and snk_i.stb) = '1' and (snk_i.adr = c_WRF_STATUS) else '0';
+ d_rx_error <= d_status and decoded_status.error;
+
+ p_snk_gen_ack : process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ snk_out.ack <= '0';
+ else
+ snk_out.ack <= snk_i.stb and snk_i.cyc and snk_i.we and not snk_out.stall;
+ end if;
+ end if;
+ end process;
+
+ p_offset_sreg : process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ snk_offset <= (0 => '1', others => '0');
+ src_offset <= (0 => '1', others => '0');
+ else
+ if(snk_i.cyc = '0') then
+ snk_offset(0) <= '1';
+ snk_offset(snk_offset'left downto 1) <= (others => '0');
+ elsif(d_valid = '1') then
+ snk_offset <= snk_offset(snk_offset'left-1 downto 0) & '0';
+ end if;
+
+ if(src_out.cyc = '0') then
+ src_offset <= (0 => '1', others => '0');
+ elsif(src_i.stall = '0' and src_out.stb = '1') then
+ src_offset <= src_offset(src_offset'left-1 downto 0) & '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+ p_src_count_acks : process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ src_ack_count <= (others => '0');
+ else
+ if(src_out.cyc = '0') then
+ src_ack_count <= (others => '0');
+ elsif(src_i.ack = '1') then
+ src_ack_count <= src_ack_count + 1;
+ end if;
+ end if;
+ end if;
+
+ end process;
+
+
+
+ p_fsm : process(clk_sys_i)
+ variable tx_offset : integer;
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ state <= IDLE;
+ stall_int <= '0';
+
+ master_o.cyc <= '0';
+ master_o.stb <= '0';
+
+ src_out.cyc <= '0';
+ src_out.stb <= '0';
+ src_out.we <= '1';
+ src_out.sel <= "11";
+ src_out.adr <= (others => '0');
+ src_out.dat <= (others => '0');
+
+ trans_readback <= '0';
+ trans_we <= '0';
+ trans_rdata <= (others => '0');
+ trans_wdata <= (others => '0');
+ trans_addr <= (others => '0');
+ trans_sel <= (others => '0');
+ trans_error <= '0';
+
+ rx_remote_mac <= (others => '0');
+ rx_ethertype <= (others => '0');
+
+ tx_ser_counter <= (others => '0');
+
+
+ else
+
+ case state is
+ when IDLE =>
+ stall_int <= '0';
+ tx_ser_counter <= (others => '0');
+
+ if(snk_i.cyc = '1') then
+ state <= RX_DATA;
+ end if;
+
+ when RX_DATA =>
+
+ f_extract_rx(rx_remote_mac(47 downto 32), snk_i.dat, d_valid, 3);
+ f_extract_rx(rx_remote_mac(31 downto 16), snk_i.dat, d_valid, 4);
+ f_extract_rx(rx_remote_mac(15 downto 0), snk_i.dat, d_valid, 5);
+ f_extract_rx(rx_ethertype, snk_i.dat, d_valid, 6);
+ f_extract_rx(trans_rx_hdr, snk_i.dat, d_valid, 7);
+ f_extract_rx(trans_addr(31 downto 16), snk_i.dat, d_valid, 8);
+ f_extract_rx(trans_addr(15 downto 0), snk_i.dat, d_valid, 9);
+ f_extract_rx(trans_wdata(31 downto 16), snk_i.dat, d_valid, 10);
+ f_extract_rx(trans_wdata(15 downto 0), snk_i.dat, d_valid, 11);
+
+ if(d_rx_error = '1' or snk_i.cyc = '0') then
+ state <= RX_DROP;
+ elsif(d_valid = '1' and snk_offset(12) = '1') then
+ state <= RX_WAIT_EOP;
+ end if;
+
+ when RX_WAIT_EOP =>
+ if(d_rx_error = '1') then
+ state <= RX_DROP;
+ elsif(snk_i.cyc = '0') then -- end-of-packet?
+ stall_int <= '1'; -- stop reception while the cycle is issued
+ state <= RX_CHECK;
+ end if;
+
+ when RX_CHECK =>
+ if(rx_ethertype = g_our_ethertype) then
+ state <= WB_ISSUE;
+ else
+ state <= RX_DROP;
+ end if;
+
+ when WB_ISSUE =>
+ if(master_i.ack = '0') then
+ master_o.cyc <= '1';
+ master_o.stb <= '1';
+ else
+ master_o.cyc <= '0';
+ master_o.stb <= '0';
+ trans_rdata <= master_i.dat;
+ state <= TX_START_PACKET;
+ end if;
+
+ trans_readback <= not trans_we;
+ trans_error <= '0';
+
+
+ when TX_START_PACKET =>
+
+ if(src_i.stall = '0') then
+ state <= TX_STATUS;
+ src_out.stb <= '1';
+ src_out.cyc <= '1';
+ src_out.adr <= c_WRF_STATUS;
+ src_out.dat <= (others => '0');
+ else
+ src_out.stb <= '0';
+ src_out.cyc <= '0';
+ end if;
+
+
+ when TX_STATUS =>
+
+ if(src_i.stall = '0') then
+ src_out.stb <= '1';
+ src_out.adr <= c_WRF_DATA;
+ state <= TX_DATA;
+ f_serialize_tx(src_out.dat, rx_remote_mac(47 downto 32), 0, tx_ser_counter);
+ end if;
+
+
+ when TX_DATA =>
+ src_out.stb <= '1';
+
+ if(src_i.stall = '1')then
+ tx_offset := 0;
+ else
+ tx_offset := -1;
+ end if;
+
+ f_serialize_tx(src_out.dat, rx_remote_mac(47 downto 32), tx_offset + 0, tx_ser_counter);
+ f_serialize_tx(src_out.dat, rx_remote_mac(31 downto 16), tx_offset + 1, tx_ser_counter);
+ f_serialize_tx(src_out.dat, rx_remote_mac(15 downto 0), tx_offset + 2, tx_ser_counter); -- DST MAC
+ f_serialize_tx(src_out.dat, s_zeroes, tx_offset + 3, tx_ser_counter);
+ f_serialize_tx(src_out.dat, s_zeroes, tx_offset + 4, tx_ser_counter);
+ f_serialize_tx(src_out.dat, s_zeroes, tx_offset + 5, tx_ser_counter);
+ f_serialize_tx(src_out.dat, s_our_ethertype, tx_offset + 6, tx_ser_counter);
+ f_serialize_tx(src_out.dat, trans_tx_hdr, tx_offset + 7, tx_ser_counter);
+ f_serialize_tx(src_out.dat, trans_rdata(31 downto 16), tx_offset + 8, tx_ser_counter);
+ f_serialize_tx(src_out.dat, trans_rdata(15 downto 0), tx_offset + 9, tx_ser_counter);
+
+ if(src_i.stall = '0') then
+ tx_ser_counter <= tx_ser_counter + 1;
+ end if;
+
+ if(tx_ser_counter = 30 and src_i.stall = '0') then
+ state <= TX_FINISH_PACKET;
+ src_out.stb <= '0';
+ end if;
+
+
+ when TX_FINISH_PACKET =>
+ if(src_ack_count = 31) then
+ src_out.stb <= '0';
+ src_out.cyc <= '0';
+ state <= IDLE;
+ end if;
+
+ when RX_DROP =>
+ if(snk_i.cyc = '0') then
+ state <= IDLE;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ master_o.dat <= trans_wdata;
+ master_o.adr <= trans_addr;
+ master_o.we <= trans_we;
+ master_o.sel <= trans_sel;
+
+
+ snk_o <= snk_out;
+
+ snk_out.err <= '0';
+ snk_out.rty <= '0';
+ snk_out.stall <= stall_int or (snk_i.cyc and snk_i.stb and f_sl(state = IDLE));
+
+ src_o <= src_out;
+
+
+end behavioral;