You have to supply +5V reference voltage to the OCXO, right? R111 is declared unmounted, so will not apply ref voltage to it. the LTC2641 does not have internal Vref. Resolution: Not for the Morion VCXO that we’re going to use – it has its’ internal ref generator that feeds the DAC.
In addition, you have selected +3V reference voltage (DAC will gives 0->+3V output), the OCXO tune range is 0->+5V. So you do not cover the whole tune range. Resolution: Morion VCXO produces a 5V reference.
You did not place a capacitor on the TRIM/NR pin of the REF5030. Resolution: Done, placed 1u.
From my arithmetic, the reference voltage only will give you a frequency vs temperature of 310^-12/°C. Where as the OCXO itself is specified 710^-12/°C (+20 to +40°C). I guess is fine? maybe high grade for the REF5030AID?
Resolution: I don’t believe the temp coef of the DAC/reference (if I understood correctly your comment) will have an impact on the stability, as they are a part of a feedback loop. Temperature changes are slow enough to be in-band for the PLL.
We need to add a 10MHz output. I think we have space on the frontpanel. Either use a 10/15dB directional coupler on the OCXO output + an amplifier. Or use a LTC6950 ouput for it? and we use a ADCLK925 for CLK_A and CLK_B so that we use only a single output for them? (using the divider in the AD9520)
the DDS clocks are AC coupled twice, once on the pll.SchDoc, once on the RF_generation.SchDoc. Maybe you can replace the 100nF by 0ohm resistor 0402. I do not like having the diff tranmission line floating (DC) if it is AC coupled at both ends. Resolution: OK.
Same comment for CLK_A and CLKB, AC coupling cap already on the clk_distribution.SchDoc. Resolution: OK.
For the VCSO, do you plan to buy part with specific phase noise performance? typical value are -105dBc/Hz @1kHz which would lead to ~-123dBc/Hz @125MHz with a BW=3kHz. +7dB above the limit. So we need to buy one as good as shown on the graph <115dBc/Hz or better!
I would AC couple the CLK_REF_P/N clock in order to avoid DC voltage link between the two boards. How is the clock input stage on the eRTM14?
For the LTC6950, SDO signal. It is recommended to use high value resistor 200k to GND if the LTC6950 is not used in a multidrop. 4.12kohm seems to be a bit too low for this output current capability.
For the REF+/- input of the LTC6950, you are using back-to-back diodes. This will clamp the signal to ~0.6Vpp differential where as the inputs accept 3Vpp diff maximum. Do we really want to get that? in addition you circuit will not be matched anymore once the diode clamp.
Use also a MAX9111 for the sync, this will allow other sync scheme
SPI buses could be share
Maybe put two 0ohm resistors in serie to the pins PD and reset of the AD9520. You may want to control only one of them (reset)
I do not have much info on the DAC output stage, but if I will assume it is like the AD9122 that I already use, so:
By using a transformer (TR5) your have short-circuit in DC for the DAC output. So before you configure your DDS, I expect the DACs driving constant 10mA on (both outputs)! Then for the output amplitude, I guess you use current fullscale=20mA, so with 50ohm resistor to GND and a shunt 100ohm resistor you get 1Vpp differential => +10dBm. With the transformer you lose 3dB, with the filter you lose 0.5dB => +6.5dBm. The rf_amplifier has a gain of 15.5dB so you end up with 22dBm . You expected to get 12dBm.
I would use the PAT attenuator (mini-circuit) instead of designing your own pi attenuator.
I would add small value attenuator between RLP-filter a & amplifier, or before also the RLP-264 to improve matching
I would re-use the same ferrite bead 390 to optimize the BOM (and increase the impedance by the way)
There is no 100ohm termination for the SYNC_P/N input of the AD9910. Are we sure there is internal 100ohm? I have not found anything in the datasheet
Why a 0 ohm resistor on the P1V8? I would remove it to optimize the PCB routing
Add a 0 ohm resistor in serie to the RF_detector for PWR_PA. If you use the RF_PROBE (J21), you cannot have two 50ohm path in parallel
I would make the control of the rf_detector independently of the control of the RF switch, we will have unused slots and you still want to monitor the channel in used without switching on the channel used. otherwise the power measurement will be wrong due to full reflection on unused channel.
I would place an RF attenuator (PAT-2+) in series to the RF_FP1/2 signal. It improve a bit the output matching and with can "adjust" the output level.
There are mistake in I2C addresses, the one I found in the datasheet and the one you put in comments in the schematics do not match. Please check.
You are using a voltage divider for the voltage monitoring with the STM32, but the input impedance of the ADC's of the STM32 are not infinite and vary with the sampling rate! In the datasheet, you have the maximum source impedance specified, and it can be as low as 18ohm, or as high as 100kohm. You voltage divider will not be negligible depending on your sampling rate
You put a note saying that the a6/b6 signals are used for a reset by NAT, LVDS? (from the DRTM-LOG1300 manual is a diff pair!) You have connected b6 to GND, should we connect these two pin to the STM32?
I would number the zone1 connectors from J10 to J17 like in the RF backplane datasheet. Do you have better solution? Hard for me to check if you put the right signal (LO, REF) at the right position...
For the LTC6950 (PLL), on the page 33 of the datasheet, i can read the output divider can be synchronize with the N divider. This would mean that the clock output would be in sync with the 10MHz OCXO (as the R divider=1). In that case having a directional coupler on the OCXO signal directly for a 10MHz output on the front panel would be okay.
I found the LMH2120 chip for RF power detector, its output is high Z when disable which would allow your multiplexing. The chip is very tiny as well and has 50ohm input. However it would need ~15dB attenuator at the input (pi attenuator with 130ohm and 68ohm 0402 resistor would do the job).
Add input matching as the PHA-101+ is poorly match and this will affect overall phase stability (which is critical in our case)
Remove 2.2nF cap between the PHA-101+ and matching circuit (you already have a 2.2nF after the matching circuit)
390nH is at the limit and could be increased. this gives only ~415ohm @200MHz. This is in parallel to 50ohm of the amplifier output and degrade matching
The RF switch HSWA2-30DR+:
Very sensitive to DC voltage on the RF input/output. AC coupling is required on the outputs to avoid damage.
You can expect Leakage of the RF to the supply and control pins. Add 2.2nF decoupling on pins 16,17 & 20.
RF power detector
As a remark, compare to IC, diode detector is looking for problem if it is not absolutely required (drift, accuracy, dynamic range,...). It looks ok on simulation but you need to test it on bare board the lab prior to make the PCB to make sure it works
It seems to work only because you do not put RF signal while you close the mosfet, otherwise the mosfet will leaks through its substrate diode
BSH103 is not recommended for new design, to be changed
The input of the op-amp (LTC1678) is floating, add maybe a pull-down
The output voltage of the follower (LTC1678) for RF_DISTR signal will be around 800mV for +14dBm, 200mV for +5dBm. 200mV is the minimum voltage for the op-amp (min output swing), so we have only 10dB dynamic range. It is not great but ok if only to check if no failure.
Add 3 more temp sensors: under AD9150 (2x) and under LTC6950.
I forgot to check the LDOs of LO/REF. The correct one were TPS7A4701 (instead of LT1764A, to improve thermal and noise). But the one in the schematics are TPS7A8901, they cannot operate at 11V input voltage.
Fix multiple nets issue (need unique designators for hierarchical blocks)
Change SMD 330 uF cap to 220u THT
Change pushbutton to smaller one
Reorganized regulators (split into hierarchical submodules)