Commit a0915e66 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

eRTM14: sync with EDMS

parent 1116eae5
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Record=SheetSymbol|SourceDocument=node_top.SchDoc|Designator=U_clk_external|SchDesignator=U_clk_external|FileName=clk_external.SchDoc|SymbolType=Normal|RawFileName=clk_external.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=node_top.SchDoc|Designator=U_fpga_configuration|SchDesignator=U_fpga_configuration|FileName=fpga_configuration.SchDoc|SymbolType=Normal|RawFileName=fpga_configuration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=node_top.SchDoc|Designator=U_FPGA_local_peripherals|SchDesignator=U_FPGA_local_peripherals|FileName=FPGA_local_peripherals.SchDoc|SymbolType=Normal|RawFileName=FPGA_local_peripherals.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=node_top.SchDoc|Designator=U_FPGA_misc_peripherals|SchDesignator=U_FPGA_misc_peripherals|FileName=FPGA_misc_peripherals.SchDoc|SymbolType=Normal|RawFileName=FPGA_misc_peripherals.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=node_top.SchDoc|Designator=U_management|SchDesignator=U_management|FileName=management.SchDoc|SymbolType=Normal|RawFileName=management.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=node_top.SchDoc|Designator=U_mtca_connector|SchDesignator=U_mtca_connector|FileName=mtca_connector.SchDoc|SymbolType=Normal|RawFileName=mtca_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=transceivers.SchDoc|Designator=U_gtx_rx_link1|SchDesignator=U_gtx_rx_link1|FileName=gtx_data_splitter.SchDoc|SymbolType=Normal|RawFileName=gtx_data_splitter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=transceivers.SchDoc|Designator=U_gtx_tx_link0|SchDesignator=U_gtx_tx_link0|FileName=gtx_data_splitter.SchDoc|SymbolType=Normal|RawFileName=gtx_data_splitter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=transceivers.SchDoc|Designator=U_gtx_tx_link1|SchDesignator=U_gtx_tx_link1|FileName=gtx_data_splitter.SchDoc|SymbolType=Normal|RawFileName=gtx_data_splitter.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=frontpanel.SchDoc|Designator=U_led_fp|SchDesignator=U_led_fp|FileName=led_fp.SchDoc|SymbolType=Normal|RawFileName=led_fp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=frontpanel.SchDoc|Designator=U_led_fp|SchDesignator=U_led_fp|FileName=led_fp.SchDoc|SymbolType=Normal|RawFileName=led_fp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
DAC_CONTROL=\S\Y\N\C\,SCLK,DIN
FPGA_Link=SCLK,SDO,SDI,INT
LINK_CTRL=LOS_TX_FAULT,DETECT,SCL,SDA,LED_ACTIVITY,LED_LINK,TX_DISABLE
LINK_CTRL=SDA,TX_DISABLE,SCL,DETECT,LED_ACTIVITY,LED_LINK,LOS_TX_FAULT
PLL_CTRL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_RESET,PLL_LOCK,PLL_CS
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