Commit 9e4ce89f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

eRTM15: pre-DEM version of the layout + updated schematics

parent a0915e66
This diff is collapsed.
This diff is collapsed.
LO_CONTROL=SER,UPDATECLK,SHIFTCLK
RF_CHANNELS=CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,CH12
AD9910_PD=SER,UPDATECLK,SHIFTCLK
AD9910_PDATA=RAM_SWP_OVR,F[1..0],PDCLK_P,PDCLK_N,SYNC_CLK_P,SYNC_CLK_N,PROFILE[2..0],IOUPDATE_P,IOUPDATE_N,{PD:AD9910_PD}
AD9910_SPI=SDO,SDIO,SCLK
AD9910_SYNC=SYNC_IN_P,SYNC_ERROR
DDS_CONTROL=SDO,SDI_P,SDI_N,SCLK_P,SCLK_N,PROFILE2,PROFILE1,PROFILE0,SYNC_CLK_P,SYNC_CLK_N,IOUPDATE_P,IOUPDATE_N,SYNC_IN_P,SYNC_IN_N,SYNC_ERROR,RESET
AD9520_CONTROL=SCLK,SDI,SDO,SYNC_N_P,SYNC_N_N
CLK_BP=CLK_4_P,CLK_4_N,CLK_5_P,CLK_5_N,CLK_6_P,CLK_6_N,CLK_7_P,CLK_7_N,CLK_8_P,CLK_8_N,CLK_9_P,CLK_9_N,CLK_10_P,CLK_10_N,CLK_11_P,CLK_11_N,CLK_12_P,CLK_12_N,CLK_13_P,CLK_13_N,CLK_14_P,CLK_14_N
AD9520_CONTROL=SCLK,SDI,SYNC_N_P,SDO,SYNC_N_N
ADC_CONTROL=SCLK,DOUT,DIN
B2B_DAC_CONTROL=DIN,SCLK,\C\L\R\
DDS_CONTROL=SDI_P,SCLK_P,SDI_N,SCLK_N,SYNC_CLK_P,IOUPDATE_P,SYNC_CLK_N,IOUPDATE_N,SYNC_IN_P,PROFILE2,SYNC_IN_N,PROFILE1,SYNC_ERROR,PROFILE0,RESET,SDO
FPGA_Link=SDI,SDO,SCLK,INT
PLL_CONTROL=SCLK,SDI,SDO,SYNC,CE_PLL,CE_DISTR
RF_CONTROL=SER,UPDATECLK,SHIFTCLK
BP_GA=GA0,GA1,GA2
BP_LVDS_DATA=A_P,A_N,B_P,B_N,C_P,C_N
CLK_BP=CLK_4_P,CLK_4_N,CLK_5_P,CLK_5_N,CLK_6_P,CLK_6_N,CLK_7_P,CLK_7_N,CLK_8_P,CLK_8_N,CLK_9_P,CLK_9_N,CLK_10_P,CLK_10_N,CLK_11_P,CLK_11_N,CLK_12_P,CLK_12_N,CLK_13_P,CLK_13_N,CLK_14_P,CLK_14_N
IPMB=SCL_L,SDA_L
RF_CHANNELS=CH4,CH5,CH6,CH7,CH8,CH9,CH10,CH11,CH12
AD9910_PD=SER,UPDATECLK,SHIFTCLK
AD9910_PDATA=RAM_SWP_OVR,F[1..0],PDCLK_P,PDCLK_N,SYNC_CLK_P,SYNC_CLK_N,PROFILE[2..0],IOUPDATE_P,IOUPDATE_N,{PD:AD9910_PD}
AD9910_SPI=SDO,SDIO,SCLK
AD9910_SYNC=SYNC_IN_P,SYNC_IN_N,SYNC_ERROR
SR_CONTROL=SER,UPDATECLK,SHIFTCLK
BP_GA=GA0,GA1,GA2
BP_LVDS_DATA=A_P,A_N,B_P,B_N,C_P,C_N
FPGA_Link=SCLK,SDO,SDI,INT
IPMB=SDA_L,SCL_L
POWER_CONTROL=P3V6_EN,P3V6_PG,P3V3_EN,P3V3_PG,P3V3_PLL_EN,P3V3_PLL_PG,P1V8_EN,P1V8_PG,P5V0_EN,PVADJ_OCXO_EN,P9V0_LO_EN,P9V0_REF_EN,P5V0_PG,OCXO_CURRENT
SR_CONTROL=SER,UPDATECLK,SHIFTCLK
Temperature_sensor=SDA,SCL
BP_GA=GA0,GA1,GA2
BP_LVDS_DATA=A_P,A_N,B_P,B_N,C_P,C_N
CLK_BP=CLK_4_P,CLK_4_N,CLK_5_P,CLK_5_N,CLK_6_P,CLK_6_N,CLK_7_P,CLK_7_N,CLK_8_P,CLK_8_N,CLK_9_P,CLK_9_N,CLK_10_P,CLK_10_N,CLK_11_P,CLK_11_N,CLK_12_P,CLK_12_N,CLK_13_P,CLK_13_N,CLK_14_P,CLK_14_N
IPMB=SCL_L,SDA_L
PLL_CONTROL=SCLK,SDI,SDO,SYNC,CE_PLL,CE_DISTR
POWER_CONTROL=P3V6_EN,P3V6_PG,P3V3_EN,P3V3_PG,P3V3_PLL_EN,P3V3_PLL_PG,P1V8_EN,P1V8_PG,P5V0_EN,PVADJ_OCXO_EN,P9V0_LO_EN,P9V0_REF_EN,P5V0_PG,OCXO_CURRENT
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