DIOT - Distributed IO Tier issueshttps://ohwr.org/project/diot/issues2022-11-30T14:59:54Zhttps://ohwr.org/project/diot/issues/13SERVMOD pull-down on Peripheral Board might be too strong2022-11-30T14:59:54ZGrzegorz DanilukSERVMOD pull-down on Peripheral Board might be too strong220 Ohm is a strong pull-down requiring FPGA on a System Board to constantly output 15mA per slot. Maybe we could use a larger resistance there?https://ohwr.org/project/diot/issues/12Add Peripheral RTM (P4) connector pinout recommendation2021-01-28T09:50:22ZGrzegorz DanilukAdd Peripheral RTM (P4) connector pinout recommendationI took some inspiration from FMC and MTCA.4 standards.
![image](/uploads/74074fd0c798acafbfa739f68679ea10/image.png)
* VCC_RTM - is +12V by default but can be a different voltage depending on the RTM/Peripheral board design
* P3V3 - is a low power (max 300mA) mainly to be used by identification EEPROM connected to SCL/SDA lines
* VIO - is the equivalent of Vadj in FMC, it's a voltage for powering the I/O buffers to match peripheral board voltage (in the case of [DI/OT Peripheral FMC Carrier](https://ohwr.org/project/diot-pfc-ku) it's 2.5V)
* SCL/SDA - identification I2C, connected together with the main backplane I2C on Peripheral Board.
* RST_N - reset line from the P1 backplane connector
* PS# - RTM presence detection
* TRST/TDO/TDI/TMS/TCK - pins reserved for JTAG, if RTM/Peripheral board doesn't have JTAG capabilities it shall tie TDI with TDO
* all the rest are general purpose I/Os, GND, RTM_BUS, Vext1/2 - all were already defined in current specification.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/11Peripheral Boards: add requirement to pull-up GA0..3 lines on the board.2020-12-11T15:54:14ZGrzegorz DanilukPeripheral Boards: add requirement to pull-up GA0..3 lines on the board.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/10Add pinout of Ext Power Supply backplane connector to the specification.2020-11-17T14:13:47ZGrzegorz DanilukAdd pinout of Ext Power Supply backplane connector to the specification.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/9Mention that SHARED_BUS lines are pulled up at the system board2020-11-13T16:22:26ZChristos GentsosMention that SHARED_BUS lines are pulled up at the system boardIt's mentioned in the specs that SHARED_BUS lines can serve as interlock lines. Even though it makes perfect sense that to be used like that, they'd be pulled up somewhere and the peripheral boards would then connect open-drain outputs to pull them down, it would be worth it to mention the pull-ups explicitly.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/8Fix IC_SCL, IC_SDA typo on pp. 8, 252020-11-11T10:51:29ZChristos GentsosFix IC_SCL, IC_SDA typo on pp. 8, 25They should be changed to I2C_* (well, either that or I2C_* on p. 21 has to be changed in the other direction).Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/7Consider renaming SERVMOD_N to SERVMOD2020-11-17T15:57:43ZChristos GentsosConsider renaming SERVMOD_N to SERVMODFrom the specifications text is follows that it's not active-low. For example, in the identification procedure it's mentioned that "low = board inserted in a given peripheral slot", which would then make Service Mode the default peripheral board state.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/6Add a reminder about floating I/Os and CMOS inputs2020-11-10T16:55:43ZChristos GentsosAdd a reminder about floating I/Os and CMOS inputsThe peripheral board I/Os are connected directly to the FPGA I/Os, which might be left floating at times. CMOS inputs usually aren't OK with this so a reminder could be added to the specs, saying that the peripheral boards are responsible for adding pull-{ups,downs} to make sure that CMOS inputs are given a well-defined logic level at all times.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/5P_RST and F_RST nets are active low, they need to be renamed to _N2020-10-23T16:57:33ZChristos GentsosP_RST and F_RST nets are active low, they need to be renamed to _NThe MoniMod power cycle nets, P_RST and F_RST, are active low. They need to be renamed to P_RST_N and F_RST_N.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/4Consider making it explicit that PWRBTN_N and PRST_N shouldn't be pulled up i...2020-10-08T14:45:37ZChristos GentsosConsider making it explicit that PWRBTN_N and PRST_N shouldn't be pulled up in the system boardThe CPCI-S standard dictates that these two nets be pulled up at the system board, but in the DI/OT specs they are repurposed to general-purpose I/Os, connected directly to the FPGA, to serve the user's needs. On one hand it might be obvious that they shouldn't be pulled up but it could also be made explicit, a rule could be added to the System Board chapter (resembling rule 6.1.10 of the 200626 version).Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/3Conflicting rules on differential pair length matching2020-10-07T13:22:02ZChristos GentsosConflicting rules on differential pair length matchingRule 2.1.8 says that 15 pairs per peripheral slot aren't length matched as they'll carry slow signals. However, in 2.1.9 a strict length matching is mentioned (of 5mm, or ~33ps). I suppose the latter can be either removed or relaxed (and 2.1.8 slightly modified in that case).
Also, it's not entirely clear to me if the length matching mentioned in 2.1.9 should apply within each differential pair or to the whole group of differential pairs that goes into each peripheral board, though that might be just me.Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/2Define the CPCI-S signal assignment of the 5 SHARED_BUS lines2020-10-07T12:54:38ZChristos GentsosDefine the CPCI-S signal assignment of the 5 SHARED_BUS linesIt should be defined which lines provide the five SHARED_BUS nets by referring to their CPCI-S names, much like it is defined in sections 2.1.6-7 which lines can (optionally) carry the MGT and clock signals. The assignments used in the Zynq-Ultrascale-based system board (and adopted by the Igloo2-based one) are shown on the table below:
|CPCI-S|SHARED_BUS bit|
|-|-|
|SATA_SL|4|
|SATA_SCL|3|
|SATA_SDO|2|
|SATA_SDI|1|
|WAKE_IN_N|0|Grzegorz DanilukGrzegorz Danilukhttps://ohwr.org/project/diot/issues/1Reconcile FMC and CPCI-S 12V power supply margins2020-10-07T12:44:01ZChristos GentsosReconcile FMC and CPCI-S 12V power supply marginsThe CPCI-S specifies a ±10% margin for the 12V, while FMC only allows ±5%. Since the system boards will generally pass the 12V directly to the mezzanine, we might want to consider adding a clause in the DI/OT specs to apply a ±5% margin to the 12V, deviating from the more relaxed CPCI-S specifications. That way we don't lose compatibility with any (hypothetical) FMC-compliant communication mezzanines that might need the tight margins.Grzegorz DanilukGrzegorz Daniluk