Commit 958a4281 authored by Tristan Gingold's avatar Tristan Gingold

urv_demo: add pll.

parent 22e2c73c
......@@ -8,7 +8,7 @@ vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt +incdir+../../s
# create a fake proasic3 library needed by nanofip
#sim_pre_cmd = "vlib ../fake_proasic3; vmap proasic3 ../fake_proasic3"
files = ["diot_urv_top.vhd"]
files = ["diot_urv_top.vhd", "pll_25_50.vhd"]
#include_dirs = [ "../../sim", "../../sim/include", "../../sim/include/wb" ]
......
......@@ -103,6 +103,18 @@ architecture rtl of diot_urv_top is
y : out std_logic);
end component;
component INBUF
port (
pad : in std_logic;
y : out std_logic);
end component;
component PLLINT
port (
a : in std_logic;
y : out std_logic);
end component;
component DFN1C1
port (
d : in std_logic;
......@@ -158,7 +170,24 @@ architecture rtl of diot_urv_top is
signal mbox_in_wr : std_logic;
signal mbox_in_rd : std_logic;
signal mbox_in_rdy : std_logic;
signal clk_25m_in : std_logic;
signal clk : std_logic;
signal pll_lock : std_logic;
begin
inst_clk_pad : PLLINT
port map (
a => clk_25m_i,
y => clk_25m_in
);
inst_pll: entity work.pll_25_50
port map (
powerdown => '1',
clka => clk_25m_in,
lock => pll_lock,
gla => clk
);
-------------------------------------------------------------------------------
-- Power-on-reset according to Microsemi Application Note AC380
......@@ -173,20 +202,20 @@ begin
cmd_por_DFF1: DFN1C1
port map (
d => '1',
clk => clk_25m_i,
clk => clk,
clr => por_n_buf,
q => por_n_d(0));
cmd_por_DFF2: DFN1C1
port map (
d => por_n_d(0),
clk => clk_25m_i,
clk => clk,
clr => por_n_buf,
q => por_n_d(1));
process(clk_25m_i)
process(clk)
begin
if rising_edge(clk_25m_i) then
if rising_edge(clk) then
if (por_n_d(1) = '0' or button_i = '1') then
rst_cnt <= t_rst_cnt'high;
elsif rst_cnt /= 0 then
......@@ -194,7 +223,7 @@ begin
end if;
end if;
end process;
rst_n <= '1' when rst_cnt = 0 else
rst_n <= '1' when rst_cnt = 0 and pll_lock = '1' else
'0';
-------------------------------------------------------------------------------
......@@ -202,20 +231,20 @@ begin
-------------------------------------------------------------------------------
cmp_sync_ffs_var1: entity work.gc_sync
port map(
clk_i => clk_25m_i,
clk_i => clk,
rst_n_a_i => rst_n,
d_i => var1_rdy_i,
q_o => var1_rdy_synced);
cmp_sync_ffs_var3: entity work.gc_sync
port map(
clk_i => clk_25m_i,
clk_i => clk,
rst_n_a_i => rst_n,
d_i => var3_rdy_i,
q_o => var3_rdy_synced);
process (clk_25m_i, rst_n)
process (clk, rst_n)
begin
if rising_edge(clk_25m_i) then
if rising_edge(clk) then
if rst_n = '0' then
-- Variable was not read.
var1_read <= '0';
......@@ -240,9 +269,9 @@ begin
var3_acc_o <= var3_acc;
-- Mailboxes (from FIP POV).
process(clk_25m_i)
process(clk)
begin
if rising_edge(clk_25m_i) then
if rising_edge(clk) then
if rst_n = '0' then
mbox_in_rdy <= '0';
mbox_out_rdy <= '0';
......@@ -275,7 +304,7 @@ begin
g_iram_init => "../../../sw/fip_urv/fip_urv.ram"
)
port map (
clk_sys_i => clk_25m_i,
clk_sys_i => clk,
rst_n_i => rst_n,
dwb_o => wb_fip_in,
dwb_i => wb_fip_out
......@@ -284,7 +313,7 @@ begin
inst_fip_regs: entity work.fip_urv_regs
port map (
rst_n_i => rst_n,
clk_i => clk_25m_i,
clk_i => clk,
wb_i => wb_fip_in,
wb_o => wb_fip_out,
plc_ctrl_rstn_o => plc_rst_n,
......@@ -340,7 +369,7 @@ begin
plc_mem_o => wb_mem_in
);
wclk_o <= clk_25m_i;
wclk_o <= clk;
rst_o <= not rst_n;
nostat_o <= '1';
rstin_o <= rst_n;
......@@ -359,7 +388,7 @@ begin
g_dram_log_size => 12
)
port map (
clk_sys_i => clk_25m_i,
clk_sys_i => clk,
rst_n_i => plc_rst_n,
ram_wb_i => wb_mem_in,
ram_wb_o => wb_mem_out,
......@@ -370,7 +399,7 @@ begin
inst_plc_regs: entity work.plc_urv_regs
port map (
rst_n_i => plc_rst_n,
clk_i => clk_25m_i,
clk_i => clk,
wb_i => wb_plc_in,
wb_o => wb_plc_out,
mailboxes_mboxout_o => mbox_in_dat,
......@@ -432,8 +461,9 @@ begin
-- Leds: assign to '0' to switch on the led, 'Z' to switch off.
leds_o(0) <= '0' when rst_n = '0' or leds(0) = '1' else 'Z';
leds_o(1) <= '0' when pll_lock = '0' or leds(1) = '1' else 'Z';
GEN_LEDS_O: for I in 1 to 5 generate
GEN_LEDS_O: for I in 2 to 5 generate
leds_o(I) <= '0' when leds(I) = '1' else
'Z';
end generate;
......
-- Version: v11.8 SP3 11.8.3.6
library ieee;
use ieee.std_logic_1164.all;
library proasic3e;
use proasic3e.all;
entity PLL_25_50 is
port( POWERDOWN : in std_logic;
CLKA : in std_logic;
LOCK : out std_logic;
GLA : out std_logic
);
end PLL_25_50;
architecture DEF_ARCH of PLL_25_50 is
component PLL
generic (VCOFREQUENCY:real := 0.0);
port( CLKA : in std_logic := 'U';
EXTFB : in std_logic := 'U';
POWERDOWN : in std_logic := 'U';
GLA : out std_logic;
LOCK : out std_logic;
GLB : out std_logic;
YB : out std_logic;
GLC : out std_logic;
YC : out std_logic;
OADIV0 : in std_logic := 'U';
OADIV1 : in std_logic := 'U';
OADIV2 : in std_logic := 'U';
OADIV3 : in std_logic := 'U';
OADIV4 : in std_logic := 'U';
OAMUX0 : in std_logic := 'U';
OAMUX1 : in std_logic := 'U';
OAMUX2 : in std_logic := 'U';
DLYGLA0 : in std_logic := 'U';
DLYGLA1 : in std_logic := 'U';
DLYGLA2 : in std_logic := 'U';
DLYGLA3 : in std_logic := 'U';
DLYGLA4 : in std_logic := 'U';
OBDIV0 : in std_logic := 'U';
OBDIV1 : in std_logic := 'U';
OBDIV2 : in std_logic := 'U';
OBDIV3 : in std_logic := 'U';
OBDIV4 : in std_logic := 'U';
OBMUX0 : in std_logic := 'U';
OBMUX1 : in std_logic := 'U';
OBMUX2 : in std_logic := 'U';
DLYYB0 : in std_logic := 'U';
DLYYB1 : in std_logic := 'U';
DLYYB2 : in std_logic := 'U';
DLYYB3 : in std_logic := 'U';
DLYYB4 : in std_logic := 'U';
DLYGLB0 : in std_logic := 'U';
DLYGLB1 : in std_logic := 'U';
DLYGLB2 : in std_logic := 'U';
DLYGLB3 : in std_logic := 'U';
DLYGLB4 : in std_logic := 'U';
OCDIV0 : in std_logic := 'U';
OCDIV1 : in std_logic := 'U';
OCDIV2 : in std_logic := 'U';
OCDIV3 : in std_logic := 'U';
OCDIV4 : in std_logic := 'U';
OCMUX0 : in std_logic := 'U';
OCMUX1 : in std_logic := 'U';
OCMUX2 : in std_logic := 'U';
DLYYC0 : in std_logic := 'U';
DLYYC1 : in std_logic := 'U';
DLYYC2 : in std_logic := 'U';
DLYYC3 : in std_logic := 'U';
DLYYC4 : in std_logic := 'U';
DLYGLC0 : in std_logic := 'U';
DLYGLC1 : in std_logic := 'U';
DLYGLC2 : in std_logic := 'U';
DLYGLC3 : in std_logic := 'U';
DLYGLC4 : in std_logic := 'U';
FINDIV0 : in std_logic := 'U';
FINDIV1 : in std_logic := 'U';
FINDIV2 : in std_logic := 'U';
FINDIV3 : in std_logic := 'U';
FINDIV4 : in std_logic := 'U';
FINDIV5 : in std_logic := 'U';
FINDIV6 : in std_logic := 'U';
FBDIV0 : in std_logic := 'U';
FBDIV1 : in std_logic := 'U';
FBDIV2 : in std_logic := 'U';
FBDIV3 : in std_logic := 'U';
FBDIV4 : in std_logic := 'U';
FBDIV5 : in std_logic := 'U';
FBDIV6 : in std_logic := 'U';
FBDLY0 : in std_logic := 'U';
FBDLY1 : in std_logic := 'U';
FBDLY2 : in std_logic := 'U';
FBDLY3 : in std_logic := 'U';
FBDLY4 : in std_logic := 'U';
FBSEL0 : in std_logic := 'U';
FBSEL1 : in std_logic := 'U';
XDLYSEL : in std_logic := 'U';
VCOSEL0 : in std_logic := 'U';
VCOSEL1 : in std_logic := 'U';
VCOSEL2 : in std_logic := 'U'
);
end component;
component GND
port(Y : out std_logic);
end component;
component VCC
port(Y : out std_logic);
end component;
signal \VCC\, \GND\ : std_logic;
signal GND_power_net1 : std_logic;
signal VCC_power_net1 : std_logic;
begin
\GND\ <= GND_power_net1;
\VCC\ <= VCC_power_net1;
Core : PLL
generic map(VCOFREQUENCY => 50.000)
port map(CLKA => CLKA,
EXTFB => \GND\,
POWERDOWN => POWERDOWN,
GLA => GLA,
LOCK => LOCK,
GLB => OPEN,
YB => OPEN,
GLC => OPEN,
YC => OPEN,
OADIV0 => \GND\,
OADIV1 => \GND\,
OADIV2 => \GND\,
OADIV3 => \GND\,
OADIV4 => \GND\,
OAMUX0 => \GND\,
OAMUX1 => \GND\,
OAMUX2 => \VCC\,
DLYGLA0 => \GND\,
DLYGLA1 => \GND\,
DLYGLA2 => \GND\,
DLYGLA3 => \GND\,
DLYGLA4 => \GND\,
OBDIV0 => \GND\,
OBDIV1 => \GND\,
OBDIV2 => \GND\,
OBDIV3 => \GND\,
OBDIV4 => \GND\,
OBMUX0 => \GND\,
OBMUX1 => \GND\,
OBMUX2 => \GND\,
DLYYB0 => \GND\,
DLYYB1 => \GND\,
DLYYB2 => \GND\,
DLYYB3 => \GND\,
DLYYB4 => \GND\,
DLYGLB0 => \GND\,
DLYGLB1 => \GND\,
DLYGLB2 => \GND\,
DLYGLB3 => \GND\,
DLYGLB4 => \GND\,
OCDIV0 => \GND\,
OCDIV1 => \GND\,
OCDIV2 => \GND\,
OCDIV3 => \GND\,
OCDIV4 => \GND\,
OCMUX0 => \GND\,
OCMUX1 => \GND\,
OCMUX2 => \GND\,
DLYYC0 => \GND\,
DLYYC1 => \GND\,
DLYYC2 => \GND\,
DLYYC3 => \GND\,
DLYYC4 => \GND\,
DLYGLC0 => \GND\,
DLYGLC1 => \GND\,
DLYGLC2 => \GND\,
DLYGLC3 => \GND\,
DLYGLC4 => \GND\,
FINDIV0 => \GND\,
FINDIV1 => \GND\,
FINDIV2 => \VCC\,
FINDIV3 => \GND\,
FINDIV4 => \GND\,
FINDIV5 => \GND\,
FINDIV6 => \GND\,
FBDIV0 => \VCC\,
FBDIV1 => \GND\,
FBDIV2 => \GND\,
FBDIV3 => \VCC\,
FBDIV4 => \GND\,
FBDIV5 => \GND\,
FBDIV6 => \GND\,
FBDLY0 => \GND\,
FBDLY1 => \GND\,
FBDLY2 => \GND\,
FBDLY3 => \GND\,
FBDLY4 => \GND\,
FBSEL0 => \VCC\,
FBSEL1 => \GND\,
XDLYSEL => \GND\,
VCOSEL0 => \GND\,
VCOSEL1 => \VCC\,
VCOSEL2 => \GND\);
GND_power_inst1 : GND
port map( Y => GND_power_net1);
VCC_power_inst1 : VCC
port map( Y => VCC_power_net1);
end DEF_ARCH;
-- _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._
-- _GEN_File_Contents_
-- Version:11.8.3.6
-- ACTGENU_CALL:1
-- BATCH:T
-- FAM:PA3
-- OUTFORMAT:VHDL
-- LPMTYPE:LPM_PLL_STATIC
-- LPM_HINT:NONE
-- INSERT_PAD:NO
-- INSERT_IOREG:NO
-- GEN_BHV_VHDL_VAL:F
-- GEN_BHV_VERILOG_VAL:F
-- MGNTIMER:F
-- MGNCMPL:T
-- DESDIR:C:/Users/gdaniluk/cernbox/windows_shared/diot-wic/hdl/syn/diot_wic_demo/smartgen\PLL_25_50
-- GEN_BEHV_MODULE:F
-- SMARTGEN_DIE:IT14X14M4
-- SMARTGEN_PACKAGE:fg896
-- AGENIII_IS_SUBPROJECT_LIBERO:T
-- FIN:25.000000
-- CLKASRC:0
-- FBDLY:1
-- FBMUX:1
-- XDLYSEL:0
-- PRIMFREQ:50.000000
-- PPHASESHIFT:0
-- DLYAVAL:1
-- OAMUX:4
-- POWERDOWN_POLARITY:0
-- LOCK_POLARITY:1
-- LOCK_CTL:0
-- VOLTAGE:1.5
-- _End_Comments_
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