adding simple design to use SB as peripheral baord with FMC DIO

8ef1c4fb · Grzegorz Daniluk · 1a8ca7f0 · 8ef1c4fb · 8ef1c4fb · 8ef1c4fb
Commit 8ef1c4fb authored Mar 03, 2020 by Grzegorz Daniluk
4 changed files
--- a/hdl/syn/diot_periph_dio.tcl
+++ b/hdl/syn/diot_periph_dio.tcl
+# Microsemi Tcl Script
+# libero
+# Date: Mon Jul 30 12:30:24 2018
+
+
+new_project -location {./diot_periph_dio} -name {diot_periph_dio} -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -use_enhanced_constraint_flow 0 -hdl {VHDL} -family {ProASIC3E} -die {A3PE3000} -package {896 FBGA} -speed {STD} -die_voltage {1.5} -part_range {COM} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:COM} -adv_options {VCCI_1.5_VOLTR:COM} -adv_options {VCCI_1.8_VOLTR:COM} -adv_options {VCCI_2.5_VOLTR:COM} -adv_options {VCCI_3.3_VOLTR:COM} -adv_options {VOLTR:COM} 
+import_files \
+         -convert_EDN_to_HDL 0 
+create_links \
+         -convert_EDN_to_HDL 0 \
+         -hdl_source {../top/diot_periph_dio/diot_periph_dio.vhd} \
+         -hdl_source {../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd}
+import_files \
+         -convert_EDN_to_HDL 0 
+create_links \
+         -convert_EDN_to_HDL 0 \
+         -pdc {../top/diot_periph_dio/diot_periph_dio.pdc} \
+         -sdc {../top/diot_periph_dio/diot_periph_dio.sdc} 
+organize_tool_files -tool {SYNTHESIZE} -file {../top/diot_periph_dio/diot_periph_dio.sdc} -module {diot_periph_dio::work} -input_type {constraint} 
+organize_tool_files -tool {COMPILE} -file {../top/diot_periph_dio/diot_periph_dio.pdc} -module {diot_periph_dio::work} -input_type {constraint} 
+organize_tool_files -tool {COMPILE} -file {../top/diot_periph_dio/diot_periph_dio.pdc} -file {../top/diot_periph_dio/diot_periph_dio.sdc} -module {diot_periph_dio::work} -input_type {constraint} 
+save_project 
--- a/hdl/top/diot_periph_dio/diot_periph_dio.pdc
+++ b/hdl/top/diot_periph_dio/diot_periph_dio.pdc
+##==== E-links banks (P2v5) ====##
+
+set_iobank Bank0 -vcci 2.50 -fixed yes
+set_iobank Bank5 -vcci 2.50 -fixed yes
+set_iobank Bank6 -vcci 2.50 -fixed yes
+set_iobank Bank7 -vcci 2.50 -fixed yes
+
+
+set_io {fmc_term_en_o[0]}   -pinname P9  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_term_en_o[1]}   -pinname G4  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_term_en_o[2]}   -pinname K1  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_term_en_o[3]}   -pinname F3  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_term_en_o[4]}   -pinname G3  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+
+set_io {fmc_oe_n[0]}   -pinname P8  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_oe_n[1]}   -pinname M3  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_oe_n[2]}   -pinname G10 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_oe_n[3]}   -pinname H1  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_oe_n[4]}   -pinname K2  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+
+set_io {fmc_p_o[0]}   -pinname N4  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_o[0]}   -pinname P4  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_o[1]}   -pinname N3  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_o[1]}   -pinname P3  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_o[2]}   -pinname N9  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_o[2]}   -pinname N8  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_o[3]}   -pinname M7  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_o[3]}   -pinname N7  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_o[4]}   -pinname B8  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_o[4]}   -pinname A8  -fixed YES -iostd LVDS -register NO
+
+set_io {fmc_p_i[0]}   -pinname N2  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_i[0]}   -pinname P2  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_i[1]}   -pinname K4  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_i[1]}   -pinname K3  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_i[2]}   -pinname H11 -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_i[2]}   -pinname J11 -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_i[3]}   -pinname L8  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_i[3]}   -pinname L9  -fixed YES -iostd LVDS -register NO
+set_io {fmc_p_i[4]}   -pinname C6  -fixed YES -iostd LVDS -register NO
+set_io {fmc_n_i[4]}   -pinname C7  -fixed YES -iostd LVDS -register NO
+
+set_io {fmc_led_top_o} -pinname H5 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {fmc_led_bot_o} -pinname J5 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+
+## I/Os assignments
+set_io {clk_25m_i}    -pinname R1  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE -schmitt_trigger OFF -in_delay OFF
+set_io {button_i}     -pinname B3  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE -schmitt_trigger OFF -in_delay OFF
+set_io {por_n_b}      -pinname T28 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE -schmitt_trigger OFF -in_delay OFF
+set_io {leds_o[0]}    -pinname AG1 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {leds_o[1]}    -pinname AB6 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {leds_o[2]}    -pinname AD2 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {leds_o[3]}    -pinname AA7 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {leds_o[4]}    -pinname AF2 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {leds_o[5]}    -pinname AE1 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+
+### Backplane I/O assignments
+# s1[0]
+set_io {slot_o[0]}    -pinname A27  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {slot_i[0]}    -pinname B26  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+# s1[1]
+set_io {slot_o[1]}    -pinname F20  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {slot_i[1]}    -pinname E20  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+# s1[2]
+set_io {slot_o[2]}    -pinname G21  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {slot_i[2]}    -pinname G20  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+# s1[4]
+set_io {slot_o[3]}    -pinname C23  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {slot_i[3]}    -pinname C22  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+# s1[5]
+set_io {slot_o[4]}    -pinname D20  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+set_io {slot_i[4]}    -pinname D19  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+
+#s1_n_b[6]
+set_io {slot_oen_i[0]}   -pinname AE26 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+#s1_n_b[7]
+set_io {slot_oen_i[1]}   -pinname AC25 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+#s1_n_b[8]
+set_io {slot_oen_i[2]}   -pinname Y23  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+#s1_n_b[9]
+set_io {slot_oen_i[3]}   -pinname AD27 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+#s1_n_b[10]
+set_io {slot_oen_i[4]}   -pinname D26  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
+
--- a/hdl/top/diot_periph_dio/diot_periph_dio.sdc
+++ b/hdl/top/diot_periph_dio/diot_periph_dio.sdc
+# Top Level Design Parameters
+
+# Clocks
+
+create_clock -name {diot_periph_dio|clk_25m_i} -period 40.000000 -waveform {0.000000 20.000000} clk_25m_i
+
+# False Paths Between Clocks
+
+
+# False Path Constraints
+
+
+# Maximum Delay Constraints
+
+
+# Multicycle Constraints
+
+
+# Virtual Clocks
+# Output Load Constraints
+# Driving Cell Constraints
+# Wire Loads
+# set_wire_load_mode top
+
+# Other Constraints
--- a/hdl/top/diot_periph_dio/diot_periph_dio.vhd
+++ b/hdl/top/diot_periph_dio/diot_periph_dio.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIOT FMC DIO for RT Demonstrator
+-- Project    : Distributed I/O Tier
+-------------------------------------------------------------------------------
+-- File       : diot_periph_dio.vhd
+-- Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2018 CERN
+--
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 0.51 (the “License”) (which enables you, at your option,
+-- to treat this file as licensed under the Apache License 2.0); you may not
+-- use this file except in compliance with the License. You may obtain a copy
+-- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity diot_periph_dio is
+  port (
+    clk_25m_i : in std_logic;
+    por_n_b   : inout std_logic;  -- Power-on-reset according to Application note AC380
+    button_i  : in std_logic;
+
+    -- FMC DIO
+    fmc_p_i  : in  std_logic_vector(4 downto 0);
+    fmc_n_i  : in  std_logic_vector(4 downto 0);
+    fmc_p_o : out std_logic_vector(4 downto 0);
+    fmc_n_o : out std_logic_vector(4 downto 0);
+    fmc_term_en_o: out std_logic_vector(4 downto 0);
+    fmc_oe_n     : out std_logic_vector(4 downto 0);
+
+    fmc_led_top_o : out std_logic;
+    fmc_led_bot_o : out std_logic;
+
+    -- backplane connections
+    slot_i   : in std_logic_vector(4 downto 0);
+    slot_o   : out std_logic_vector(4 downto 0);
+    slot_oen_i: in std_logic_vector(4 downto 0);
+
+    leds_o  : out std_logic_vector(5 downto 0)
+  );
+end diot_periph_dio;
+
+architecture rtl of diot_periph_dio is
+
+  component BIBUF_LVCMOS25
+  port (
+    pad : inout std_logic;
+    d   : in    std_logic;
+    e   : in    std_logic;
+    y   : out   std_logic);
+  end component;
+
+  component DFN1C1
+  port (
+    d   : in  std_logic;
+    clk : in  std_logic;
+    clr : in  std_logic;
+    q   : out std_logic);
+  end component;
+
+  component INBUF_LVDS
+  port (
+    padp : in  std_logic;
+    padn : in  std_logic;
+    y    : out std_logic);
+  end component;
+
+  component OUTBUF_LVDS
+  port (
+    d    : in  std_logic;
+    padp : out std_logic;
+    padn : out std_logic);
+  end component;
+
+  signal por_n_buf : std_logic;
+  signal por_n_d   : std_logic_vector(1 downto 0);
+  signal cnt       : unsigned(24 downto 0);
+  signal leds      : std_logic_vector(5 downto 0);
+  signal rst_cnt   : unsigned(15 downto 0) := (others=> '0');
+  signal rst_n     : std_logic;
+
+  signal fmc_input : std_logic_vector(4 downto 0);
+  signal fmc_output: std_logic_vector(4 downto 0);
+begin
+
+-------------------------------------------------------------------------------
+-- Power-on-reset according to Microsemi Application Note AC380
+-------------------------------------------------------------------------------
+  cmp_por_bibuf: BIBUF_LVCMOS25
+  port map (
+    pad => por_n_b,
+    d   => '0',
+    e   => '1',
+    y   => por_n_buf);
+
+  cmd_por_DFF1: DFN1C1
+  port map (
+    d   => '1',
+    clk => clk_25m_i,
+    clr => por_n_buf,
+    q   => por_n_d(0));
+
+  cmd_por_DFF2: DFN1C1
+  port map (
+    d   => por_n_d(0),
+    clk => clk_25m_i,
+    clr => por_n_buf,
+    q   => por_n_d(1));
+
+  process(clk_25m_i)
+  begin
+    if rising_edge(clk_25m_i) then
+      if (por_n_d(1) = '0' or button_i = '1') then
+        rst_cnt <= (others=>'0');
+      elsif and_reduce(std_logic_vector(rst_cnt)) /= '1' then
+        rst_cnt <= rst_cnt + 1;
+      end if;
+    end if;
+  end process;
+  rst_n <= '1' when and_reduce(std_logic_vector(rst_cnt))='1' else
+           '0';
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+  fmc_term_en_o <= (others=>'0');
+  fmc_oe_n      <= slot_oen_i;
+
+  GEN_INBUFS_I: for I in 0 to 4 generate
+    U_BUF_FMC: INBUF_LVDS
+    port map (
+      padp => fmc_p_i(I),
+      padn => fmc_n_i(I),
+      y    => fmc_input(I));
+
+    slot_o <= fmc_input;
+  end generate; 
+
+  GEN_OUTBUFS_I: for I in 0 to 4 generate
+    fmc_output <= slot_i;
+    U_BUF_BCKPL: OUTBUF_LVDS
+    port map (
+      d    => fmc_output(I),
+      padp => fmc_p_o(I),
+      padn => fmc_n_o(I));
+  end generate; 
+
+  process(clk_25m_i)
+  begin
+    if rising_edge(clk_25m_i) then
+      if rst_n = '0' then
+        cnt  <= (others=>'0');
+        leds <= "000001";
+      else
+        if cnt = to_unsigned(25000000, 25) then
+          cnt <= (others=>'0');
+          leds(5 downto 0) <= leds(4 downto 0) & leds(5);
+        else
+          cnt <= cnt + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  fmc_led_top_o <= leds(0);
+  fmc_led_bot_o <= slot_i(3);
+  GEN_LEDS_O: for I in 0 to 5 generate
+    leds_o(I) <= '0' when leds(I) = '1' else
+                 'Z';
+  end generate;
+
+-------------------------------------------------------------------------------
+
+end rtl;