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DIOT WIC Gateware
DIOT WIC Gateware
Commit 761de9ed authored by Tristan Gingold's avatar Tristan Gingold
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urv: adjust reset, wishbone port.

parent 1e965514
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hdl/rtl/urv_wic/fip_urv_regs.cheby
View file @ 761de9ed
......@@ -58,7 +58,7 @@ memory-map:
name: fip_reg
interface: wb-32-be
description: NanoFIP internal memory/registers
size: 512
size: 2k
x-hdl:
busgroup: True
- submap:
......
hdl/rtl/urv_wic/fip_urv_regs.vhd
View file @ 761de9ed
-- Do not edit. Generated on Wed Feb 05 14:47:23 2020 by tgingold
-- Do not edit. Generated on Tue Feb 11 11:36:23 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i fip_urv_regs.cheby --gen-hdl fip_urv_regs.vhd
......@@ -219,7 +219,7 @@ begin
fip_reg_o.stb <= fip_reg_tr;
fip_reg_wack <= fip_reg_i.ack and fip_reg_wt;
fip_reg_rack <= fip_reg_i.ack and fip_reg_rt;
fip_reg_o.adr <= ((22 downto 0 => '0') & adr_int(8 downto 2)) & (1 downto 0 => '0');
fip_reg_o.adr <= ((20 downto 0 => '0') & adr_int(10 downto 2)) & (1 downto 0 => '0');
fip_reg_o.sel <= wr_sel_d0;
fip_reg_o.we <= fip_reg_wt;
fip_reg_o.dat <= wr_dat_d0;
......@@ -254,51 +254,51 @@ begin
plc_mem_we <= '0';
case wr_adr_d0(13 downto 13) is
when "0" =>
case wr_adr_d0(12 downto 9) is
when "0000" =>
case wr_adr_d0(8 downto 2) is
when "0000000" =>
case wr_adr_d0(12 downto 11) is
when "00" =>
case wr_adr_d0(10 downto 2) is
when "000000000" =>
-- Reg plc_ctrl
plc_ctrl_wreq <= wr_req_d0;
wr_ack_int <= plc_ctrl_wack;
when "0000001" =>
when "000000001" =>
-- Reg fip_status
wr_ack_int <= wr_req_d0;
when "0000010" =>
when "000000010" =>
-- Reg presence
wr_ack_int <= wr_req_d0;
when "0000011" =>
when "000000011" =>
-- Reg leds
leds_wreq <= wr_req_d0;
wr_ack_int <= leds_wack;
when "0001000" =>
when "000001000" =>
-- Reg boards_pins_0
wr_ack_int <= wr_req_d0;
when "0001001" =>
when "000001001" =>
-- Reg boards_pins_1
wr_ack_int <= wr_req_d0;
when "0001010" =>
when "000001010" =>
-- Reg boards_pins_2
wr_ack_int <= wr_req_d0;
when "0001011" =>
when "000001011" =>
-- Reg boards_pins_3
wr_ack_int <= wr_req_d0;
when "0001100" =>
when "000001100" =>
-- Reg boards_pins_4
wr_ack_int <= wr_req_d0;
when "0001101" =>
when "000001101" =>
-- Reg boards_pins_5
wr_ack_int <= wr_req_d0;
when "0001110" =>
when "000001110" =>
-- Reg boards_pins_6
wr_ack_int <= wr_req_d0;
when "0001111" =>
when "000001111" =>
-- Reg boards_pins_7
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "0001" =>
when "01" =>
-- Submap fip_reg
fip_reg_we <= wr_req_d0;
wr_ack_int <= fip_reg_wack;
......@@ -322,66 +322,66 @@ begin
plc_mem_re <= '0';
case adr_int(13 downto 13) is
when "0" =>
case adr_int(12 downto 9) is
when "0000" =>
case adr_int(8 downto 2) is
when "0000000" =>
case adr_int(12 downto 11) is
when "00" =>
case adr_int(10 downto 2) is
when "000000000" =>
-- Reg plc_ctrl
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= plc_ctrl_rst_reg;
rd_dat_d0(31 downto 1) <= (others => '0');
when "0000001" =>
when "000000001" =>
-- Reg fip_status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= fip_status_var1_rdy_i;
rd_dat_d0(1) <= fip_status_var3_rdy_i;
rd_dat_d0(31 downto 2) <= (others => '0');
when "0000010" =>
when "000000010" =>
-- Reg presence
rd_ack_d0 <= rd_req_int;
rd_dat_d0(7 downto 0) <= presence_en_i;
rd_dat_d0(31 downto 8) <= (others => '0');
when "0000011" =>
when "000000011" =>
-- Reg leds
rd_ack_d0 <= rd_req_int;
rd_dat_d0(5 downto 0) <= leds_val_reg;
rd_dat_d0(31 downto 6) <= (others => '0');
when "0001000" =>
when "000001000" =>
-- Reg boards_pins_0
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_0_i;
when "0001001" =>
when "000001001" =>
-- Reg boards_pins_1
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_1_i;
when "0001010" =>
when "000001010" =>
-- Reg boards_pins_2
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_2_i;
when "0001011" =>
when "000001011" =>
-- Reg boards_pins_3
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_3_i;
when "0001100" =>
when "000001100" =>
-- Reg boards_pins_4
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_4_i;
when "0001101" =>
when "000001101" =>
-- Reg boards_pins_5
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_5_i;
when "0001110" =>
when "000001110" =>
-- Reg boards_pins_6
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_6_i;
when "0001111" =>
when "000001111" =>
-- Reg boards_pins_7
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= boards_pins_7_i;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "0001" =>
when "01" =>
-- Submap fip_reg
fip_reg_re <= rd_req_int;
rd_dat_d0 <= fip_reg_i.dat;
......
hdl/top/diot_urv_demo/diot_urv_top.vhd
View file @ 761de9ed
......@@ -49,9 +49,9 @@ entity diot_urv_top is
we_o : out std_logic;
cyc_o : out std_logic;
ack_i : in std_logic;
rst_o : out std_logic;
rst_o : out std_logic; -- Active high
-- nanoFIP control
rstin_o : out std_logic;
rstin_o : out std_logic; -- Active low
nostat_o : out std_logic;
var3_acc_o : out std_logic;
var3_rdy_i : in std_logic;
......@@ -119,7 +119,8 @@ architecture rtl of diot_urv_top is
signal por_n_buf : std_logic;
signal por_n_d : std_logic_vector(1 downto 0);
signal leds : std_logic_vector(5 downto 0);
signal rst_cnt : unsigned(15 downto 0) := (others=> '0');
subtype t_rst_cnt is natural range 0 to 15;
signal rst_cnt : t_rst_cnt;
signal rst_n : std_logic;
signal slots_in : t_wic_slot_in_array(c_SLOT_NUM-1 downto 0);
......@@ -131,7 +132,7 @@ architecture rtl of diot_urv_top is
signal wb_fip_out : t_wishbone_slave_out;
signal sel : std_logic_vector(3 downto 0);
signal unc_dat : std_logic_vector(31 downto 8);
signal unc_adr : std_logic_vector(31 downto 10);
signal unc_adr : std_logic_vector(31 downto 12);
begin
-------------------------------------------------------------------------------
......@@ -162,13 +163,13 @@ begin
begin
if rising_edge(clk_25m_i) then
if (por_n_d(1) = '0' or button_i = '1') then
rst_cnt <= x"0004"; -- (others=>'1');
elsif rst_cnt /= (15 downto 0 => '0') then
rst_cnt <= t_rst_cnt'high;
elsif rst_cnt /= 0 then
rst_cnt <= rst_cnt - 1;
end if;
end if;
end process;
rst_n <= '1' when rst_cnt = (15 downto 0 => '0') else
rst_n <= '1' when rst_cnt = 0 else
'0';
-------------------------------------------------------------------------------
......@@ -240,8 +241,8 @@ begin
fip_reg_i.stall => '0',
fip_reg_o.dat (7 downto 0) => dat_o,
fip_reg_o.dat (31 downto 8) => unc_dat,
fip_reg_o.adr (9 downto 0) => adr_o,
fip_reg_o.adr (31 downto 10) => unc_adr,
fip_reg_o.adr (11 downto 2) => adr_o,
fip_reg_o.adr (31 downto 12) => unc_adr,
fip_reg_o.cyc => cyc_o,
fip_reg_o.stb => stb_o,
fip_reg_o.sel => sel,
......@@ -256,8 +257,8 @@ begin
wclk_o <= clk_25m_i;
rst_o <= not rst_n;
nostat_o <= '0';
rstin_o <= not rst_n;
nostat_o <= '1';
rstin_o <= rst_n;
var3_acc_o <= '0';
var2_acc_o <= '0';
......
sw/diot-sw/hello/Makefile
View file @ 761de9ed
......@@ -13,6 +13,7 @@ MFIP ?= $(REPO_PARENT)
TRTL ?= $(REPO_PARENT)/mockturtle/software
# use delivered version
CFLAGS += --std=gnu99
CFLAGS += -Wall -ggdb $(DBG) -I. -I$(MFIP) -I$(MFIP)/include -I$(MFIP)/lib
CFLAGS += -D__GIT_VER__="\"$(GIT_VER)\"" -D__GIT_USR__="\"$(GIT_USR)\""
CXXFLAGS = $(CFLAGS) -std=c++11
......
sw/fip_urv/Makefile
View file @ 761de9ed
......@@ -18,6 +18,8 @@ all: $(OUTPUT).ram
fip_urv_regs.h: ../../hdl/rtl/urv_wic/fip_urv_regs.cheby
cheby --gen-c=$@ -i $<
fip_urv.o: fip_urv.c fip_urv_regs.h
%.bin: %.elf
${OBJCOPY} -O binary $< $@
......
sw/fip_urv/fip_urv.c
View file @ 761de9ed
......@@ -16,8 +16,9 @@ main (void)
while (1)
{
/* Check for FIP message. */
regs->leds = leds;
leds = ((leds << 1) & 0x3f) | ((leds >> 5) & 1);
regs->leds = (leds << 3) | (regs->fip_status & 7);
regs->fip_reg[0x102] = leds;
leds = ((leds << 1) & 0x7) | ((leds >> 2) & 1);
for (j = 0; j < 1000000; j++)
asm volatile ("nop");
}
......
sw/fip_urv/fip_urv_regs.h
View file @ 761de9ed
......@@ -50,8 +50,8 @@
#define FIP_URV_REGS_BOARDS_PINS_7 0x3cUL
/* NanoFIP internal memory/registers */
#define FIP_URV_REGS_FIP_REG 0x200UL
#define FIP_URV_REGS_FIP_REG_SIZE 512
#define FIP_URV_REGS_FIP_REG 0x800UL
#define FIP_URV_REGS_FIP_REG_SIZE 2048
/* Memory of the PLC urv */
#define FIP_URV_REGS_PLC_MEM 0x2000UL
......@@ -100,14 +100,14 @@ struct fip_urv_regs {
uint32_t pins_7;
} boards;
/* padding to: 128 words */
uint32_t __padding_1[112];
/* padding to: 512 words */
uint32_t __padding_1[496];
/* [0x200]: SUBMAP NanoFIP internal memory/registers */
uint32_t fip_reg[128];
/* [0x800]: SUBMAP NanoFIP internal memory/registers */
uint32_t fip_reg[512];
/* padding to: 2048 words */
uint32_t __padding_2[1792];
uint32_t __padding_2[1024];
/* [0x2000]: SUBMAP Memory of the PLC urv */
uint32_t plc_mem[2048];
......
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