HDL: rename temporary gefe_test to final diot_wic_demo

3af98e16 · Grzegorz Daniluk · 8d1a2d7e · 3af98e16 · 3af98e16 · 3af98e16
Commit 3af98e16 authored Nov 27, 2018 by Grzegorz Daniluk
7 changed files
--- a/README
+++ b/README
+This repository contains the sources of HDL and software for a Distributed I/O
+Tier demonstrator, with a proof-of-concept Warm Interlocks Controller
+implementation.
+* hdl/top/diot_wic_demo - is a top VHDL design file
+* sw/diot-sw/gui_demo   - is a main demonstrator GUI application running on a
+  MasterFIP computer to communicate with a DIOT crate, display diagnostics,
+  display status of WIC current loops and provide buttons to drive WIC test
+  relays.
--- a/hdl/syn/gefe_test.tcl
+++ b/hdl/syn/gefe_test.tcl
@@ -3,12 +3,12 @@
 # Date: Mon Jul 30 12:30:24 2018


-new_project -location {./gefe_test} -name {gefe_test} -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -use_enhanced_constraint_flow 0 -hdl {VHDL} -family {ProASIC3E} -die {A3PE3000} -package {896 FBGA} -speed {STD} -die_voltage {1.5} -part_range {COM} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:COM} -adv_options {VCCI_1.5_VOLTR:COM} -adv_options {VCCI_1.8_VOLTR:COM} -adv_options {VCCI_2.5_VOLTR:COM} -adv_options {VCCI_3.3_VOLTR:COM} -adv_options {VOLTR:COM} 
+new_project -location {./diot_wic_demo} -name {diot_wic_demo} -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -use_enhanced_constraint_flow 0 -hdl {VHDL} -family {ProASIC3E} -die {A3PE3000} -package {896 FBGA} -speed {STD} -die_voltage {1.5} -part_range {COM} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:COM} -adv_options {VCCI_1.5_VOLTR:COM} -adv_options {VCCI_1.8_VOLTR:COM} -adv_options {VCCI_2.5_VOLTR:COM} -adv_options {VCCI_3.3_VOLTR:COM} -adv_options {VOLTR:COM} 
 import_files \
         -convert_EDN_to_HDL 0 
 create_links \
         -convert_EDN_to_HDL 0 \
-         -hdl_source {../top/gefe_test/gefe_top.vhd} \
+         -hdl_source {../top/diot_wic_demo/diot_wic_top.vhd} \
         -hdl_source {../rtl/wic_modules/wic_pkg.vhd} \
         -hdl_source {../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd} \
         -hdl_source {../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd} \
@@ -21,9 +21,9 @@ import_files \
         -convert_EDN_to_HDL 0 
 create_links \
         -convert_EDN_to_HDL 0 \
-         -pdc {../top/gefe_test/gefe_top.pdc} \
-         -sdc {../top/gefe_test/gefe_top_sdc.sdc} 
-organize_tool_files -tool {SYNTHESIZE} -file {../top/gefe_test/gefe_top_sdc.sdc} -module {gefe_top::work} -input_type {constraint} 
-organize_tool_files -tool {COMPILE} -file {../top/gefe_test/gefe_top.pdc} -module {gefe_top::work} -input_type {constraint} 
-organize_tool_files -tool {COMPILE} -file {../top/gefe_test/gefe_top.pdc} -file {../top/gefe_test/gefe_top_sdc.sdc} -module {gefe_top::work} -input_type {constraint} 
+         -pdc {../top/diot_wic_demo/diot_wic_demo.pdc} \
+         -sdc {../top/diot_wic_demo/diot_wic_demo.sdc} 
+organize_tool_files -tool {SYNTHESIZE} -file {../top/diot_wic_demo/diot_wic_demo.sdc} -module {diot_wic_top::work} -input_type {constraint} 
+organize_tool_files -tool {COMPILE} -file {../top/diot_wic_demo/diot_wic_demo.pdc} -module {diot_wic_top::work} -input_type {constraint} 
+organize_tool_files -tool {COMPILE} -file {../top/diot_wic_demo/diot_wic_demo.pdc} -file {../top/diot_wic_demo/diot_wic_demo.sdc} -module {diot_wic_top::work} -input_type {constraint} 
 save_project 
--- a/hdl/top/diot_wic_demo/Manifest.py
+++ b/hdl/top/diot_wic_demo/Manifest.py
+files = ["diot_wic_top.vhd"];
--- a/hdl/top/gefe_test/gefe_top.pdc
+++ b/hdl/top/gefe_test/gefe_top.pdc
--- a/hdl/top/gefe_test/gefe_top_sdc.sdc
+++ b/hdl/top/gefe_test/gefe_top_sdc.sdc
@@ -2,7 +2,7 @@

 # Clocks

-create_clock -name {gefe_top|clk_25m_i} -period 40.000000 -waveform {0.000000 20.000000} clk_25m_i
+create_clock -name {diot_wic_top|clk_25m_i} -period 40.000000 -waveform {0.000000 20.000000} clk_25m_i

 # False Paths Between Clocks


--- a/hdl/top/gefe_test/gefe_top.vhd
+++ b/hdl/top/gefe_test/gefe_top.vhd
 -------------------------------------------------------------------------------
-- Title      : DIOT WIC GEFE
+-- Title      : DIOT WIC Demonstrator
 -- Project    : Distributed I/O Tier
 -------------------------------------------------------------------------------
-- File       : gefe_top.vhd
+-- File       : diot_wic_top.vhd
 -- Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
 -- Description:
-- DIOT top module with DIOT WIC. Done for first gateware tests in hardware,
-- while we are waiting for the first System Board to be produced.
+-- DIOT top module with for Warm Interlocks Controller demo.
 -------------------------------------------------------------------------------
 --
 -- Copyright (c) 2018 CERN
@@ -37,7 +36,7 @@ use work.diag_pkg.all;
 library unisim;
 use unisim.vcomponents.all;

-entity gefe_top is
+entity diot_wic_top is
  port (
    clk_25m_i : in std_logic;
    por_n_b   : inout std_logic;  -- Power-on-reset according to Application note AC380
@@ -96,9 +95,9 @@ entity gefe_top is

    leds_o  : out std_logic_vector(5 downto 0)
  );
-end gefe_top;
+end diot_wic_top;

-architecture rtl of gefe_top is
+architecture rtl of diot_wic_top is

  component BIBUF_LVCMOS25
  port (

--- a/hdl/top/gefe_test/Manifest.py
+++ b/hdl/top/gefe_test/Manifest.py
-files = ["gefe_top.vhd"];