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DIOT WIC Gateware
DIOT WIC Gateware
Commit 303b3a49 authored by Tristan Gingold's avatar Tristan Gingold
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fip_urv: adjust variable ready.

parent 761de9ed
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Showing with 178 additions and 20 deletions
hdl/rtl/urv_wic/fip_urv.vhd
View file @ 303b3a49
......@@ -97,8 +97,9 @@ begin
U_cpu_core : urv_cpu
generic map (
g_timer_frequency => 0,
g_with_hw_debug => 0,
g_with_hw_mulh => 0,
g_with_hw_mul => 0,
g_with_hw_div => 0
)
port map (
......
hdl/rtl/urv_wic/fip_urv_regs.cheby
View file @ 303b3a49
......@@ -28,6 +28,24 @@ memory-map:
- field:
name: var3_rdy
range: 1
- reg:
name: fip_var1
description: Set access to var 1
width: 32
access: rw
children:
- field:
name: acc
range: 0
- reg:
name: fip_var3
description: Set access to var 1
width: 32
access: rw
children:
- field:
name: acc
range: 0
- reg:
name: presence
description: presence lines for boards
......
hdl/rtl/urv_wic/fip_urv_regs.vhd
View file @ 303b3a49
-- Do not edit. Generated on Tue Feb 11 11:36:23 2020 by tgingold
-- Do not edit. Generated on Tue Feb 11 16:17:59 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i fip_urv_regs.cheby --gen-hdl fip_urv_regs.vhd
......@@ -23,6 +23,12 @@ entity fip_urv_regs is
fip_status_var1_rdy_i : in std_logic;
fip_status_var3_rdy_i : in std_logic;
-- Set access to var 1
fip_var1_acc_o : out std_logic;
-- Set access to var 1
fip_var3_acc_o : out std_logic;
-- presence lines for boards
presence_en_i : in std_logic_vector(7 downto 0);
......@@ -76,6 +82,12 @@ architecture syn of fip_urv_regs is
signal plc_ctrl_rst_reg : std_logic;
signal plc_ctrl_wreq : std_logic;
signal plc_ctrl_wack : std_logic;
signal fip_var1_acc_reg : std_logic;
signal fip_var1_wreq : std_logic;
signal fip_var1_wack : std_logic;
signal fip_var3_acc_reg : std_logic;
signal fip_var3_wreq : std_logic;
signal fip_var3_wack : std_logic;
signal leds_val_reg : std_logic_vector(5 downto 0);
signal leds_wreq : std_logic;
signal leds_wack : std_logic;
......@@ -168,6 +180,38 @@ begin
-- Register fip_status
-- Register fip_var1
fip_var1_acc_o <= fip_var1_acc_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fip_var1_acc_reg <= '0';
fip_var1_wack <= '0';
else
if fip_var1_wreq = '1' then
fip_var1_acc_reg <= wr_dat_d0(0);
end if;
fip_var1_wack <= fip_var1_wreq;
end if;
end if;
end process;
-- Register fip_var3
fip_var3_acc_o <= fip_var3_acc_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fip_var3_acc_reg <= '0';
fip_var3_wack <= '0';
else
if fip_var3_wreq = '1' then
fip_var3_acc_reg <= wr_dat_d0(0);
end if;
fip_var3_wack <= fip_var3_wreq;
end if;
end if;
end process;
-- Register presence
-- Register leds
......@@ -247,8 +291,10 @@ begin
plc_mem_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, plc_ctrl_wack, leds_wack, fip_reg_wack, plc_mem_wack) begin
process (wr_adr_d0, wr_req_d0, plc_ctrl_wack, fip_var1_wack, fip_var3_wack, leds_wack, fip_reg_wack, plc_mem_wack) begin
plc_ctrl_wreq <= '0';
fip_var1_wreq <= '0';
fip_var3_wreq <= '0';
leds_wreq <= '0';
fip_reg_we <= '0';
plc_mem_we <= '0';
......@@ -265,9 +311,17 @@ begin
-- Reg fip_status
wr_ack_int <= wr_req_d0;
when "000000010" =>
-- Reg fip_var1
fip_var1_wreq <= wr_req_d0;
wr_ack_int <= fip_var1_wack;
when "000000011" =>
-- Reg fip_var3
fip_var3_wreq <= wr_req_d0;
wr_ack_int <= fip_var3_wack;
when "000000100" =>
-- Reg presence
wr_ack_int <= wr_req_d0;
when "000000011" =>
when "000000101" =>
-- Reg leds
leds_wreq <= wr_req_d0;
wr_ack_int <= leds_wack;
......@@ -315,7 +369,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, plc_ctrl_rst_reg, fip_status_var1_rdy_i, fip_status_var3_rdy_i, presence_en_i, leds_val_reg, boards_pins_0_i, boards_pins_1_i, boards_pins_2_i, boards_pins_3_i, boards_pins_4_i, boards_pins_5_i, boards_pins_6_i, boards_pins_7_i, fip_reg_i.dat, fip_reg_rack, plc_mem_i.dat, plc_mem_rack) begin
process (adr_int, rd_req_int, plc_ctrl_rst_reg, fip_status_var1_rdy_i, fip_status_var3_rdy_i, fip_var1_acc_reg, fip_var3_acc_reg, presence_en_i, leds_val_reg, boards_pins_0_i, boards_pins_1_i, boards_pins_2_i, boards_pins_3_i, boards_pins_4_i, boards_pins_5_i, boards_pins_6_i, boards_pins_7_i, fip_reg_i.dat, fip_reg_rack, plc_mem_i.dat, plc_mem_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
fip_reg_re <= '0';
......@@ -337,11 +391,21 @@ begin
rd_dat_d0(1) <= fip_status_var3_rdy_i;
rd_dat_d0(31 downto 2) <= (others => '0');
when "000000010" =>
-- Reg fip_var1
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= fip_var1_acc_reg;
rd_dat_d0(31 downto 1) <= (others => '0');
when "000000011" =>
-- Reg fip_var3
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= fip_var3_acc_reg;
rd_dat_d0(31 downto 1) <= (others => '0');
when "000000100" =>
-- Reg presence
rd_ack_d0 <= rd_req_int;
rd_dat_d0(7 downto 0) <= presence_en_i;
rd_dat_d0(31 downto 8) <= (others => '0');
when "000000011" =>
when "000000101" =>
-- Reg leds
rd_ack_d0 <= rd_req_int;
rd_dat_d0(5 downto 0) <= leds_val_reg;
......
hdl/top/diot_urv_demo/diot_urv_top.vhd
View file @ 303b3a49
......@@ -133,6 +133,9 @@ architecture rtl of diot_urv_top is
signal sel : std_logic_vector(3 downto 0);
signal unc_dat : std_logic_vector(31 downto 8);
signal unc_adr : std_logic_vector(31 downto 12);
signal var1_acc, var1_rdy, var1_read : std_logic;
signal var3_acc, var3_rdy : std_logic;
begin
-------------------------------------------------------------------------------
......@@ -188,6 +191,32 @@ begin
d_i => var3_rdy_i,
q_o => var3_rdy_synced);
process (clk_25m_i, rst_n)
begin
if rising_edge(clk_25m_i) then
if rst_n = '0' then
-- Variable was not read.
var1_read <= '0';
else
if var1_rdy_synced = '0' then
-- A new value will be written.
var1_read <= '0';
elsif var1_acc = '1' then
-- Variable is (being) read.
var1_read <= '1';
end if;
end if;
end if;
end process;
-- A variable is ready if it the data are ready from nanofip and not yet read.
var1_rdy <= var1_rdy_synced and not var1_read;
var3_rdy <= var3_rdy_synced;
var1_acc_o <= var1_acc;
var3_acc_o <= var3_acc;
-------------------------------------------------------------------------------
inst_fip_urv: entity work.fip_urv
......@@ -208,8 +237,10 @@ begin
wb_i => wb_fip_in,
wb_o => wb_fip_out,
plc_ctrl_rst_o => open,
fip_status_var1_rdy_i => var1_rdy_synced,
fip_status_var3_rdy_i => var3_rdy_synced,
fip_status_var1_rdy_i => var1_rdy,
fip_status_var3_rdy_i => var3_rdy,
fip_var1_acc_o => var1_acc,
fip_var3_acc_o => var3_acc,
presence_en_i (0) => s1_en_i,
presence_en_i (1) => s2_en_i,
presence_en_i (2) => s3_en_i,
......@@ -260,9 +291,7 @@ begin
nostat_o <= '1';
rstin_o <= rst_n;
var3_acc_o <= '0';
var2_acc_o <= '0';
var1_acc_o <= '0';
p3_lgth_o <= "001"; -- 8 bytes
diag_scl_b <= 'Z';
......
sw/fip_urv/fip_urv.c
View file @ 303b3a49
......@@ -8,18 +8,50 @@ main (void)
volatile struct fip_urv_regs *regs =
(volatile struct fip_urv_regs *)0x100000;
int j;
unsigned char b;
unsigned char rdy;
/* Init. */
leds = 1;
j = 0;
rdy = 0;
/* Infinite loop. */
while (1)
{
/* Check for FIP message. */
regs->leds = (leds << 3) | (regs->fip_status & 7);
regs->fip_reg[0x102] = leds;
leds = ((leds << 1) & 0x7) | ((leds >> 2) & 1);
for (j = 0; j < 1000000; j++)
asm volatile ("nop");
unsigned int status = regs->fip_status;
regs->leds = (leds << 3) | status;
/* Send leds status. */
if (status & 1)
{
/* Received. */
/* Consume variable. */
regs->fip_var1 = 1;
b = regs->fip_reg[0x02];
rdy = 1;
regs->fip_var1 = 0;
}
if ((status & 2) && rdy)
{
/* Produce variable. */
regs->fip_var3 = 1;
regs->fip_reg[0x102] = b;
regs->fip_reg[0x103] = leds;
regs->fip_var3 = 0;
rdy = 0;
}
j++;
if (j == 1000000)
{
leds = ((leds << 1) & 0x7) | ((leds >> 2) & 1);
j = 0;
}
}
}
sw/fip_urv/fip_urv_regs.h
View file @ 303b3a49
......@@ -11,13 +11,21 @@
#define FIP_URV_REGS_FIP_STATUS_VAR1_RDY 0x1UL
#define FIP_URV_REGS_FIP_STATUS_VAR3_RDY 0x2UL
/* Set access to var 1 */
#define FIP_URV_REGS_FIP_VAR1 0x8UL
#define FIP_URV_REGS_FIP_VAR1_ACC 0x1UL
/* Set access to var 1 */
#define FIP_URV_REGS_FIP_VAR3 0xcUL
#define FIP_URV_REGS_FIP_VAR3_ACC 0x1UL
/* presence lines for boards */
#define FIP_URV_REGS_PRESENCE 0x8UL
#define FIP_URV_REGS_PRESENCE 0x10UL
#define FIP_URV_REGS_PRESENCE_EN_MASK 0xffUL
#define FIP_URV_REGS_PRESENCE_EN_SHIFT 0
/* led */
#define FIP_URV_REGS_LEDS 0xcUL
#define FIP_URV_REGS_LEDS 0x14UL
#define FIP_URV_REGS_LEDS_VAL_MASK 0x3fUL
#define FIP_URV_REGS_LEDS_VAL_SHIFT 0
......@@ -64,14 +72,20 @@ struct fip_urv_regs {
/* [0x4]: REG (ro) Status bits from NanoFIP */
uint32_t fip_status;
/* [0x8]: REG (ro) presence lines for boards */
/* [0x8]: REG (rw) Set access to var 1 */
uint32_t fip_var1;
/* [0xc]: REG (rw) Set access to var 1 */
uint32_t fip_var3;
/* [0x10]: REG (ro) presence lines for boards */
uint32_t presence;
/* [0xc]: REG (rw) led */
/* [0x14]: REG (rw) led */
uint32_t leds;
/* padding to: 8 words */
uint32_t __padding_0[4];
uint32_t __padding_0[2];
/* [0x20]: BLOCK (no description) */
struct boards {
......
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