Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
DIOT WIC Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
DIOT WIC Gateware
Commits
1a8ca7f0
Commit
1a8ca7f0
authored
May 19, 2020
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
add urv-core submodule
parent
9381b101
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
4 additions
and
0 deletions
+4
-0
.gitmodules
.gitmodules
+3
-0
urv-core
hdl/ip_cores/urv-core
+1
-0
No files found.
.gitmodules
View file @
1a8ca7f0
...
...
@@ -10,3 +10,6 @@
[submodule "sw/masterfip"]
path = sw/masterfip
url = https://gitlab.cern.ch/cohtdrivers/masterfip.git
[submodule "hdl/ip_cores/urv-core"]
path = hdl/ip_cores/urv-core
url = https://ohwr.org/project/urv-core.git
urv-core
@
f4a94d1b
Subproject commit f4a94d1bc3fa885d082b88cc9bc9e51976dd6310
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment