DI/OT Zynq Ultrascale-based System Board with White Rabbit support
Project description
The DI/OT System Board is one of the main components of the Distributed I/O Tier project ecosystem. It is designed in compliance with the Compact PCI Serial standard (CPCI-S.0) and therefore can act as a System Board in off-the-shelf CompactPCI-Serial crates.
The DI/OT System Board controls the whole DI/OT crate, communicating with up to 8 Peripheral Boards and higher layers of the control system using White Rabbit, Gigabit Ethernet or any other industrial fieldbus.
Main features and components
SoC / FPGA
Type |
Component |
How many |
Other designs |
Comments |
Zynq Ultrascale+ ZU7 |
XCZU7CG-1FFVF1517E |
1 |
AFCZ |
|
Memories
Type |
Component |
How many |
Other designs |
Comments |
PS DDR4 8Gb x4 |
MT40A512M16LY-075:E |
4 (5 with ECC) |
|
8Gb (512M x 16 x 4) |
PL DDR4 8Gb |
MT40A512M16LY-075:E |
1 |
|
8Gb (512M x 16 x 4) |
QSPI 512Mbit |
MT25QU512ABB |
1 |
7S, ZCU102 |
NOR Flash |
eMMC 32Gb |
IS21ES04G-JCLI |
1 |
7S |
4Gb x 8 |
White Rabbit support
See SPEC sch (page 2, 16) and FASEC sch (page 22) for reference
Type |
Component |
How many |
Other designs |
Comments |
SFP |
|
1 |
|
RD/TD and control signals to FPGA, no need for SFP SYNCE REFCLK like in SPEC |
Link/Act LEDs |
|
2 |
Placed close to SFP cage (probably SMDs on PCB bottom) |
|
DAC 16-bit |
AD5662BRMZ-1 |
2 |
SPEC, FASEC, AFCK, (WRS) |
|
Main OSC |
VM53S3-25.000-2.5/-30+75 |
1 |
SPEC, FASEC, AFCK, WRS |
25 MHz TCXO |
Helper OSC |
LF VCXO026156 |
1 |
SPEC, AFCK |
20 MHz |
Clock generator |
CDCM61004RHBT |
1 |
SPEC, FASEC, AFCK |
25 MHz -> 125 MHz |
|
AD9516 |
|
WRS |
25 MHz -> 125 MHz (and others, can be programmed, to allow also 10G WR?) |
|
Si5341 |
|
ZCU102, AFCZ |
|
(optional) Startup OSC |
FNETHE025 |
1 |
WRS |
|
I2C EEPROM |
24AA64T-I/MC |
1 |
FASEC, HT FMC mezzanines |
for WRPC configuration |
I2C Unique ID |
24AA025E48 |
1 |
SPEC7 |
on the same I2C bus with EEPROM |
1-PPS OUT buffers |
SN74LVT125DW |
3 |
WRS |
see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal |
ABSCAL OUT buffers |
SN74LVT125DW |
3 |
WRS |
see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal |
Other oscillators / clock generators
Type |
Component |
How many |
Other designs |
Comments |
GTH Clk generator/distribution |
e.g. Si5341 or AD9516 |
1 |
WRS, AFCZ |
Clock distribution for all GTH transceivers (WR, FMC, Backplane); UG576 (p. 30-33) 1 clk reference per Quad is enough; even 1 clk reference for multiple Quands is enough, but this is too constraining |
PS REF CLK |
48 MHz |
1 |
AFCZ |
anything between 27MHz-60MHz (DS925, p.32) |
PS RTC crystal |
32.768 kHz |
1 |
ZCU102, AFCZ |
DS925 p.33 |
?? Clock cross-point switch |
IDT 8V54816A |
1 |
AFCZ |
Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
Power
Miscellaneous
Type |
Component |
How many |
Other designs |
Comments |
12V, GND headers pads |
-- |
1 |
-- |
For external powering during first tests |
Xilinx JTAG connector |
-- |
1 |
-- |
|
Self power-cycle circuit driving backplane PS_ON# |
|
1 |
|
In normal operation PS_ON# has to be grounded, if driven high or open-circuited PSU shuts off 12V rail |
??? External watchdog chip for PL (or LPD/FPD Watchdogs inside Zynq) |
LTC2917HMS-B1#PBF |
1 |
FASEC |
|
Thermometers |
|
3? |
|
|
(optional) header connector for FPGA fan |
|
1 |
|
|
Mounting holes for FPGA heatsink |
|
|
|
|
USB UART |
|
1 |
|
|
Related links and documents
Contacts
Status
Date |
Event |
Jul-2019 |
Project starts, gathering specification |