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DIOT Zynq Ultrascale-based System Board
Wiki
Backplane gth ibert analysis
Backplane gth ibert analysis
Last edited by
Grzegorz Daniluk
May 18, 2021
Page history
All tests done with 15-bit PRBS and far-end PMA loopback at Peripheral Slot
Peripheral Slot
8Gbps
12.5Gbps
1
ibert_DIOT_SB_BSS_BP1_8Gbps
ibert_DIOT_SB_BSS_BP1_12_5Gbps
2
ibert_DIOT_SB_BSS_BP2_8Gbps
ibert_DIOT_SB_BSS_BP2_12_5Gbps
3
ibert_DIOT_SB_BSS_BP3_8Gbps
ibert_DIOT_SB_BSS_BP3_12_5Gbps
4
ibert_DIOT_SB_BSS_BP4_8Gbps
ibert_DIOT_SB_BSS_BP4_12_5Gbps
5
ibert_DIOT_SB_BSS_BP5_8Gbps
ibert_DIOT_SB_BSS_BP5_12_5Gbps
6
ibert_DIOT_SB_BSS_BP6_8Gbps
ibert_DIOT_SB_BSS_BP6_12_5Gbps
7
ibert_DIOT_SB_BSS_BP7_8Gbps
ibert_DIOT_SB_BSS_BP7_12_5Gbps
8
ibert_DIOT_SB_BSS_BP8_8Gbps
ibert_DIOT_SB_BSS_BP8_12_5Gbps
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