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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
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polygons on signal layer
#198
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
8
updated
Jul 21, 2021
[L1, L14] IC30, IC31 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
#155
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Jul 20, 2021
[General] minor impedance discontinuities - on slow LVDS improve only if possible
#162
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Minor
CLOSED
1
updated
Sep 08, 2020
[L5] DDR4 PAR signal (FPGA pin AH18), minor plane crossing with L4PWR.
#163
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Minor
CLOSED
1
updated
Sep 08, 2020
[General] Clearance to unplated holes is a bit too tight
#149
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Sep 08, 2020
boot mode function table
#211
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
3
updated
Sep 08, 2020
verify power polygons
3 of 3 tasks completed
#221
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
4
updated
Sep 08, 2020
[fpga-pl-mgts] SATA_TX vs SATAC_TX have P/N swapped!
#227
· opened
Aug 31, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Sep 08, 2020
[L14] X:124mm Y:30mm move SFP.MGT_Tx_P/N so that it lays fully over continuous GND in L13.
#228
· opened
Sep 04, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Sep 08, 2020
connect heat-sink mounting hole to GND
#196
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
7
updated
Sep 08, 2020
[L1] what is the role of pads e.g. on WR_DAC lines (DIN, SYNC1, SYNC2, SCLK)?
#174
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Question
CLOSED
2
updated
Sep 04, 2020
"mouse bites" for PCB depanelization
#203
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Minor
CLOSED
5
updated
Sep 03, 2020
[General] Xilinx BGA package delays
#4
· opened
Jan 27, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
10
updated
Sep 03, 2020
[General] what is the estimated cost of this board today excluding the FPGA price?
#170
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
1
updated
Sep 03, 2020
add ground via under DDR chips
#204
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
1
updated
Sep 02, 2020
create xsignals between DDR chips for command signal group
#195
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
2
updated
Sep 02, 2020
P1V8 power plane
#197
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Major
CLOSED
2
updated
Sep 01, 2020
[General] Impedance of differential pairs not always 100 Ohm, very thin traces (0.075mm)
#146
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
2
updated
Sep 01, 2020
various board texts
#214
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
1
updated
Aug 31, 2020
[L1] IC22, IC32 layout
3 of 3 tasks completed
#225
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 31, 2020
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