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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit a6ff71cf authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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first version sources

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sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/fpga_device.c 0 → 100644
View file @ a6ff71cf
/******************************************************************************/
/*
*
* @file fpga_device.c
*
* Functions to plot the FPGA Device info
*
******************************************************************************/
/***************************** Include Files **********************************/
#include "fpga_device.h"
/******************************** Structs *************************************/
struct command_entry commands_list_fpga_device[] = {
{ .cmd_name = "status", .cmd_func = cmd_fpga_status, .cmd_help_string = "Get all the information about FPGA convention\n", .cmd_params = "<all>"}
};
/******************************* Functions ************************************/
/******************************************************************************/
/**
* This function seach for subcommands related with FPGA information
*
******************************************************************************/
static void cmd_fpga (char *params) {
struct command_entry *entry;
char *cmd_start_p = params;
int ret;
int cmd_len;
if (!params || !(*params)) {
printf("Please provide subcommand for the Gateware command\n");
cmd_help("gateware");
return -ENOENT;
}
params = strchr(params, ' ');
if (params) {
cmd_len = params - cmd_start_p;
/* skip spaces for params */
while (*params && (*params == ' ')) {
params++;
}
} else {
cmd_len = strlen(cmd_start_p);
}
entry = commands_list_fpga_device;
while (entry && entry->cmd_name) {
if (cmd_len == strlen(entry->cmd_name) && !strncmp(entry->cmd_name, cmd_start_p, cmd_len)) {
ret = entry->cmd_func(params);
break;
}
entry++;
}
if (!(entry && entry->cmd_name)) {
printf("Commad \"%s\" not found\n", cmd_start_p);
ret = -ENOENT;
}
return ret;
}
static void cmd_fpga_status(char *params) {
/*{
struct tm build_date_s;
char name_c[9] = { [0 ... 8] = 0 };
char build_date_c[80] = { [0 ... 79] = 0 };
char git_tag_c[9] = { [0 ... 8] = 0 };
char core_id_c[4] = { [0 ... 3] = 0 };
uintptr_t auxaddr = FPGA_DEVICE_ADDR;
int fd = open("/dev/mem", O_RDWR | O_SYNC);
if (fd < 0) {
perror("Failed in Open device");
return fd;
}
uint32_t * regs_32b = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fd, auxaddr);
if (regs_32b == MAP_FAILED) {
close(fd);
perror("Failed in Mmap device");
return -2;
}
//! Read Core ID
uint32_t aux_core_id = bswap_32(regs_32b[16]);
memcpy(&core_id_c,&aux_core_id,4);
//! Read Project Name
uint64_t name_u64 = bswap_64(((uint64_t) regs_32b[18] << 32) + (uint64_t) regs_32b[17]);
memcpy(&name_c,&name_u64,8);
//! Read Build Date
time_t date = (time_t) regs_32b[19];
build_date_s = *localtime(&date);
strftime(build_date_c, sizeof(build_date_c), "%a %Y-%m-%d %H:%M:%S", &build_date_s);
//! Read String Tag
uint64_t git_tag_u64 = bswap_64(((uint64_t) regs_32b[35] << 32) + (uint64_t) regs_32b[34]);
memcpy(&git_tag_c,&git_tag_u64,8);
printf("Gateware version information:\n");
printf("VENDOR ID : %08x\n",regs_32b[0]);
printf("DEVICE ID : %08x\n",regs_32b[1]);
printf("VERSION : %08x\n",regs_32b[2]);
printf("Byte Order Map : %08x\n",regs_32b[3]);
printf("Source ID : %08x%08x%08x%08x\n",regs_32b[7],regs_32b[6],regs_32b[5],regs_32b[4]);
printf("Capability Mask : %08x\n",regs_32b[8]);
printf("UUID : %08x%08x%08x%08x\n",regs_32b[15],regs_32b[14],regs_32b[13],regs_32b[12]);
printf("IP CORE ID : %s\n",core_id_c);
printf("NAME : %s\n",name_c);
printf("BUILD DATE : %s\n",build_date_c);
printf("GIT HASH : %08x%08x%08x%08x%08x\n",regs_32b[24],regs_32b[23],regs_32b[22],regs_32b[21],regs_32b[20]);
printf("DNA : %08x%08x%08x\n",regs_32b[27],regs_32b[26],regs_32b[25]);
printf("GIT TAG : %s\n\n",git_tag_c);
close(fd);
return;
*/
printf("FPGA STATUS TO BE DONE");
return;
}
\ No newline at end of file
sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/fpga_device.h 0 → 100644
View file @ a6ff71cf
/** @file fpga_device.h
*
* @brief Library for FPGA device Convention
*
* @author alen.arias.vazquez@cern.ch
* @date 12/05/2022
* @url https://ohwr.org/project/fpga-dev-id/wikis/home
*
*/
#ifndef __FPGA_DEVICE_H
#define __FPGA_DEVICE_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files **********************************/
#include <limits.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
#include <byteswap.h>
#include <fcntl.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <errno.h>
/************************** Constant Definitions ******************************/
/***************** Macros (Inline Functions) Definitions **********************/
#define c_ADDR_VENDOR_ID 0x00
#define c_ADDR_DEVICE_ID 0x01
#define c_ADDR_VERSION 0x02
#define c_ADDR_BYTE_ORD_MARK 0x03
#define c_ADDR_SOURCE_ID_0 0x04
#define c_ADDR_SOURCE_ID_1 0x05
#define c_ADDR_SOURCE_ID_2 0x06
#define c_ADDR_SOURCE_ID_3 0x07
#define c_ADDR_CAP_MASK 0x08
#define c_ADDR_VENDOR_UUID_0 0x0C
#define c_ADDR_VENDOR_UUID_1 0x0D
#define c_ADDR_VENDOR_UUID_2 0x0E
#define c_ADDR_VENDOR_UUID_3 0x0F
#define c_ADDR_CORE_ID 0x10
#define c_ADDR_NAME_LSB 0x11
#define c_ADDR_NAME_MSB 0x12
#define c_ADDR_BUILD_T 0x13
#define c_ADDR_HASH_0 0x14
#define c_ADDR_HASH_1 0x15
#define c_ADDR_HASH_2 0x16
#define c_ADDR_HASH_3 0x17
#define c_ADDR_HASH_4 0x18
#define c_ADDR_DNA_0 0x19
#define c_ADDR_DNA_1 0x1A
#define c_ADDR_DNA_2 0x1B
#define c_ADDR_TAG_LSB 0x1C
#define c_ADDR_TAG_MSB 0x1D
#define c_ADDR_IP_CORE 0x80000000
#define c_SIZE_BYTES c_ADDR_TAG_MSB*4
/**************************** Type Definitions ********************************/
/************************** Variable Definitions ******************************/
/************************** Function Prototypes *******************************/
static void cmd_fpga (char *params);
static void cmd_fpga_status (char *params);
#ifdef __cplusplus
}
#endif
#endif /* __FPGA_DEVICE_H */
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