added RST SYNC

849d80e0 · Alén Arias Vázquez · ee881dde · 849d80e0 · 849d80e0
Commit 849d80e0 authored Oct 25, 2022 by Alén Arias Vázquez 😎
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Showing with 5 additions and 5 deletions

dna_reader.v gw/common-ip/fpga_device/src/dna_reader.v +2 -2

fpga_device.v gw/common-ip/fpga_device/src/fpga_device.v +3 -3

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--- a/gw/common-ip/fpga_device/src/dna_reader.v
+++ b/gw/common-ip/fpga_device/src/dna_reader.v
@@ -49,7 +49,7 @@ module dna_reader # (
    wire        s_data;

    //! FSM
-    always @(posedge clk_i, negedge rst_n_i)
+    always @(posedge clk_i)
    begin : p_fsm
        if(! rst_n_i) begin
            s_read <= 1'b0;
@@ -108,7 +108,7 @@ module dna_reader # (
    end : p_fsm

    //! Shift Register
-    always @(posedge clk_i, negedge rst_n_i)
+    always @(posedge clk_i)
    begin : p_shift
        if (! rst_n_i)
            s_dna <= 'h0;

--- a/gw/common-ip/fpga_device/src/fpga_device.v
+++ b/gw/common-ip/fpga_device/src/fpga_device.v
@@ -123,7 +123,7 @@ module fpga_device # (

    //--------------------------------------------------------------------------
    //! ARREADY LOGIC & ARADDR Latch
-    always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
+    always @(posedge S_AXI_ACLK)
    begin : p_arready
        if (! S_AXI_ARESETN) begin
            s_araddr  <= 'h0;
@@ -144,7 +144,7 @@ module fpga_device # (
    assign S_AXI_ARREADY = s_arready;

    //! RVALID
-    always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
+    always @(posedge S_AXI_ACLK)
    begin : p_rvalid
        if (! S_AXI_ARESETN)
            s_rvalid <= 1'b0;
@@ -161,7 +161,7 @@ module fpga_device # (
    assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;

    //! Register Access
-    always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
+    always @(posedge S_AXI_ACLK)
    begin : p_read
        if (! S_AXI_ARESETN)
            s_RDATA <= 'h0;