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DIOT Zynq Ultrascale-based System Board
Commits
66cef8d2
Commit
66cef8d2
authored
May 12, 2022
by
Alén Arias Vázquez
😎
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added TB
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2414552c
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#3653
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dna_reader_tb.sv
gw/common-ip/fpga_device/tb/dna_reader_tb.sv
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gw/common-ip/fpga_device/tb/dna_reader_tb.sv
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66cef8d2
//==============================================================================
//! @file dna_reader_tb.sv
//==============================================================================
//------------------------------------------------------------------------------
// --
// CERN - TestBench DNA Reader Xilinx FPGA --
// --
//------------------------------------------------------------------------------
//
// unit name: TestBench DNA Reader Xilinx FPGA
//
//! @brief TestBench DNA Reader Xilinx FPGA
//
//! @author alen.arias.vazquez@cern.ch
//
//! @date 12/05/2022
//
//------------------------------------------------------------------------------
module
dna_reader_tb
#
(
parameter
g_SIM_DNA_VALUE
=
96'hAABBCCDDEEFF112233445566
)
;
//! Define time units
timeunit
1
ns
;
//! Define stimulus
wire
[
95
:
0
]
s_dna
;
reg
s_clk
;
reg
s_rst_n
;
wire
s_dna_rdy
;
dna_reader
#
(
.
g_SIM_DNA_VALUE
(
g_SIM_DNA_VALUE
)
)
i_dna_reader
(
.
clk_i
(
s_clk
)
,
.
rst_n_i
(
s_rst_n
)
,
.
dna_rdy_o
(
s_dna_rdy
)
,
.
dna_o
(
s_dna
)
)
;
//! Initial block
initial
begin
:
p_initial
s_rst_n
=
1'b0
;
s_clk
=
1'b0
;
end
:
p_initial
//! Clock generator
always
begin
:
p_clock
#
5
s_clk
=
1'b1
;
#
5
s_clk
=
1'b0
;
end
:
p_clock
//! Clock generator
always
begin
:
p_rst
#
25
s_rst_n
=
1'b1
;
end
:
p_rst
//! Check Result
initial
begin
:
p_result
@
(
posedge
s_dna_rdy
)
assert
(
s_dna
==
g_SIM_DNA_VALUE
)
$
display
(
"Result is correct"
)
;
else
begin
$
error
(
"Failure in simulation"
)
;
$
error
(
"Generic value: %X"
,
g_SIM_DNA_VALUE
)
;
$
error
(
"Expecter Valuer: %X"
,
s_dna
)
;
end
end
:
p_result
endmodule
//------------------------------------------------------------------------------
//! end module
//------------------------------------------------------------------------------
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