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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 5e334670 authored by Adam Wujek's avatar Adam Wujek Committed by Adam Wujek
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sw/petalinux/fsbl: clear pin 29 (TX_DISABLE for SFP) 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent 0d2f3033
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sw/petalinux/project-spec/meta-user/recipes-bsp/fsbl/files/0001-clear-TX_DISABLE-for-SFP-gpio-29.patch 0 → 100644
View file @ 5e334670
From 25dff62774a9d7e29a69cd7e302c417c5e7935e1 Mon Sep 17 00:00:00 2001
From: Adam Wujek <dev_public@wujek.eu>
Date: Wed, 21 Jul 2021 00:02:44 +0200
Subject: [PATCH] clear TX_DISABLE for SFP (gpio 29)
Signed-off-by: Adam Wujek <dev_public@wujek.eu>
---
lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c | 42 +++++++++++++++++++++++
lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.h | 1 +
2 files changed, 43 insertions(+)
diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c
index 910139cca..cfcf366b3 100644
--- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c
+++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c
@@ -763,6 +763,47 @@ static void XFsbl_PcieReset(void)
}
#endif
#endif
+
+/*
+ * gpio_init
+ *
+ * Lower GPIO pin 29. This enables SFP (clears TX_DISABLE)
+ */
+void gpio_myplatform_init()
+{
+ uint32_t *gpio_base = (uint32_t *)(0xFF0A0000);
+ uint32_t bank = 1;
+ uint32_t *gpio_mask = (uint32_t *)(GPIO_BASEADDR + 8 * bank);
+ uint32_t *gpio_data = (uint32_t *)(GPIO_BASEADDR + 0x40 + 4 * bank);
+ uint32_t *gpio_dirm = (uint32_t *)(GPIO_BASEADDR + 0x204 + 0x40 * bank);
+ uint32_t *gpio_oen = (uint32_t *)(GPIO_BASEADDR + 0x208 + 0x40 * bank);
+ uint32_t *gpio_data_ro = (uint32_t *)(GPIO_BASEADDR + 0x60 + 4 * bank);
+ uint32_t tmp_data;
+
+ XFsbl_Printf(DEBUG_PRINT_ALWAYS,
+ "Clear gpio 29 (clear TX_DISABLE for SFP).\n\r");
+
+ /* Read the register and print it out for debugging */
+ tmp_data = *gpio_data_ro;
+ XFsbl_Printf(DEBUG_GENERAL,
+ "%s: Before: gpio%d = 0x%08p, dirm = 0x%08p, "
+ "oen = 0x%08p\r\n",
+ __FUNCTION__, bank, tmp_data, *gpio_dirm, *gpio_oen);
+
+ *gpio_dirm |= 1 << 3;
+ *gpio_oen |= 1 << 3;
+ *gpio_mask |= 1 << 3;
+
+ *gpio_data &= ~(1 << 3);
+
+ /* Read the register and print it out for debugging */
+ tmp_data = *gpio_data_ro;
+ XFsbl_Printf(DEBUG_GENERAL,
+ "%s: After: gpio%d = 0x%08p, dirm = 0x%08p, "
+ "oen = 0x%08p\r\n",
+ __FUNCTION__, bank, tmp_data, *gpio_dirm, *gpio_oen);
+}
+
/*****************************************************************************/
/**
* This function does board specific initialization.
@@ -779,6 +820,7 @@ static void XFsbl_PcieReset(void)
u32 XFsbl_BoardInit(void)
{
u32 Status;
+ gpio_myplatform_init();
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
|| defined(XPS_BOARD_ZCU104) || defined(XPS_BOARD_ZCU111)
/* Program I2C to configure GT lanes */
diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.h b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.h
index 2cc6175fa..b94741ed9 100644
--- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.h
+++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.h
@@ -196,6 +196,7 @@ typedef struct XVoutCommands {
/************************** Function Prototypes ******************************/
#endif
u32 XFsbl_BoardInit(void);
+void gpio_myplatform_init();
#ifdef __cplusplus
}
sw/petalinux/project-spec/meta-user/recipes-bsp/fsbl/fsbl_%.bbappend 0 → 100644
View file @ 5e334670
#Force to use embeddedsw repo
EXTERNALXSCTSRC = ""
EXTERNALXSCTSRC_BUILD = ""
#Patch FSBL
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += "file://0001-clear-TX_DISABLE-for-SFP-gpio-29.patch"
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