Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
DIOT Zynq Ultrascale-based System Board
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
41
Issues
41
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
DIOT Zynq Ultrascale-based System Board
Commits
30370c32
Commit
30370c32
authored
Nov 16, 2021
by
Adam Wujek
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
sw/configs/device-tree: test for 10G link, generate 156250000Hz on clk out0
Signed-off-by:
Adam Wujek
<
dev_public@wujek.eu
>
parent
2a497674
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
9 additions
and
1 deletion
+9
-1
ps-user.dtsi
sw/configs/device-tree/ps-user.dtsi
+9
-1
No files found.
sw/configs/device-tree/ps-user.dtsi
View file @
30370c32
...
...
@@ -40,6 +40,14 @@
/* fallback MAC address */
local-mac-address = [00 0a 35 00 22 01];
phy-handle = <&phy9>;
clock-names = "pixel";
clocks = <&si5341 0 0>; /* Output 0 */
/* Set output 7 to use syntesizer 3 as its parent */
assigned-clocks = <&si5341 0 0>, <&si5341 1 0>;
assigned-clock-parents = <&si5341 1 0>;
/* Set output 0 to 156.25 MHz using a synth frequency of 25 MHz */
assigned-clock-rates = <156250000>, <1250000000>;
phy9: phy@9 {
reg = <0x9>;
xlnx,phy-type = <0x5>;
...
...
@@ -106,7 +114,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
si5341@76 {
si5341
: si5341
@76 {
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment