/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include <stdio.h>
#include <string.h>
#include "platform.h"
#include "xil_printf.h"
#include "xgpiops.h"
#include "xparameters.h"
#include <xil_types.h>
#include <xiicps.h>
#include <xiicps_hw.h>
#include <xuartps_hw.h>
#include "helloworld.h"

#include "Si5341-RevD-diot_sb-Registers.h"

#define LED_DELAY		50000000
#define LED_MAX_BLINK		0x10

#define UART_BASEADDR XPAR_XUARTPS_0_BASEADDR
#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID

int shell_state;

static int reset_pl(void);
static int i2c(void);
static int shell(void);
static int pwr_cycle(XGpioPs *gpio);

int main()
{
	init_platform();

	xil_printf("Hello World\n\r");
	i2c();

	xil_printf("Si5341 config done\n\r");

	reset_pl();
	xil_printf("PL reset done\n\r");

	shell_state = SHELL_STATE_CMD;
	shell();

	xil_printf("Exiting\n\r");

	cleanup_platform();
	return 0;
}

static s32 IicPsSlaveMonitor(XIicPs *InstancePtr, u16 Address) {
	u32 Index, IntrStatusReg;
	XIicPs *IicPtr;

	IicPtr = InstancePtr;
	XIicPs_EnableSlaveMonitor(InstancePtr, Address);

	Index = 0;
	/*
	 * Wait for the Slave Monitor Status
	 */
	while (Index < 0x00FFFFFF) {
		Index++;
		/*
		 * Read the Interrupt status register.
		 */
		IntrStatusReg = XIicPs_ReadReg(IicPtr->Config.BaseAddress,
				(u32)XIICPS_ISR_OFFSET);
		if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
			XIicPs_DisableSlaveMonitor(InstancePtr);
			XIicPs_WriteReg(IicPtr->Config.BaseAddress, (u32)XIICPS_ISR_OFFSET,
					IntrStatusReg);
			return XST_SUCCESS;
		}
	}
	XIicPs_DisableSlaveMonitor(InstancePtr);
	return XST_FAILURE;
}

void i2cmux_set_channel(XIicPs *InstancePtr, uint8_t channel) {
	uint8_t buffer[4];

	buffer[0] = 1 << channel;

	XIicPs_MasterSendPolled(InstancePtr, buffer, 1, I2C_MUX_ADDR);
	while (XIicPs_BusIsBusy(InstancePtr))
		;
}

void si5341_i2c_write(XIicPs *InstancePtr, uint16_t addr, uint8_t data) {

	uint8_t buffer[4];

	buffer[0] = 0x01;
	buffer[1] = (0xFF00 & addr) >> 8;
	buffer[2] = (0x00FF & addr);
	buffer[3] = data;

	XIicPs_MasterSendPolled(InstancePtr, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(InstancePtr, &buffer[2], 2, I2C_SI5341_ADDR);
}

void si5341_dev_ready(XIicPs *InstancePtr)
{
	uint8_t buffer[4];

	buffer[0] = 0x01;
	buffer[1] = 0;
	buffer[2] = 0xFE;	//DEVICE_READY reg

	XIicPs_MasterSendPolled(InstancePtr, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(InstancePtr, &buffer[2], 1, I2C_SI5341_ADDR);
	do {
		buffer[0] = 0;
		XIicPs_MasterRecvPolled(InstancePtr, buffer, 1, I2C_SI5341_ADDR);
	} while (*buffer != 0xF);
}


void si5341_soft_rst(XIicPs *InstancePtr)
{
	uint8_t buffer[4];

	buffer[0] = 0x01;
	buffer[1] = 0;
	buffer[2] = 0x1C;	//SOFT_RST
	buffer[3] = 1;

	XIicPs_MasterSendPolled(InstancePtr, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(InstancePtr, &buffer[2], 2, I2C_SI5341_ADDR);
}

void si5341_i2c_write_nvm(XIicPs *iic) {

	uint8_t buffer[4];

	// see p13 of the reference manual Si5341-40-D-RM
	
	xil_printf("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\r");
	xil_printf("Si5341: wiriting to NVM!!!\n\r");

	// write 0xC7 to NVM_WRITE register
	buffer[0] = 0x01;
	buffer[1] = 0;
	buffer[2] = 0xE3;
	buffer[3] = 0xC7;

	XIicPs_MasterSendPolled(iic, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(iic, &buffer[2], 2, I2C_SI5341_ADDR);

	// wait until DEVICE_READY = 0x0F
	buffer[0] = 0x01;
	buffer[1] = 0;
	buffer[2] = 0xFE;
	XIicPs_MasterSendPolled(iic, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(iic, &buffer[2], 1, I2C_SI5341_ADDR);
	do {
		buffer[0] = 0;
		XIicPs_MasterRecvPolled(iic, buffer, 1, I2C_SI5341_ADDR);
	} while (*buffer != 0xF);

	// Set NVM_READ_BANK 0x00E4[0] = 1
	buffer[0] = 0x01;
	buffer[1] = 0;
	buffer[2] = 0xE4;
	buffer[4] = 1;
	XIicPs_MasterSendPolled(iic, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(iic, &buffer[2], 2,
			I2C_SI5341_ADDR);

	// wait until DEVICE_READY = 0x0F
	buffer[0] = 0x01;
	buffer[1] = 0;
	buffer[2] = 0xFE;
	XIicPs_MasterSendPolled(iic, buffer, 2, I2C_SI5341_ADDR);
	XIicPs_MasterSendPolled(iic, &buffer[2], 1,
			I2C_SI5341_ADDR);
	do {
		buffer[0] = 0;
		XIicPs_MasterRecvPolled(iic, buffer, 1, I2C_SI5341_ADDR);
	} while (*buffer != 0xF);

	xil_printf("Si5341: wiriting to NVM DONE!!!\n\r");
	xil_printf("////////////////////////////////\n\r");
}

static int i2c(void)
{
	XIicPs iic;
	XIicPs_Config *iic_config;
	int32_t status;

	/* Initialize the IIC0 driver so that it is ready to use */
	iic_config = XIicPs_LookupConfig(IIC_TEMP_ID);
	if (iic_config == NULL) {
		xil_printf("XIicPs_LookupConfig error\r\n");
		return -1;
	}

	status = XIicPs_CfgInitialize(&iic, iic_config, iic_config->BaseAddress);
	if (status != XST_SUCCESS) {
		xil_printf("XIicPs_CfgInitialize error\r\n");
		return -1;
	}

	/* Set the IIC serial clock rate */
	status = XIicPs_SetSClk(&iic, IIC_SCLK_RATE);
	if (status != XST_SUCCESS) {
		xil_printf("XIicPs_SetSClk error\r\n");
		return -1;
	}

	// check if mux is alive
	//status = IicPsSlaveMonitor(&iic, I2C_MUX_ADDR);
	//if (status == XST_SUCCESS) {
	//	xil_printf("I2C mux alive\r\n");
	//} else {
	//	xil_printf("I2C mux not alive\r\n");
	//	return -1;
	//}
//SI config
//	i2cmux_set_channel(&iic, I2C_MUX_CH_SI5341);
//
//	// send preamble
//	for (int i = 0; i < 6; i++) {
//		si5341_i2c_write(&iic, si5341_revd_registers[i].address,
//				si5341_revd_registers[i].value);
//	}
//
//	xil_printf("Si5341: preamble sent\n\r");
//
//	/* Delay 300 msec */
//	usleep(300000);
//
//	for (int i = 6; i < SI5341_REVD_REG_CONFIG_NUM_REGS; i++) {
//		si5341_i2c_write(&iic, si5341_revd_registers[i].address,
//				si5341_revd_registers[i].value);
//	}
//	xil_printf("Si5341: config sent\n\r");
//
//	/* Wait until bus is idle */
//	while (XIicPs_BusIsBusy(&iic) > 0)
//		;
//
//	/* Soft reset */
//	si5341_soft_rst(&iic);
//	usleep(300000);
//
//	/* Wait for dev ready */
//	si5341_dev_ready(&iic);
//
//SI config done

	/* Configure I2C Mux to SFP */
	i2cmux_set_channel(&iic, I2C_MUX_CH_SFP);

//GD	xil_printf("Si5341: Completed!\n\r");

}

static int board_i2c_init(XIicPs *iic, int iic_id)
{
	XIicPs_Config *iic_config;
	int32_t status;

	/* Initialize the IIC0 driver so that it is ready to use */
	iic_config = XIicPs_LookupConfig(iic_id);
	if (iic_config == NULL) {
		xil_printf("XIicPs_LookupConfig error\r\n");
		return -1;
	}

	status = XIicPs_CfgInitialize(iic, iic_config, iic_config->BaseAddress);
	if (status != XST_SUCCESS) {
		xil_printf("XIicPs_CfgInitialize error\r\n");
		return -1;
	}

	/* Set the IIC serial clock rate */
	status = XIicPs_SetSClk(iic, IIC_SCLK_RATE);
	if (status != XST_SUCCESS) {
		xil_printf("XIicPs_SetSClk error\r\n");
		return -1;
	}


	return XST_SUCCESS;
}

static int board_gpio_init(XGpioPs *gpio)
{
	XGpioPs_Config *ConfigPtr;

	ConfigPtr = XGpioPs_LookupConfig(XPAR_XGPIOPS_0_DEVICE_ID);
	if (XGpioPs_CfgInitialize(gpio, ConfigPtr, ConfigPtr->BaseAddr) != XST_SUCCESS) {;
		xil_printf("GPIO: Init failed\r\n");
		return XST_FAILURE;
	}

	XGpioPs_SetDirectionPin(gpio, EMIO_PPRES_0, 0);
	XGpioPs_SetDirectionPin(gpio, EMIO_PPRES_1, 0);

	XGpioPs_SetDirectionPin(gpio, MIO_LED2, 1);
	XGpioPs_SetDirectionPin(gpio, EMIO_PCYCLE, 1);
	XGpioPs_SetDirectionPin(gpio, EMIO_PCYCLE_STR, 1);
	XGpioPs_SetOutputEnablePin(gpio, MIO_LED2, 1);
	XGpioPs_SetOutputEnablePin(gpio, EMIO_PCYCLE, 1);

	return XST_SUCCESS;
}

int dpow(int a, int b)
{
	int i, ret;
	
	ret = 1;
	for (i=0; i<b; ++i) {
		ret *= a;
	}
	return ret;
}

static float pmbus_linear_convert(int linear)
{
	int exp, man;
	exp = ((linear & 0x8000)?-32:0) + ((linear >> 11) & 0x1f);
	man = ((linear & 0x0400)?-2048:0) + (linear & 0x7ff);
	//xil_printf("%s: lin: %x, man: %d, exp: %d\r\n", __func__, linear, man, exp);
	if (exp < 0)
		return (float)man / dpow(2, -1*exp);
	else
		return man * dpow(2, exp);
}

static float pmbus_vout_convert(int vout)
{
	int exp = -9;
	int man = vout;
	return (float)man / dpow(2, -1*exp);
}

static int diot_i2c_access(XIicPs *iic, uint8_t i2c_addr, uint8_t *buffer, int wbytes, int rbytes)
{
	XIicPs_MasterSendPolled(iic, buffer, wbytes, i2c_addr);
	XIicPs_MasterSendPolled(iic, buffer, 0, i2c_addr);
	while (XIicPs_BusIsBusy(iic) > 0);
	if (rbytes > 0) {
		XIicPs_MasterRecvPolled(iic, buffer, rbytes, i2c_addr);
		while (XIicPs_BusIsBusy(iic) > 0);
	}

	return XST_SUCCESS;
}

static int read_diag(XIicPs *temp_iic, XIicPs *psu_iic, XGpioPs *gpio)
{
	uint8_t buffer[10];
	uint8_t addrs[3] = {I2C_LM75_0_ADDR, I2C_LM75_1_ADDR, I2C_LM75_2_ADDR};
	uint8_t psu_addrs[2] = {I2C_PSU0_ADDR, I2C_PSU1_ADDR};
	int lm75_temps[3];
	int fpga_temp;
	int val;
	int i;
	int psu_id, ch_id;
	struct t_psu_diag psu_diag[2];

	xil_printf("\e[2J\e[1;1H"); // clear terminal

	i2cmux_set_channel(temp_iic, I2C_MUX_CH_THERM);

	/* Read temperature from 3 LM75 */
	for (i=0; i<3; ++i) {
		buffer[0] = 0x00;
		diot_i2c_access(temp_iic, addrs[i], buffer, 1, 1);
		lm75_temps[i] = (int) buffer[0];
	}

	/* Read temperature from MAX6639 */
	i2cmux_set_channel(temp_iic, I2C_MUX_CH_FAN);

	buffer[0] = 0x00;
	diot_i2c_access(temp_iic, I2C_MAX6639_ADDR, buffer, 1, 1);
	fpga_temp = buffer[0];

	/* Read PSUs status */
	psu_diag[0].pres = !XGpioPs_ReadPin(gpio, EMIO_PPRES_0);
	psu_diag[1].pres = !XGpioPs_ReadPin(gpio, EMIO_PPRES_1);

	/* Read PSUs diagnostics */
	for (psu_id = 0; psu_id<2; ++psu_id) {
		if (psu_diag[psu_id].pres == 0) {
			/* No PSU, don't read diagnostics */
			continue;
		}
		for (ch_id = 0; ch_id<2; ++ch_id) {
			buffer[0] = 0x00;
			buffer[1] = ch_id;
			diot_i2c_access(psu_iic, psu_addrs[psu_id], buffer, 2, 0);
			
			buffer[0] = 0x8B; //VOUT
			diot_i2c_access(psu_iic, psu_addrs[psu_id], buffer, 1, 3);
			val = (((int) buffer[1] << 8) & 0xFF00) | ((int) buffer[0] & 0x00FF);
			psu_diag[psu_id].vout[ch_id] = pmbus_vout_convert(val);

			buffer[0] = 0x8C; //IOUT
			diot_i2c_access(psu_iic, psu_addrs[psu_id], buffer, 1, 2);
			val = (((int) buffer[1] << 8) & 0xFF00) | ((int) buffer[0] & 0x00FF);
			psu_diag[psu_id].iout[ch_id] = pmbus_linear_convert(val);

			buffer[0] = 0x96; //POUT
			diot_i2c_access(psu_iic, psu_addrs[psu_id], buffer, 1, 2);
			val = (((int) buffer[1] << 8) & 0xFF00) | ((int) buffer[0] & 0x00FF);
			psu_diag[psu_id].pout[ch_id] = pmbus_linear_convert(val);
		}

		buffer[0] = 0x8D; //TEMP
		diot_i2c_access(psu_iic, psu_addrs[psu_id], buffer, 1, 2);
		val = (((int) buffer[1] << 8) & 0xFF00) | ((int) buffer[0] & 0x00FF);
		psu_diag[psu_id].temp = pmbus_linear_convert(val);
	}

	xil_printf("--------- TEMPERATURES ---------\r\n");
	xil_printf("DDR: %dC; FMC: %dC; DC/DC: %dC; FPGA: %dC      \r\n", lm75_temps[0], lm75_temps[1], lm75_temps[2], fpga_temp);
	xil_printf("-------- Power Supplies --------\r\n");
	for (psu_id=0; psu_id<2; ++psu_id) {
		xil_printf("PSU%d: %s \r\n", psu_id, psu_diag[psu_id].pres?"yes":"--not present--");
		if (psu_diag[psu_id].pres) {
			printf("\tVout: %.2f \t %.2f\r\n", psu_diag[psu_id].vout[0], psu_diag[psu_id].vout[1]);
			printf("\tIout: %.2f \t %.2f\r\n", psu_diag[psu_id].iout[0], psu_diag[psu_id].iout[1]);
			printf("\tPout: %.2f \t %.2f\r\n", psu_diag[psu_id].pout[0], psu_diag[psu_id].pout[1]);
			printf("\tTemp: %.2f \r\n", psu_diag[psu_id].temp);
		}
	}
	
	return XST_SUCCESS;
}

static int shell(void)
{
	u32 reg;
	u8 dat;
	u8 buf[80];

	//UPS XUartPs_Config *uart_cfg;
	//UPS XUartPs uart;
	XIicPs iic0, iic1;
	XGpioPs gpio;
	int status;

	xil_printf("Shell starting\n\r");

	if (board_i2c_init(&iic0, IIC_PSU_ID) != XST_SUCCESS) {
		xil_printf("Failed to initialize IIC0\r\n");
		return -1;
	}

	if (board_i2c_init(&iic1, IIC_TEMP_ID) != XST_SUCCESS) {
		xil_printf("Failed to initialize IIC1\r\n");
		return -1;
	}

	if (board_gpio_init(&gpio) != XST_SUCCESS) {
		xil_printf("Failed to initialize GPIO\r\n");
		return -1;
	}
	
	reg = XUartPs_ReadReg(UART_BASEADDR, XUARTPS_CR_OFFSET);
	XUartPs_WriteReg(UART_BASEADDR, XUARTPS_CR_OFFSET,
			((reg & ~XUARTPS_CR_EN_DIS_MASK) |
			 XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN));
	

	while (shell_state != SHELL_STATE_INACTIVE) {
		if (XUartPs_IsReceiveData(UART_BASEADDR)) {
			dat = XUartPs_ReadReg(UART_BASEADDR, XUARTPS_FIFO_OFFSET);
			switch (dat) {
				case 'p':
					pwr_cycle(&gpio);
					break;
				case 't':
					xil_printf("\r\n");
					shell_state = SHELL_STATE_TMP;
					break;
				case 'q':
					if (shell_state == SHELL_STATE_TMP) {
						shell_state = SHELL_STATE_CMD;
						xil_printf("\r\n");
					} else
						shell_state = SHELL_STATE_INACTIVE;
					break;
				default:
					XUartPs_WriteReg(UART_BASEADDR, XUARTPS_FIFO_OFFSET, dat + 1);
					break;
			}
		}
		if (shell_state == SHELL_STATE_TMP) {
			read_diag(&iic1, &iic0, &gpio);
		}
		usleep(200000);

	}

	return XST_SUCCESS;
}

static int pwr_cycle(XGpioPs *gpio)
{
	xil_printf("Power-cycling DI/OT crate\n\r");

	XGpioPs_WritePin(gpio, EMIO_PCYCLE, 0x1);
	XGpioPs_WritePin(gpio, EMIO_PCYCLE_STR, 0x0);
	XGpioPs_WritePin(gpio, EMIO_PCYCLE_STR, 0x1);
	usleep(1000);
	XGpioPs_WritePin(gpio, EMIO_PCYCLE_STR, 0x0);
	XGpioPs_WritePin(gpio, EMIO_PCYCLE, 0x0);
	XGpioPs_WritePin(gpio, EMIO_PCYCLE_STR, 0x1);
	usleep(1000);
	XGpioPs_WritePin(gpio, EMIO_PCYCLE_STR, 0x0);
	usleep(500000);

	return XST_SUCCESS;
}

//////////////////////////////////////////////////////////////////////////

#undef GPIO_MASK_DATA_5_MSW_OFFSET 
#define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
#undef GPIO_DIRM_5_OFFSET 
#define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
#undef GPIO_OEN_5_OFFSET 
#define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
#undef GPIO_DATA_5_OFFSET 
#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054

static
void PSU_Mask_Write(unsigned long offset, unsigned long mask,
	unsigned long val)
{
	unsigned long RegVal = 0x0;

	RegVal = Xil_In32(offset);
	RegVal &= ~(mask);
	RegVal |= (val & mask);
	Xil_Out32(offset, RegVal);
}

static int reset_pl(void)
{
	XGpioPs_Config *ConfigPtr;
	XGpioPs Gpio;	/* The driver instance for GPIO Device. */
	//u32 user_led = 78+95;
	u32 mio_sfp_disable = 29;
	u32 emio_rst_n = 78;
	u32 emio_led = 80;
	int status;
	int i;
	u32 Data;
	volatile int Delay;

	ConfigPtr = XGpioPs_LookupConfig(XPAR_XGPIOPS_0_DEVICE_ID);
	status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
			ConfigPtr->BaseAddr);
	if (status != XST_SUCCESS) {
		print("Reset_PL: Init failed\n\r");
		return XST_FAILURE;
	}

	XGpioPs_SetDirectionPin(&Gpio, emio_rst_n, 1);
	XGpioPs_SetDirectionPin(&Gpio, emio_led, 1);
	XGpioPs_SetDirectionPin(&Gpio, mio_sfp_disable, 1);
	XGpioPs_SetOutputEnablePin(&Gpio, emio_rst_n, 1);
	XGpioPs_SetOutputEnablePin(&Gpio, emio_led, 1);
	XGpioPs_SetOutputEnablePin(&Gpio, mio_sfp_disable, 1);

	/* Reset PL */
	XGpioPs_WritePin(&Gpio, emio_rst_n, 0x0);
	Data = XGpioPs_ReadPin(&Gpio, emio_rst_n);
	if (Data != 0 ) {
		print("Reset_PL: fail set 0\n\r");
		return XST_FAILURE;
	}

	usleep(1);

	//XGpioPs_WritePin(&Gpio, emio_rst_n, 0x1);
	//Data = XGpioPs_ReadPin(&Gpio, emio_rst_n);
	//if (Data != 1 ) {
	//	print("Reset_PL: fail reset\n\r");
	//	return XST_FAILURE;
	//}

	//usleep(1);

	/* Turn on SFP */
	XGpioPs_WritePin(&Gpio, mio_sfp_disable, 0x0);
	Data = XGpioPs_ReadPin(&Gpio, mio_sfp_disable);
	if (Data != 0 ) {
		print("SFP Enable: fail\n\r");
		return XST_FAILURE;
	}

	/* blink LED a bit */
	//for (i=0; i<10; ++i) {
	//	XGpioPs_WritePin(&Gpio, emio_led, 0x1);
	//	usleep(500000);
	//	XGpioPs_WritePin(&Gpio, emio_led, 0x0);
	//	usleep(500000);
	//}


	//PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, 0xFFFF0000U, 0x80000000U);
	//PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
	//PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
	//PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
	//usleep(1);
	//PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U);
	//usleep(1);
	//PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
}
