--==============================================================================
--! @file diot_v1_top.vhd
--==============================================================================
--------------------------------------------------------------------------------
-- --
-- CERN - DIOT V1 --
-- --
--------------------------------------------------------------------------------
--
-- unit name:  diot_v1_top
--
--! @brief top level DIOT system board Version 1 based in ZynqMP+
--
--! @author alen.arias.vazquez@cern.ch
--
--! @date 05/04/2022
--
--------------------------------------------------------------------------------

library ieee;
library unisim;

use ieee.std_logic_1164.all;
use unisim.vcomponents.all;

--==============================================================================
--! Entity declaration for diot_v1_top
--==============================================================================
entity diot_v1_top is
    port (
        emio_i2c_scl        : inout std_logic_vector(0 downto 0);
        emio_i2c_sda        : inout std_logic_vector(0 downto 0);
        M_SCL_0             : inout std_logic_vector(0 downto 0);
        M_SDA_0             : inout std_logic_vector(0 downto 0);
        wrflash_scl         : inout std_logic_vector(0 downto 0);
        wrflash_sda         : inout std_logic_vector(0 downto 0);
        gtrefclk_in_clk_n   : in std_logic;
        gtrefclk_in_clk_p   : in std_logic;
        link_status_led     : out std_logic_vector(0 downto 0);
        link_sync_led       : out std_logic_vector(0 downto 0);
        mdc_clk_led         : out std_logic_vector(0 downto 0);
        pl_reset_led        : out std_logic;
        p_pres_i_0          : in std_logic_vector(1 downto 0);
        pwr_cycle_req_o_0   : out std_logic;
        bckpl_servmod_b     : inout std_logic_vector(7 downto 0);
        bckpl_rst_n_o       : out std_logic;
        bckpl_scl           : inout std_logic;
        bckpl_sda           : inout std_logic;
        psu_alert_i         : in std_logic;
        f_rst               : inout std_logic;
        sfp_rxn             : in std_logic;
        sfp_rxp             : in std_logic;
        sfp_txn             : out std_logic;
        sfp_txp             : out std_logic;
        clk_src_sel_o       : out std_logic_vector(1 downto 0)
    );
end diot_v1_top;

--==============================================================================
--! Architecture declaration
--==============================================================================
architecture structure of diot_v1_top is

    component diot_v1 is
        port (
            link_status_led     : out std_logic_vector(0 downto 0);
            link_sync_led       : out std_logic_vector(0 downto 0);
            mdc_clk_led         : out std_logic_vector(0 downto 0);
            emio_i2c_sda        : inout std_logic_vector(0 downto 0);
            emio_i2c_scl        : inout std_logic_vector(0 downto 0);
            M_SDA_0             : inout std_logic_vector(0 downto 0);
            M_SCL_0             : inout std_logic_vector(0 downto 0);
            wrflash_scl         : inout std_logic_vector(0 downto 0);
            wrflash_sda         : inout std_logic_vector(0 downto 0);
            pl_reset_led        : out std_logic;
            gtrefclk_in_clk_n   : in std_logic;
            gtrefclk_in_clk_p   : in std_logic;
            p_pres_i_0          : in std_logic_vector(1 downto 0);
            pwr_cycle_req_o_0   : out std_logic;
            bckpl_servmod_b     : inout std_logic_vector(7 downto 0);
            bckpl_rst_n_o       : out std_logic;
            bckpl_scl           : inout std_logic_vector(0 downto 0);
            bckpl_sda           : inout std_logic_vector(0 downto 0);
            psu_alert_i         : in  std_logic;
            f_rst               : inout std_logic_vector(0 downto 0);
            sfp_rxn             : in std_logic;
            sfp_rxp             : in std_logic;
            sfp_txn             : out std_logic;
            sfp_txp             : out std_logic;
            clk_src_sel_o       : out std_logic_vector(1 downto 0)
        );
    end component diot_v1;

--==============================================================================
--! Architecture begin
--==============================================================================
begin

    design_1_i: component diot_v1
        port map (
            emio_i2c_scl(0)     => emio_i2c_scl(0),
            emio_i2c_sda(0)     => emio_i2c_sda(0),
            M_SCL_0(0)          => M_SCL_0(0),
            M_SDA_0(0)          => M_SDA_0(0),
            wrflash_scl(0)      => wrflash_scl(0),
            wrflash_sda(0)      => wrflash_sda(0),
            gtrefclk_in_clk_n   => gtrefclk_in_clk_n,
            gtrefclk_in_clk_p   => gtrefclk_in_clk_p,
            link_status_led(0)  => link_status_led(0),
            link_sync_led(0)    => link_sync_led(0),
            mdc_clk_led(0)      => mdc_clk_led(0),
            pl_reset_led        => pl_reset_led,
            p_pres_i_0          => p_pres_i_0,
            pwr_cycle_req_o_0   => pwr_cycle_req_o_0,
            bckpl_servmod_b     => bckpl_servmod_b,
            bckpl_rst_n_o       => bckpl_rst_n_o,
            bckpl_scl(0)        => bckpl_scl,
            bckpl_sda(0)        => bckpl_sda,
            psu_alert_i         => psu_alert_i,
            f_rst(0)            => f_rst,
            sfp_rxn             => sfp_rxn,
            sfp_rxp             => sfp_rxp,
            sfp_txn             => sfp_txn,
            sfp_txp             => sfp_txp,
            clk_src_sel_o       => clk_src_sel_o
        );

end architecture structure;
--==============================================================================
-- architecture end
--==============================================================================

