Milestone expired on Nov 11, 2020
Unstarted Issues (open and unassigned)
Ongoing Issues (open and assigned)
Completed Issues (closed)
- Power Bank 2 with 3.3V and get rid of a bunch of level shifters
- According to UG0451 the VPUMP pin should be left open at the JTAG connector
- R6 and R7 on the Input of LT3083 (IC2)
- FPGA pin U16 should be connected on Brown out circuit.
- FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled
- Monitoring: ATSAMD21G18 is known to freeze in radiation, we should also have a power cycle/reset line from FPGA
- Connect DEVRST_N to PGOOD.P1V2
- Fix JTAG pull-down and DEVRST_N pull-up values
- Go through the design checklist in AC393
- FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
- CPCI-S_Backplane_P1-P3: some signals missing ESD protection
- P12V fuse
- wrong backplane P5 connector pinout (J5F)
- Harness type
- Constrain_Periph_Nets: length matching for LVDS_17 quite loose
- Translate_2V5_to_PPERIPH: SERVMOD_DIR pulled-up multiple times
- Fit two lines / level shifter for SERVMOD
- Add a pin header for a possible monitoring expansion board
- IC14 analog domain issues
- IC2 Configuration and VCONTROL pin
- Missing pull resistors on SN74LVC2T45
- Missing pull ups on TMS and TDI lines
- Filtering on the outputs of OPA192
- ESD strips and nets are floating.
- Issues on TPS7A (IC5 and IC4)
- 2 types of 10uF Capacitors
- 330uF Capacitor is used only once
- CMS Vishay Y14870R05000B9R availability is limited
- Change the capacitor tying GND to CHASSIS with one of a higher voltage rating
- I'd add I2C/SPI I/O expander to encode with resistor net version of the board and some unique ID chip.
- Translate_GPIO_to_2V5: more uniform translation circuits
- Top_Misc: STRIP3 shall be also connected to the front panel i.e. CHASSIS net
- CPCI-S_Backplane_P4-P6: add note that LVDS_17_P/N from all slots shall be length matched
- Fiducial targets
- OPA192 power supply
- 12V input power connector
- CPCI-S_Backplane_P1-P3: add series current limiting resistors (small value) together with ESD protection diodes
- current sense opamps
- Isolation resistors on opamp driving ADC input
- pull-down on LED's transistors
- Comments about ERC settings
- FMC: add a note saying which LA_D are connected to FPGA differential-capable bank, it's not all of them
- FPGA_Banks_1_2: add a note next to Bank1 saying it cannot handle LVDS therefore swapping signals with other banks shall be avoided
- Top_Misc: R171 should be not mounted
- Translate_2V5_to_PPERIPH: SHARED_BUS0..4 shall be puled up on System Board so that they can be used as multi-drop lines e.g. for IRQs
- Does FEAST need filtering to comply with EN 55022 class a or b directives?
- What is the startegy for current sense and voltage monitoring?
- FPGA Pin D24 is not an I/O.
- FMC net naming does not follow _P _N naming convention
- P connectors index should also include what is decided to be used within DIOT functionality
- Colouring of harness, wires, comments should take into account accessibility for color vision deficiency
- Maybe add a Power-up sequence diagram?
- Jtag Chain needs a block diagram for visualization
- Explanatory heading is missing from some design shcematic pages.
- Use one sheet symbol and schematic for each connector and/or FPGA Banks
- Unify harness representation in schematics
- Net Identifier scope and Hierarcy
- relicense to CERN-OHL-W v2
- aligning net labels
- FPGA_Banks_6_7: connecting FMC clocks
- FPGA_Banks_6_7: I guess we don't need the filter circuit for SERDES_0_L23_*
- Powering: Do we need 12V brownout detection circuit?
- FPGA decoupling capacitors on dedicated sheet
- MoniMod reset
- backplane signal names
- Power dissipation IC4