Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
DIOT Igloo2-based radiation-tolerant System Board
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
DIOT Igloo2-based radiation-tolerant System Board
Issues
Open
0
Closed
14
All
14
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
Power Bank 2 with 3.3V and get rid of a bunch of level shifters
#61
· opened
Nov 11, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 11, 2020
According to UG0451 the VPUMP pin should be left open at the JTAG connector
#59
· opened
Nov 06, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 06, 2020
R6 and R7 on the Input of LT3083 (IC2)
#58
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
FPGA pin U16 should be connected on Brown out circuit.
#49
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled
#28
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Monitoring: ATSAMD21G18 is known to freeze in radiation, we should also have a power cycle/reset line from FPGA
#26
· opened
Oct 26, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
5
updated
Nov 12, 2020
Connect DEVRST_N to PGOOD.P1V2
#24
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 05, 2020
Fix JTAG pull-down and DEVRST_N pull-up values
#23
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Go through the design checklist in AC393
#22
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 13, 2020
FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
#20
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Nov 09, 2020
CPCI-S_Backplane_P1-P3: some signals missing ESD protection
2 of 3 tasks completed
#18
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Oct 27, 2020
P12V fuse
#14
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
wrong backplane P5 connector pinout (J5F)
#10
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
1
updated
Nov 04, 2020
Harness type
#7
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
critical
CLOSED
0
updated
Nov 03, 2020