Issues · Projects / DIOT Igloo2-based radiation-tolerant System Board · Open Hardware Repository

Wrong pull ups at voltage translators (IC7)

#69 · opened Dec 14, 2020 by Volker Schramm layout v1.0 Dec 18, 2020 critical
- 1
updated Dec 14, 2020
Power Bank 2 with 3.3V and get rid of a bunch of level shifters

#61 · opened Nov 11, 2020 by Christos Gentsos sch v1.0 critical
- CLOSED
- 1
updated Nov 11, 2020
According to UG0451 the VPUMP pin should be left open at the JTAG connector

#59 · opened Nov 06, 2020 by Christos Gentsos sch v1.0 critical
- CLOSED
- 0
updated Nov 06, 2020
R6 and R7 on the Input of LT3083 (IC2)

#58 · opened Nov 05, 2020 by Spyridon Georgakakis sch v1.0 critical
- CLOSED
- 1
updated Nov 05, 2020
FPGA pin U16 should be connected on Brown out circuit.

#49 · opened Nov 05, 2020 by Spyridon Georgakakis sch v1.0 critical
- CLOSED
- 1
updated Nov 05, 2020
FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled

#28 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 critical
- CLOSED
- 1
updated Nov 03, 2020
Monitoring: ATSAMD21G18 is known to freeze in radiation, we should also have a power cycle/reset line from FPGA

#26 · opened Oct 26, 2020 by Grzegorz Daniluk sch v1.0 critical
- CLOSED
- 5
updated Nov 12, 2020
Connect DEVRST_N to PGOOD.P1V2

#24 · opened Oct 23, 2020 by Christos Gentsos sch v1.0 critical
- CLOSED
- 0
updated Nov 05, 2020
Fix JTAG pull-down and DEVRST_N pull-up values

#23 · opened Oct 23, 2020 by Christos Gentsos sch v1.0 critical
- CLOSED
- 1
updated Nov 03, 2020
Go through the design checklist in AC393

#22 · opened Oct 23, 2020 by Christos Gentsos sch v1.0 critical
- CLOSED
- 1
updated Nov 13, 2020
FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL

#20 · opened Oct 23, 2020 by Grzegorz Daniluk sch v1.0 critical
- CLOSED
- 2
updated Nov 09, 2020
CPCI-S_Backplane_P1-P3: some signals missing ESD protection 2 of 3 tasks completed

#18 · opened Oct 23, 2020 by Grzegorz Daniluk sch v1.0 critical
- CLOSED
- 2
updated Oct 27, 2020
P12V fuse

#14 · opened Oct 23, 2020 by Paul PERONNARD sch v1.0 critical
- CLOSED
- 1
updated Nov 05, 2020
wrong backplane P5 connector pinout (J5F)

#10 · opened Oct 23, 2020 by Grzegorz Daniluk sch v1.0 critical
- CLOSED
- 1
updated Nov 04, 2020
power cycle pulse generator

#9 · opened Oct 23, 2020 by Paul PERONNARD layout v1.0 critical
- 0
updated Nov 16, 2020
Harness type

#7 · opened Oct 23, 2020 by Paul PERONNARD sch v1.0 critical
- CLOSED
- 0
updated Nov 03, 2020
Capacitor V-Ratings

#1 · opened Oct 13, 2020 by Volker Schramm layout v1.0 critical
- 1
updated Nov 16, 2020