Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
DIOT Igloo2-based radiation-tolerant System Board
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
6
Issues
6
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
DIOT Igloo2-based radiation-tolerant System Board
Issues
Open
0
Closed
66
All
66
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
FMC: add a note saying which LA_D are connected to FPGA differential-capable bank, it's not all of them
#68
· opened
Nov 16, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
1
updated
Nov 16, 2020
Constrain_Periph_Nets: length matching for LVDS_17 quite loose
#67
· opened
Nov 16, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
2
updated
Nov 16, 2020
FPGA_Banks_1_2: add a note next to Bank1 saying it cannot handle LVDS therefore swapping signals with other banks shall be avoided
#66
· opened
Nov 16, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
3
updated
Nov 16, 2020
Top_Misc: R171 should be not mounted
#65
· opened
Nov 13, 2020
by
Grzegorz Daniluk
sch v1.0
CLOSED
0
updated
Nov 13, 2020
Translate_2V5_to_PPERIPH: SHARED_BUS0..4 shall be puled up on System Board so that they can be used as multi-drop lines e.g. for IRQs
#64
· opened
Nov 13, 2020
by
Grzegorz Daniluk
sch v1.0
CLOSED
0
updated
Nov 13, 2020
Translate_2V5_to_PPERIPH: SERVMOD_DIR pulled-up multiple times
#63
· opened
Nov 13, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
1
updated
Nov 13, 2020
Fit two lines / level shifter for SERVMOD
#62
· opened
Nov 12, 2020
by
Christos Gentsos
sch v1.0
minor
CLOSED
0
updated
Nov 12, 2020
Power Bank 2 with 3.3V and get rid of a bunch of level shifters
#61
· opened
Nov 11, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 11, 2020
Add a pin header for a possible monitoring expansion board
#60
· opened
Nov 11, 2020
by
Christos Gentsos
sch v1.0
minor
CLOSED
0
updated
Nov 11, 2020
According to UG0451 the VPUMP pin should be left open at the JTAG connector
#59
· opened
Nov 06, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 06, 2020
R6 and R7 on the Input of LT3083 (IC2)
#58
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
IC14 analog domain issues
#57
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
2
updated
Nov 12, 2020
IC2 Configuration and VCONTROL pin
#56
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
2
updated
Nov 12, 2020
Does FEAST need filtering to comply with EN 55022 class a or b directives?
#55
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
question
CLOSED
3
updated
Nov 10, 2020
What is the startegy for current sense and voltage monitoring?
#54
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
question
CLOSED
2
updated
Nov 09, 2020
Missing pull resistors on SN74LVC2T45
#53
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
5
updated
Nov 11, 2020
Missing pull ups on TMS and TDI lines
#52
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
4
updated
Nov 10, 2020
Filtering on the outputs of OPA192
#51
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
3
updated
Nov 05, 2020
ESD strips and nets are floating.
#50
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
minor
CLOSED
1
updated
Nov 05, 2020
FPGA pin U16 should be connected on Brown out circuit.
#49
· opened
Nov 05, 2020
by
Spyridon Georgakakis
sch v1.0
critical
CLOSED
1
updated
Nov 05, 2020
Prev
1
2
3
4
Next