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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
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LC filter layout can be improved
#123
· opened
May 21, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
0
updated
May 21, 2021
P2V5_A rail is unused, it has to be removed
#122
· opened
May 20, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
0
updated
May 21, 2021
Different kind of Vias...
#120
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 19, 2021
Stack Up Layer Legend does not match the stack up
#119
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
Board guide
#118
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 19, 2021
C102 not directly connected to IC22
#117
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
C180 is placed Under FPGA and not IC32
#116
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 19, 2021
IC27 : Decoupling capacitor placed on wrong pin
#115
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
MONIMOD I2C lines close to monitoring signals
#114
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
Stray Lines and Via on FMC-JTAG.TMS line
#113
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 18, 2021
DC blocking caps routing
#112
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
Missing return vias (GND Vias) on serdes signals
#111
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
Placement of SERDES resistor and decoupling cap.
#110
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
Skew compensation
#109
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
Vias sharing and decoupling caps net width
#108
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 21, 2021
Stray line on SD_PLL_VSSA
#107
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
Routing of VDDPLL and PLLVSSA should be done with Planes not traces
#106
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 21, 2021
Decoupling Caps for FPGA are using Vias on Pads that are not Capped and Filled.
#105
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
Stray track on PPERIPH net and Keep out region
#104
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
Acid Traps
#103
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
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