Commit d7be1c2b authored by Christos Gentsos's avatar Christos Gentsos

Improve peripheral board diff. pair length matching rules

parent 14e7d6a5
......@@ -28,7 +28,7 @@ DItemRevisionGUID=
ReportSuppressedErrorsInMessages=0
FSMCodingStyle=eFMSDropDownList_OneProcess
FSMEncodingStyle=eFMSDropDownList_OneHot
OutputPath=
OutputPath=Project Outputs for DIOT-sb-igl
LogFolderPath=
ManagedProjectGUID=
IncludeDesignInRelease=0
......@@ -530,6 +530,40 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=VWSCYIBF
[Document30]
DocumentPath=Schematics\Constrain_Periph_Nets.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=ERSNRNPT
[Document31]
DocumentPath=Schematics\Constrain_Periph_Nets.Harness
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[GeneratedDocument1]
DocumentPath=Project Outputs for DIOT-sb-igl\BGA Escape Route - DIOT-sb-igl_pcb.html
DItemRevisionGUID=
......@@ -703,7 +737,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
SaveSettingsToOutJob=-1
[Generic_EDE]
OutputDir=
OutputDir=Project Outputs for DIOT-sb-igl
[OutputGroup1]
Name=Netlist Outputs
......
......@@ -7,6 +7,7 @@ Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=JTAG|SchDesi
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Monitoring|SchDesignator=Monitoring|FileName=Monitoring.SchDoc|SymbolType=Normal|RawFileName=Monitoring.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Powering|SchDesignator=Powering|FileName=Powering.SchDoc|SymbolType=Normal|RawFileName=Powering.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Top_Misc|SchDesignator=Top_Misc|FileName=Top_Misc.SchDoc|SymbolType=Normal|RawFileName=Top_Misc.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Constrain Peripheral Board Nets|SchDesignator=Constrain Peripheral Board Nets|FileName=Constrain_Periph_Nets.SchDoc|SymbolType=Normal|RawFileName=Constrain_Periph_Nets.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 0,3,5,8|SchDesignator=FPGA Banks 0,3,5,8|FileName=FPGA_Banks_0_3_5_8.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_0_3_5_8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 1,2|SchDesignator=FPGA Banks 1,2|FileName=FPGA_Banks_1_2.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_1_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 6,7|SchDesignator=FPGA Banks 6,7|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
......
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PERIPH_CONN=LVDS_0_P,LVDS_0_N,LVDS_1_P,LVDS_1_N,LVDS_2_P,LVDS_2_N,LVDS_3_P,LVDS_3_N,LVDS_4_P,LVDS_4_N,LVDS_5_P,LVDS_5_N,LVDS_6_P,LVDS_6_N,LVDS_7_P,LVDS_7_N,LVDS_8_P,LVDS_8_N,LVDS_9_P,LVDS_9_N,LVDS_10_P,LVDS_10_N,LVDS_11_P,LVDS_11_N,LVDS_12_P,LVDS_12_N,LVDS_13_P,LVDS_13_N,LVDS_14_P,LVDS_14_N,LVDS_15_P,LVDS_15_N,LVDS_16_P,LVDS_16_N,LVDS_17_P,LVDS_17_N
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