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DIOT Igloo2-based radiation-tolerant System Board
DIOT Igloo2-based radiation-tolerant System Board
Commit c51efb25 authored by Christos Gentsos's avatar Christos Gentsos
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Rename nets for clarity, connect SYSEN_N to FPGA, add TVS

parent 0eabb86b
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hw/DIOT-sb-igl.PrjPcbStructure
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......@@ -22,11 +22,11 @@ Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD6|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD7|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD8|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=CRT-GPIO I2C Translation|SchDesignator=CRT-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus1|SchDesignator=REPEAT(Voltage_trans_sharedbus,1,4)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus2|SchDesignator=REPEAT(Voltage_trans_sharedbus,1,4)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus3|SchDesignator=REPEAT(Voltage_trans_sharedbus,1,4)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus4|SchDesignator=REPEAT(Voltage_trans_sharedbus,1,4)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Translate GPIO voltage|SchDesignator=Translate GPIO voltage|FileName=Translate_GPIO_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_GPIO_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Translate GPIO voltages|SchDesignator=Translate GPIO voltages|FileName=Translate_GPIO_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_GPIO_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus0|SchDesignator=Voltage_trans_sharedbus0|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=CRT-GPIO I2C Translation|SchDesignator=CRT-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=SB-GPIO I2C Translation|SchDesignator=SB-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation|SchDesignator=MON-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hw/DIOT-sb-igl.pdf
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hw/Schematics/CPCI-S_Backplane_P1-P3.Harness
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CRT-GPIO={I2C:I2C},RST_N,PRST_N,PWRBTN_N,PWR_FAIL_N
CRT-GPIO=PRST_N,PWRBTN_N
I2C=SCL,SDA
SB-GPIO={I2C:I2C},P_RST_N,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST_N,F_IO0,F_IO1
MON-GPIO={I2C:I2C},P_RST_N,P_IO0,P_IO1,P_IO2,F_RST_N,F_IO0,F_IO1,PWR_FAIL_N,PSU_PRES0,PSU_PRES1
hw/Schematics/FPGA_Banks_1_2.Harness
View file @ c51efb25
FMC-LA=D_N[33..0],D_P[33..0]
FMC-SIGS=PRSNT,{I2C:I2C},{LA:FMC-LA}
I2C=SCL,SDA
SPI=SS_N,SCLK,MOSI,MISO
hw/Schematics/FPGA_Banks_6_7.Harness
View file @ c51efb25
FMC-CLKS=CLK0_M2C_P,CLK0_M2C_N,CLK1_M2C_P,CLK1_M2C_N
MGT=GBTCLK_M2C_P,GBTCLK_M2C_N,DP_M2C_N,DP_M2C_P,DP_C2M_N,DP_C2M_P
SPI=SS_N,SCLK,MOSI,MISO
hw/Schematics/Translate_GPIO_to_2V5.Harness
View file @ c51efb25
CRT-GPIO={I2C:I2C},RST_N,PRST_N,PWRBTN_N,PWR_FAIL_N
I2C=SCL,SDA
SB-GPIO={I2C:I2C},P_RST_N,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST_N,F_IO0,F_IO1
MON-GPIO={I2C:I2C},P_RST_N,P_IO0,P_IO1,P_IO2,F_RST_N,F_IO0,F_IO1,PWR_FAIL_N,PSU_PRES0,PSU_PRES1
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