Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
DIOT Igloo2-based radiation-tolerant System Board
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
7
Issues
7
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
DIOT Igloo2-based radiation-tolerant System Board
Commits
8bbef201
Commit
8bbef201
authored
Nov 11, 2020
by
Christos Gentsos
1
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Split the I2C level translator into two generic ones
parent
fbf0d1c7
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
12 additions
and
5 deletions
+12
-5
DIOT-sb-igl.PrjPcb
hw/DIOT-sb-igl.PrjPcb
+1
-1
DIOT-sb-igl.PrjPcbStructure
hw/DIOT-sb-igl.PrjPcbStructure
+11
-4
FPGA_Banks_1_2.SchDoc
hw/Schematics/FPGA_Banks_1_2.SchDoc
+0
-0
Translate_GPIO_to_2V5.SchDoc
hw/Schematics/Translate_GPIO_to_2V5.SchDoc
+0
-0
Translate_OD_3V3_to_2V5.SchDoc
hw/Schematics/Translate_OD_3V3_to_2V5.SchDoc
+0
-0
No files found.
hw/DIOT-sb-igl.PrjPcb
View file @
8bbef201
...
...
@@ -514,7 +514,7 @@ GenerateClassCluster=0
DocumentUniqueId=
[Document29]
DocumentPath=Schematics\Translate_
3V3_I2C
_to_2V5.SchDoc
DocumentPath=Schematics\Translate_
OD_3V3
_to_2V5.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=1
...
...
hw/DIOT-sb-igl.PrjPcbStructure
View file @
8bbef201
...
...
@@ -13,9 +13,12 @@ Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 1,2|SchDesig
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 6,7|SchDesignator=FPGA Banks 6,7|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Config|SchDesignator=FPGA Config|FileName=FPGA_Config.SchDoc|SymbolType=Normal|RawFileName=FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Power|SchDesignator=FPGA Power|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=CRT-GPIO I2C Translation|SchDesignator=CRT-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=FMC I2C Translation|SchDesignator=FMC I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=MoniMod I2C Translation|SchDesignator=MoniMod I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Backplane I2C Translation - SCL|SchDesignator=Backplane I2C Translation - SCL|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Backplane I2C Translation - SDA|SchDesignator=Backplane I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=FMC I2C Translation - SCL|SchDesignator=FMC I2C Translation - SCL|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=FMC I2C Translation - SDA|SchDesignator=FMC I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=MoniMod I2C Translation - SCL|SchDesignator=MoniMod I2C Translation - SCL|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=MoniMod I2C Translation - SDA|SchDesignator=MoniMod I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD1|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD2|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD3|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
...
...
@@ -30,4 +33,8 @@ Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_sharedbus4|SchDesignator=REPEAT(Voltage_trans_sharedbus,1,4)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Translate GPIO voltages|SchDesignator=Translate GPIO voltages|FileName=Translate_GPIO_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_GPIO_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_sharedbus0|SchDesignator=Voltage_trans_sharedbus0|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation|SchDesignator=MON-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation - SCL|SchDesignator=MON-GPIO I2C Translation - SCL|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation - SDA|SchDesignator=MON-GPIO I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation - SDA|SchDesignator=MON-GPIO I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation - SDA|SchDesignator=MON-GPIO I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=MON-GPIO I2C Translation - SDA|SchDesignator=MON-GPIO I2C Translation - SDA|FileName=Translate_OD_3V3_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_OD_3V3_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hw/Schematics/FPGA_Banks_1_2.SchDoc
View file @
8bbef201
No preview for this file type
hw/Schematics/Translate_GPIO_to_2V5.SchDoc
View file @
8bbef201
No preview for this file type
hw/Schematics/Translate_
3V3_I2C
_to_2V5.SchDoc
→
hw/Schematics/Translate_
OD_3V3
_to_2V5.SchDoc
View file @
8bbef201
No preview for this file type
Christos Gentsos
@cgentsos
mentioned in issue
#27 (closed)
·
Nov 11, 2020
mentioned in issue
#27 (closed)
mentioned in issue #27
Toggle commit list
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
