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DIOT Igloo2-based radiation-tolerant System Board
DIOT Igloo2-based radiation-tolerant System Board
Commit 54efb6a7 authored by Christos Gentsos's avatar Christos Gentsos
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Add CRT I2C, redundant PWR_CYC; fix MoniMod supply, few cap ratings

parent 53d94fb7
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Showing with 69 additions and 4 deletions
hw/DIOT-sb-igl.PrjPcb
View file @ 54efb6a7
......@@ -513,6 +513,23 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document29]
DocumentPath=Schematics\Translate_3V3_I2C_to_2V5.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=19
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=VWSCYIBF
[GeneratedDocument1]
DocumentPath=Project Outputs for DIOT-sb-igl\BGA Escape Route - DIOT-sb-igl_pcb.html
DItemRevisionGUID=
......@@ -1004,6 +1021,18 @@ OutputName2=Component Cross Reference Report
OutputDocumentPath2=
OutputVariantName2=[No Variations]
OutputDefault2=0
Configuration2_Name1=ColumnNameFormat
Configuration2_Item1=CaptionAsName
Configuration2_Name2=ForceUpdateSettings
Configuration2_Item2=False
Configuration2_Name3=General
Configuration2_Item3=OpenExported=False|AddToProject=False|ReportBOMViolationsInMessages=False|ForceFit=False|NotFitted=False|Database=False|DatabasePriority=False|IncludePcbData=False|IncludeVaultData=False|IncludeCloudData=False|IncludeDocumentData=True|IncludeAlternatives=False|ShowExportOptions=True|TemplateFilename=|TemplateVaultGuid=|TemplateRevisionGuid=|BatchMode=5|FormWidth=1200|FormHeight=710|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=USD|SolutionsPerItem=1|SuppliersPerSolution=1|ViewType=0|UseDirectApi=False|BomSetName=
Configuration2_Name4=GroupOrder
Configuration2_Item4=Document=True
Configuration2_Name5=SortOrder
Configuration2_Item5=Document=Up|Designator=Up
Configuration2_Name6=VisibleOrder
Configuration2_Item6=Comment=120|Description=120|Designator=120|Footprint=120|LibRef=120|Quantity=120
OutputType3=ReportHierarchy
OutputName3=Report Project Hierarchy
OutputDocumentPath3=
......@@ -1314,6 +1343,36 @@ OutputName12=Specctra Design PCB
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Ansoft Neutral
OutputName13=Ansoft Neutral (AutoPCB)
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=HyperLynx
OutputName14=HyperLynx (AutoPCB)
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=Orcad v7 Capture Design
OutputName15=Orcad v7 Capture Design (AutoSCH)
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=P-CAD ASCII
OutputName16=P-CAD ASCII (AutoPCB)
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=P-CAD V16 Schematic Design
OutputName17=P-CAD V16 Schematic Design (AutoSCH)
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=SiSoft
OutputName18=SiSoft (AutoPCB)
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
[OutputGroup10]
Name=PostProcess Outputs
......
hw/DIOT-sb-igl.PrjPcbStructure
View file @ 54efb6a7
......@@ -12,6 +12,8 @@ Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 1,2|SchDesig
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Banks 6,7|SchDesignator=FPGA Banks 6,7|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Config|SchDesignator=FPGA Config|FileName=FPGA_Config.SchDoc|SymbolType=Normal|RawFileName=FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA Power|SchDesignator=FPGA Power|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=FMC I2C Translation|SchDesignator=FMC I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=MoniMod I2C Translation|SchDesignator=MoniMod I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD1|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD2|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Voltage_trans_SERVMOD3|SchDesignator=REPEAT(Voltage_trans_SERVMOD,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
......@@ -26,3 +28,5 @@ Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus4|SchDesignator=REPEAT(Voltage_trans_sharedbus,1,4)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Translate GPIO voltage|SchDesignator=Translate GPIO voltage|FileName=Translate_GPIO_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_GPIO_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_6_7.SchDoc|Designator=Voltage_trans_sharedbus0|SchDesignator=Voltage_trans_sharedbus0|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=CRT-GPIO I2C Translation|SchDesignator=CRT-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Translate_GPIO_to_2V5.SchDoc|Designator=SB-GPIO I2C Translation|SchDesignator=SB-GPIO I2C Translation|FileName=Translate_3V3_I2C_to_2V5.SchDoc|SymbolType=Normal|RawFileName=Translate_3V3_I2C_to_2V5.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hw/DIOT-sb-igl.pdf
View file @ 54efb6a7
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hw/Schematics/CPCI-S_Backplane_P1-P3.Harness
View file @ 54efb6a7
CRT-GPIO=I2C_SCL,I2C_SDA,RST_N,PRST_N,PWR_FAIL_N
SB-GPIO=M_SCL,M_SDA,P_RST_N,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST_N,F_IO0,F_IO1
CRT-GPIO={I2C:I2C},RST_N,PRST_N,PWR_FAIL_N
I2C=SCL,SDA
SB-GPIO={I2C:I2C},P_RST_N,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST_N,F_IO0,F_IO1
hw/Schematics/FMC.SchDoc
View file @ 54efb6a7
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hw/Schematics/Translate_GPIO_to_2V5.Harness
View file @ 54efb6a7
CRT-GPIO=I2C_SCL,I2C_SDA,RST_N,PRST_N,PWR_FAIL_N
SB-GPIO=M_SCL,M_SDA,P_RST_N,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST_N,F_IO0,F_IO1
CRT-GPIO={I2C:I2C},RST_N,PRST_N,PWR_FAIL_N
I2C=SCL,SDA
SB-GPIO={I2C:I2C},P_RST_N,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST_N,F_IO0,F_IO1
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