Commit 419d52a6 authored by Christos Gentsos's avatar Christos Gentsos

Re-annotate the design, fix length matching constraints

parent 8dde02e0
......@@ -3,7 +3,7 @@ Version=1.0
HierarchyMode=2
ChannelRoomNamingStyle=0
ReleasesFolder=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelDesignatorFormatString=$Component_$ChannelPrefix$ChannelIndex
ChannelRoomLevelSeperator=_
OpenOutputs=0
ArchiveProject=0
......@@ -28,7 +28,7 @@ DItemRevisionGUID=
ReportSuppressedErrorsInMessages=0
FSMCodingStyle=eFMSDropDownList_OneProcess
FSMEncodingStyle=eFMSDropDownList_OneHot
OutputPath=Project Outputs for DIOT-sb-igl
OutputPath=
LogFolderPath=
ManagedProjectGUID=
IncludeDesignInRelease=0
......@@ -39,7 +39,7 @@ PrefsRevisionGUID=
[Document1]
DocumentPath=Schematics\DIOT-sb-igl_top.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
......@@ -56,11 +56,11 @@ DocumentUniqueId=MRUCKTLN
[Document2]
DocumentPath=Schematics\Powering.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=1
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -73,7 +73,7 @@ DocumentUniqueId=BMEQNNRB
[Document3]
DocumentPath=Schematics\FPGA.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
......@@ -90,7 +90,7 @@ DocumentUniqueId=FOGZHMLJ
[Document4]
DocumentPath=Schematics\FPGA_Banks_0_3_5_8.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
......@@ -107,11 +107,11 @@ DocumentUniqueId=OYVWUQED
[Document5]
DocumentPath=Schematics\FPGA_Banks_1_2.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=6
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -124,11 +124,11 @@ DocumentUniqueId=CHLXHSCN
[Document6]
DocumentPath=Schematics\FPGA_Banks_6_7.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=7
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -141,11 +141,11 @@ DocumentUniqueId=HOLKXCTX
[Document7]
DocumentPath=Schematics\Monitoring.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=8
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -158,7 +158,7 @@ DocumentUniqueId=DCGCVREG
[Document8]
DocumentPath=Schematics\CPCI-S_Backplane_P1-P3.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
......@@ -175,7 +175,7 @@ DocumentUniqueId=MGGAGLMH
[Document9]
DocumentPath=Schematics\CPCI-S_Backplane_P4-P6.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
......@@ -192,11 +192,11 @@ DocumentUniqueId=WYCILRIO
[Document10]
DocumentPath=Schematics\FMC.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=11
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -213,7 +213,7 @@ AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=12
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -226,11 +226,11 @@ DocumentUniqueId=BUVPNJML
[Document12]
DocumentPath=Schematics\FPGA_Config.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=13
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -243,11 +243,11 @@ DocumentUniqueId=LHMIGOJS
[Document13]
DocumentPath=Schematics\FPGA_Power.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=3
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -328,11 +328,11 @@ DocumentUniqueId=
[Document18]
DocumentPath=Schematics\JTAG.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=15
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -345,9 +345,9 @@ DocumentUniqueId=JJWMNXJW
[Document19]
DocumentPath=Schematics\Translate_2V5_to_PPERIPH_1b.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotationIndexControlEnabled=1
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=16
......@@ -413,11 +413,11 @@ DocumentUniqueId=
[Document23]
DocumentPath=Schematics\Translate_GPIO_to_2V5.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateScope=Only Selected Parts
AnnotateOrder=18
DoLibraryUpdate=1
DoDatabaseUpdate=1
......@@ -515,9 +515,9 @@ DocumentUniqueId=
[Document29]
DocumentPath=Schematics\Translate_3V3_I2C_to_2V5.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotationIndexControlEnabled=1
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=19
......@@ -532,7 +532,7 @@ DocumentUniqueId=VWSCYIBF
[Document30]
DocumentPath=Schematics\Constrain_Periph_Nets.SchDoc
AnnotationEnabled=1
AnnotationEnabled=0
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
......@@ -733,7 +733,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
SaveSettingsToOutJob=-1
[Generic_EDE]
OutputDir=Project Outputs for DIOT-sb-igl
OutputDir=
[OutputGroup1]
Name=Netlist Outputs
......@@ -1373,6 +1373,36 @@ OutputName12=Specctra Design PCB
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Ansoft Neutral
OutputName13=Ansoft Neutral (AutoPCB)
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=HyperLynx
OutputName14=HyperLynx (AutoPCB)
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=Orcad v7 Capture Design
OutputName15=Orcad v7 Capture Design (AutoSCH)
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=P-CAD ASCII
OutputName16=P-CAD ASCII (AutoPCB)
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=P-CAD V16 Schematic Design
OutputName17=P-CAD V16 Schematic Design (AutoSCH)
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=SiSoft
OutputName18=SiSoft (AutoPCB)
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
[OutputGroup10]
Name=PostProcess Outputs
......@@ -1716,8 +1746,8 @@ L16=WWWWNWWNWWWNWWWNW
L17=WWWWWWWWWWWWWWWWN
[Annotate]
SortOrder=3
SortLocation=0
SortOrder=1
SortLocation=1
MatchParameter1=Comment
MatchStrictly1=1
MatchParameter2=Library Reference
......
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