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DIOT Igloo2-based radiation-tolerant System Board
DIOT Igloo2-based radiation-tolerant System Board
Commit 3dbf0a26 authored by Christos Gentsos's avatar Christos Gentsos
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Add voltage translators for SERVMOD_N, rules for FMC diff pairs

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DIOT-sb-igl.PrjPcb
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DIOT-sb-igl.PrjPcbStructure
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...@@ -8,9 +8,16 @@ Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|S ...@@ -8,9 +8,16 @@ Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|S
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Monitoring.SchDoc|SymbolType=Normal|RawFileName=Monitoring.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Monitoring.SchDoc|SymbolType=Normal|RawFileName=Monitoring.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Powering.SchDoc|SymbolType=Normal|RawFileName=Powering.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Powering.SchDoc|SymbolType=Normal|RawFileName=Powering.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_5_8.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_5_8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Config.SchDoc|SymbolType=Normal|RawFileName=FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Config.SchDoc|SymbolType=Normal|RawFileName=FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_1_2.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_1_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_1_2.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_1_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_0_3.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_0_3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_0_3_5_8.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_0_3_5_8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans1|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans2|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans3|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans4|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans5|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans6|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans7|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans8|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Schematics/FMC.SchDoc
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Schematics/FPGA.SchDoc
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Schematics/FPGA_Banks_1_2.Harness
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FMC-LA=P[33..0],N[33..0] FMC-LA=D_N[33..0],D_P[33..0]
FMC-SIGS=PRSNT,{I2C:I2C},{LA:FMC-LA}
I2C=SCL,SDA I2C=SCL,SDA
Schematics/JTAG.SchDoc
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