Pin swapping and placement + sch changes:
- Moved RTM_SHARED_BUS 6 and 7 to bank 64, eliminating need for IC17, T4, C65, C66, R89 and DIR signals - Swapped bank 66 with bank 67 and bank 66 with bank 68 (before: 66: lower dq, 67: a, 68: higher dq; now: 66: higher dq, 67: lower dq, 68: a) - Swapped HP banks: (before: 44: BP IO, 45: HA, 46: LA lower, 47: LA higher, 48: HB; after: 44: LA higher, 45: HA, 46: HB, 47: BP IO, 48: LA lower) - moved helper clock and fpga_clk and fpga_out_clk signals to bank 64 - changed all 0402 100nF 16V capacitors to 25V (unifying 0402 100nF) - swapped BP DUAL 4 with BP DUAL 3 (and related signals) on LVDS switches and then 2 with 4 - swapped accordingly signals on LVDS to CMOS converter - swapped FMC MGT 8 and 9 with BP MGT - changed C156, 158 and 160 from 47uF to 4.7uF - changed DDR4 I2C and Event_n to 2V5 to follow VDD SPD, and moved it to bank 64 - added LED to FPGA_DONE signal - swapped FMC MGT
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