Second prototype review (Jan. 2020)
Schematics in general
- To make it better visually, on monimod.sch, "Sheet:power" add in drawing/txt the input/output voltage levels
- To make it better visually, on monimod.sch the crossing of lines between the uC and analog Sheets could be avoided by arranging differently the IOs
- CERN OHL: "Copyright 2019-2020"
- more test points/ a led on the pcb?
- for final design: connectors with latches as on system board, at least for J2
- PESD5V0S2UAT is common cathode (reverse polarity), we should use PESD5V2S2UT (not yet in the library)
- 2.49k instead of 2.55k for the PT100 current drivers
- update Copyright to 2020
- would it make more sense to connect "rst_n" line to "EN" input of IC2 to fully power-cycle uC instead of just resetting? - we should maybe discuss with Salvatore and/or consult radiation report for uC
- check if 0.1% resistors are required
-
protection for analog inputs - I' m wondering is it possible to use internal 8MHz uC clock? (to save a component;)
Power
- 2 types of 10UF capacitor; if possible use just one type? "C9,C8,C10";"CAPC1608X80N";3;"CC0603_10UF_16V_20%_X5R";;; "C7";"CAPMP3216X180N";1;"CTE3216-18_10UF_16V_20%_AVX_TCJ";;;
uC
- Why 8MHz Xtal? In our design we used the 32Khz
- Vddio and Vddin need each 100n, I see couple of missing caps
- R31 is the only 1k 1% resistor, use instead the same 1k (0.1% if needed) as in the analog sheet
- take the reset and connect it to the DC/DC
- The usb connector for production might be useless because you will never use the USB classes.
Analog
- to avoid copy&paste mistakes, a single temperature measurement channel could be placed in a separate sheet and just instantiated 3x in analog sheet
- R6/R18/R19 are 0.1% resistors, wouldn't 1% be enough?
- R8, R9, R13, R16, R17 are 0.1% resistors, wouldn't 1% be enough?
- can R7 2k2 (the only 2k2 in design) be replaced with 2k value?
- instead of R12 20k (the only value in design) one can place 2x 10k
-
use a fuse at the output of the ratopus -
replace BJT circuit - why switches for temperature analog front-end??
Connectors
- add some labels/groups to indicated which connector is for what
- J1: reversed polarity of ESD protection on usb+/- lines
- J1: use "_p"/"_n" for differential lane instead of +/-
Fan MOSFETs
- to avoid copy&paste mistakes, have 1 sheet with single fan channel and instantiate it multiple times even on the main sheet.
- current limiting resistors in gate driver 10ohm
- larger capacitors (power) for output (1206), 10u
- fast zener between gate driver and gate
- use schottky instead of ultrafast ES2A
- look at the diode current spikes
- check the temp of the board with an IR camera
PCB layout
- add info table with layers stack (see DI/OT backplane or FMC nanoFIP)
- Layer In1 rename to GND
- Layer In2 rename to PWR
- On silkscreen usually we have CERN logo, not open hardware, right?
- Silkscreen of IC2-9 is covered by the components
- Silkscreen of J2-4-5 is too close to the board edges
- Silkscreen C8 on top of J10
- It's not the final design, but still the silkscreen in the SW could indicate which side is PT100 or LM61; also the silkscreen on the connectors could be descriptive (fans/curr/volt..)
- Several signals on the B layer are passing from cutouts/polygon splits of the In2 layer; is there something sensitive?
Radiation tolerance
- IRFH5025PbF has the highest Vth threshold voltage shift at 0V - > use IPD5N25S3-430 has lower Vth shift, you don’t need high voltage >100V; otherwise the IRF634 but at 10V of gate voltage (fixed) the Vth threshold change is quite high.
-
LTC625x should be put in place of the AD8030 - UART much more used in radiation
- L6498D has never tested??
Readthedocs
- Fig 2,3 component names not shown
- "Fan drivers" chapter reference to Fig 1 should be Fig 2 i think
Other remarks
- scatter some test points in various places
- check that the PWM pins are GPIO-capable
- also add ceramic capacitors to MOSFETs and fans
- Save BOM together with the project files
- measure power rail noise in proto
- I' m wondering has it already been tested with System board FPGA? (using the off-the-shelf backplane with its utility connector)
- For the schematics pdf generation, better plot than print, so as to enable searching in the pdf ;)
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