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DIOT Monitoring Module
DIOT Monitoring Module
Commit c3b39e0c authored by Christos Gentsos's avatar Christos Gentsos
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Main: update START, use internal 8MHz osc

parent 628f36ee
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Showing with 103 additions and 55 deletions
main_fw/atmel_start_prj/AtmelStart.env_conf
View file @ c3b39e0c
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAMD21G18A" name="SAMD21_DFP" vendor="Atmel" version="1.3.331"/>
<device-pack device="ATSAMD21G18A" name="SAMD21_DFP" vendor="Atmel" version="1.3.395"/>
</device-packs>
</environment>
main_fw/atmel_start_prj/atmel_start_config.atstart
View file @ c3b39e0c
......@@ -2,16 +2,16 @@ format_version: '2'
name: My Project
versions:
api: '1.0'
backend: 1.7.360
commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7
backend: 1.8.580
commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
content: unknown
content_pack_name: unknown
format: '2'
frontend: 1.7.360
packs_version_avr8: 1.0.1415
frontend: 1.8.580
packs_version_avr8: 1.0.1463
packs_version_qtouch: unknown
packs_version_sam: 1.0.1622
version_backend: 1.7.360
packs_version_sam: 1.0.1726
version_backend: 1.8.580
version_frontend: ''
board:
identifier: CustomBoard
......@@ -102,7 +102,7 @@ drivers:
adc_arch_gain: 1x
adc_arch_gaincorr: 0
adc_arch_inputoffset: 0
adc_arch_inputscan: 11
adc_arch_inputscan: 0
adc_arch_leftadj: false
adc_arch_offsetcorr: 0
adc_arch_refcomp: true
......@@ -323,6 +323,18 @@ drivers:
functionality: System
api: HAL:HPL:GCLK
configuration:
$input: 8000000
$input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
RESERVED_InputFreq: 8000000
RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
_$freq_output_Generic clock generator 0: 24000000
_$freq_output_Generic clock generator 1: 31250
_$freq_output_Generic clock generator 2: 48000000
_$freq_output_Generic clock generator 3: 400000
_$freq_output_Generic clock generator 4: 8000000
_$freq_output_Generic clock generator 5: 8000000
_$freq_output_Generic clock generator 6: 8000000
_$freq_output_Generic clock generator 7: 8000000
enable_gclk_gen_0: true
enable_gclk_gen_0__externalclock: 1000000
enable_gclk_gen_1: true
......@@ -384,7 +396,7 @@ drivers:
gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
gclk_gen_1_div: 256
gclk_gen_1_div_sel: false
gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
gclk_gen_2_div: 1
gclk_gen_2_div_sel: false
gclk_gen_2_oscillator: Digital Frequency Locked Loop (DFLL48M)
......@@ -413,6 +425,11 @@ drivers:
functionality: System
api: HAL:HPL:PM
configuration:
$input: 24000000
$input_id: Generic clock generator 0
RESERVED_InputFreq: 24000000
RESERVED_InputFreq_id: Generic clock generator 0
_$freq_output_CPU: 24000000
apba_div: '1'
apbb_div: '1'
apbc_div: '1'
......@@ -927,6 +944,14 @@ drivers:
functionality: System
api: HAL:HPL:SYSCTRL
configuration:
$input: 31007.751937984496
$input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
RESERVED_InputFreq: 31007.751937984496
RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
_$freq_output_8MHz Internal Oscillator (OSC8M): 8000000
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): '8000000'
_$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 186046.511627907
dfll48m_arch_bplckc: false
dfll48m_arch_calibration: false
dfll48m_arch_ccdis: true
......@@ -948,9 +973,9 @@ drivers:
enable_dfll48m: true
enable_fdpll96m: false
enable_osc32k: false
enable_osc8m: false
enable_osc8m: true
enable_osculp32k: false
enable_xosc: true
enable_xosc: false
enable_xosc32k: false
fdpll96m_arch_enable: false
fdpll96m_arch_lbypass: true
......@@ -970,11 +995,11 @@ drivers:
osc32k_arch_startup: 3 Clock Cycles (92us)
osc32k_arch_wrtlock: false
osc8m_arch_calib: 0
osc8m_arch_enable: false
osc8m_arch_enable: true
osc8m_arch_ondemand: true
osc8m_arch_overwrite_calibration: false
osc8m_arch_runstdby: false
osc8m_presc: '8'
osc8m_arch_runstdby: true
osc8m_presc: '1'
osculp32k_arch_calib: 0
osculp32k_arch_overwrite_calibration: false
osculp32k_arch_wrtlock: false
......@@ -988,7 +1013,7 @@ drivers:
xosc32k_arch_wrtlock: false
xosc32k_arch_xtalen: true
xosc_arch_ampgc: true
xosc_arch_enable: true
xosc_arch_enable: false
xosc_arch_gain: 8Mhz
xosc_arch_ondemand: false
xosc_arch_runstdby: true
......@@ -1214,3 +1239,4 @@ pads:
user_label: PB03
configuration: null
toolchain_options: []
static_files: []
main_fw/atmel_start_prj/config/hpl_adc_config.h
View file @ c3b39e0c
......@@ -243,11 +243,7 @@
// <i>This register gives the number of input sources included in pin scan. The number of input sources included is INPUTSCAN + 1. 0 disables the input scan feature. (INPUTSCAN)
// <id> adc_arch_inputscan
#ifndef CONF_ADC_0_INPUTSCAN
#ifdef MMRTSB
#define CONF_ADC_0_INPUTSCAN 0
#else
#define CONF_ADC_0_INPUTSCAN 0
#endif
#endif
// <o> Positive Mux Setting Offset <0-15>
......
main_fw/atmel_start_prj/config/hpl_gclk_config.h
View file @ c3b39e0c
......@@ -142,7 +142,7 @@
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SRC
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_OSC8M
#endif
// </h>
......
main_fw/atmel_start_prj/config/hpl_sysctrl_config.h
View file @ c3b39e0c
......@@ -46,7 +46,7 @@
// <i> Indicates whether configuration for OSC8M is enabled or not
// <id> enable_osc8m
#ifndef CONF_OSC8M_CONFIG
#define CONF_OSC8M_CONFIG 0
#define CONF_OSC8M_CONFIG 1
#endif
// <h> 8MHz Internal Oscillator (OSC8M) Control
......@@ -54,7 +54,7 @@
// <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not
// <id> osc8m_arch_enable
#ifndef CONF_OSC8M_ENABLE
#define CONF_OSC8M_ENABLE 0
#define CONF_OSC8M_ENABLE 1
#endif
// <q> On Demand Control
......@@ -72,7 +72,7 @@
// <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
// <id> osc8m_arch_runstdby
#ifndef CONF_OSC8M_RUNSTDBY
#define CONF_OSC8M_RUNSTDBY 0
#define CONF_OSC8M_RUNSTDBY 1
#endif
// <y> Prescaler
......@@ -84,7 +84,7 @@
// <i> Default: No Prescaling
// <id> osc8m_presc
#ifndef CONF_OSC8M_PRESC
#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_0_Val
#endif
// <q> Overwrite Default Osc Calibration
......@@ -284,7 +284,7 @@
// <i> Indicates whether configuration for External Multipurpose Osc is enabled or not
// <id> enable_xosc
#ifndef CONF_XOSC_CONFIG
#define CONF_XOSC_CONFIG 1
#define CONF_XOSC_CONFIG 0
#endif
// <o> Frequency <400000-32000000>
......@@ -299,7 +299,7 @@
// <i> Indicates whether External Multipurpose Oscillator is enabled or not
// <id> xosc_arch_enable
#ifndef CONF_XOSC_ENABLE
#define CONF_XOSC_ENABLE 1
#define CONF_XOSC_ENABLE 0
#endif
// <q> On Demand
......
main_fw/atmel_start_prj/driver_init.c
View file @ c3b39e0c
......@@ -212,7 +212,7 @@ static void TIMER_0_init(void)
void PWM_0_PORT_init(void)
{
gpio_set_pin_function(PA18, PINMUX_PA18E_TC3_WO0);
gpio_set_pin_function(PA18, PINMUX_PA18E_TC3_WO0);
gpio_set_pin_function(PA19, PINMUX_PA19E_TC3_WO1);
}
......@@ -233,7 +233,7 @@ void PWM_0_init(void)
void PWM_1_PORT_init(void)
{
gpio_set_pin_function(PA22, PINMUX_PA22E_TC4_WO0);
gpio_set_pin_function(PA22, PINMUX_PA22E_TC4_WO0);
gpio_set_pin_function(PA23, PINMUX_PA23E_TC4_WO1);
}
......@@ -389,6 +389,20 @@ void system_init(void)
{
init_mcu();
// GPIO on PA17
gpio_set_pin_level(PA17,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PA17, GPIO_DIRECTION_OUT);
gpio_set_pin_function(PA17, GPIO_PIN_FUNCTION_OFF);
// GPIO on PA20
// Set pin direction to input
......
main_fw/atmel_start_prj/hpl/dmac/hpl_dmac.c
View file @ c3b39e0c
......@@ -216,7 +216,6 @@ static inline void _dmac_handler(void)
hri_dmac_write_CHID_reg(DMAC, channel);
flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK);
hri_dmac_write_CHID_reg(DMAC, current_channel);
if (flag_status & DMAC_CHINTFLAG_TERR) {
hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC);
......@@ -225,6 +224,7 @@ static inline void _dmac_handler(void)
hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC);
tmp_resource->dma_cb.transfer_done(tmp_resource);
}
hri_dmac_write_CHID_reg(DMAC, current_channel);
}
/**
......
main_fw/atmel_start_prj/hpl/sercom/hpl_sercom.c
View file @ c3b39e0c
......@@ -1719,6 +1719,10 @@ int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const
NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
// Enable Address Match and PREC interrupt by default.
hri_sercomi2cs_set_INTEN_AMATCH_bit(hw);
hri_sercomi2cs_set_INTEN_PREC_bit(hw);
return ERR_NONE;
}
......@@ -1921,7 +1925,14 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
if (flags & SERCOM_I2CS_INTFLAG_ERROR) {
ASSERT(device->cb.error);
device->cb.error(device);
} else if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
}
if (flags & SERCOM_I2CS_INTFLAG_AMATCH) {
hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(hw);
}
if (flags & SERCOM_I2CS_INTFLAG_PREC) {
hri_sercomi2cs_clear_INTFLAG_PREC_bit(hw);
}
if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
if (!hri_sercomi2cs_get_STATUS_DIR_bit(hw)) {
ASSERT(device->cb.rx_done);
device->cb.rx_done(device, hri_sercomi2cs_read_DATA_reg(hw));
......@@ -1929,6 +1940,7 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
ASSERT(device->cb.tx);
device->cb.tx(device);
}
hri_sercomi2cs_clear_INTFLAG_DRDY_bit(hw);
#if (CONF_MCLK_LPDIV) != (CONF_MCLK_CPUDIV)
/* Adding grace time while waiting for SCL line to be released */
hri_sercomi2cs_clear_STATUS_reg(hw, 0);
......
main_fw/atmel_start_prj/samd21a/include/component-version.h
View file @ c3b39e0c
......@@ -3,7 +3,7 @@
*
* \brief Component version header file
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
* Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
......@@ -43,7 +43,7 @@
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 331
#define BUILD_NUMBER 395
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
......@@ -58,7 +58,7 @@
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2018-08-17 08:46:55"
#define COMPONENT_DATE_STRING "2019-09-19 13:04:38"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
main_fw/atmel_start_prj/samd21a/include/sam.h
View file @ c3b39e0c
......@@ -3,7 +3,7 @@
*
* \brief Top level header file
*
* Copyright (c) 2018 Microchip Technology Inc.
* Copyright (c) 2019 Microchip Technology Inc.
*
* \license_start
*
......@@ -30,34 +30,34 @@
#ifndef _SAM_
#define _SAM_
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
#include "samd21e15a.h"
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
#if defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
#include "samd21e16a.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
#include "samd21e17a.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
#include "samd21e18a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
#include "samd21g15a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
#include "samd21g16a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
#include "samd21j16a.h"
#elif defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
#include "samd21e15a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
#include "samd21j18a.h"
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
#include "samd21g17a.h"
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
#include "samd21g17au.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
#include "samd21g18a.h"
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
#include "samd21g18au.h"
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
#include "samd21j15a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
#include "samd21j16a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
#include "samd21g16a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
#include "samd21g15a.h"
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
#include "samd21j17a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
#include "samd21j18a.h"
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
#include "samd21g17au.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
#include "samd21e17a.h"
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
#include "samd21g18au.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
#include "samd21e18a.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
#include "samd21g18a.h"
#else
#error Library does not support the specified device
#endif
......
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