bootloader: clock changes (not used clocks?)

Signed-off-by: Adam Wujek <dev_public@wujek.eu>

bootloader: clock changes (not used clocks?)
Signed-off-by: Adam Wujek <dev_public@wujek.eu>
c0876f57 · Adam Wujek · 42058a96 · c0876f57 · c0876f57
Commit c0876f57 authored May 16, 2022 by Adam Wujek
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atmel_start_config.atstart bootloader/atmel_start_prj/atmel_start_config.atstart +22 -22

hpl_sysctrl_config.h bootloader/atmel_start_prj/config/hpl_sysctrl_config.h +11 -11

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--- a/bootloader/atmel_start_prj/atmel_start_config.atstart
+++ b/bootloader/atmel_start_prj/atmel_start_config.atstart
@@ -27,17 +27,17 @@ drivers:
    api: HAL:HPL:GCLK
    configuration:
      $input: 8000000
-      $input_id: 8MHz Internal Oscillator (OSC8M)
+      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
      RESERVED_InputFreq: 8000000
-      RESERVED_InputFreq_id: 8MHz Internal Oscillator (OSC8M)
+      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
      _$freq_output_Generic clock generator 0: 24000000
      _$freq_output_Generic clock generator 1: 31250
      _$freq_output_Generic clock generator 2: 48000000
      _$freq_output_Generic clock generator 3: 400000
      _$freq_output_Generic clock generator 4: 8000000
-      _$freq_output_Generic clock generator 5: 400000
-      _$freq_output_Generic clock generator 6: 400000
-      _$freq_output_Generic clock generator 7: 400000
+      _$freq_output_Generic clock generator 5: 8000000
+      _$freq_output_Generic clock generator 6: 8000000
+      _$freq_output_Generic clock generator 7: 8000000
      enable_gclk_gen_0: true
      enable_gclk_gen_0__externalclock: 1000000
      enable_gclk_gen_1: true
@@ -477,14 +477,14 @@ drivers:
    functionality: System
    api: HAL:HPL:SYSCTRL
    configuration:
-      $input: 31250
-      $input_id: Generic clock generator 1
-      RESERVED_InputFreq: 31250
-      RESERVED_InputFreq_id: Generic clock generator 1
+      $input: 3542.9583702391496
+      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
+      RESERVED_InputFreq: 3542.9583702391496
+      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
      _$freq_output_8MHz Internal Oscillator (OSC8M): 8000000
      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
-      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
-      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 45775390.625
+      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): '8000000'
+      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 21257.750221434897
      dfll48m_arch_bplckc: false
      dfll48m_arch_calibration: false
      dfll48m_arch_ccdis: true
@@ -514,10 +514,10 @@ drivers:
      fdpll96m_arch_lbypass: true
      fdpll96m_arch_ondemand: false
      fdpll96m_arch_runstdby: false
-      fdpll96m_clock_div: 1
-      fdpll96m_ldr: 1463
-      fdpll96m_ldrfrac: 13
-      fdpll96m_ref_clock: Generic clock generator 1
+      fdpll96m_clock_div: 1128
+      fdpll96m_ldr: 5
+      fdpll96m_ldrfrac: 0
+      fdpll96m_ref_clock: External Crystal Oscillator 0.4-32MHz (XOSC)
      osc32k_arch_calib: 0
      osc32k_arch_en1k: false
      osc32k_arch_en32k: false
@@ -545,14 +545,14 @@ drivers:
      xosc32k_arch_startup: 122 us
      xosc32k_arch_wrtlock: false
      xosc32k_arch_xtalen: true
-      xosc_arch_ampgc: false
+      xosc_arch_ampgc: true
      xosc_arch_enable: false
-      xosc_arch_gain: 2Mhz
-      xosc_arch_ondemand: true
-      xosc_arch_runstdby: false
-      xosc_arch_startup: 31 us
-      xosc_arch_xtalen: false
-      xosc_frequency: 400000
+      xosc_arch_gain: 8Mhz
+      xosc_arch_ondemand: false
+      xosc_arch_runstdby: true
+      xosc_arch_startup: 125000 us
+      xosc_arch_xtalen: true
+      xosc_frequency: 8000000
    optional_signals: []
    variant: null
    clocks:

--- a/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
@@ -291,7 +291,7 @@
 // <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
 // <id> xosc_frequency
 #ifndef CONF_XOSC_FREQUENCY
-#define CONF_XOSC_FREQUENCY 400000
+#define CONF_XOSC_FREQUENCY 8000000
 #endif

 // <h> External Multipurpose Crystal Oscillator (XOSC) Control
@@ -308,7 +308,7 @@
 // <i> If this bit is 1: the oscillator will only be running when requested by a peripheral.
 // <id> xosc_arch_ondemand
 #ifndef CONF_XOSC_ONDEMAND
-#define CONF_XOSC_ONDEMAND 1
+#define CONF_XOSC_ONDEMAND 0
 #endif

 // <q> Run In Standby
@@ -317,21 +317,21 @@
 // <i> If this bit is 1: The oscillator is not stopped in standby sleep mode.
 // <id> xosc_arch_runstdby
 #ifndef CONF_XOSC_RUNSTDBY
-#define CONF_XOSC_RUNSTDBY 0
+#define CONF_XOSC_RUNSTDBY 1
 #endif

 // <q> Enable XTAL
 // <i> Enable XTAL
 // <id> xosc_arch_xtalen
 #ifndef CONF_XOSC_XTALEN
-#define CONF_XOSC_XTALEN 0
+#define CONF_XOSC_XTALEN 1
 #endif

 // <q> Automatic Amplitude Control Enable
 // <i> Indicates whether Automatic Amplitude Control is Enabled or not
 // <id> xosc_arch_ampgc
 #ifndef CONF_XOSC_AMPGC
-#define CONF_XOSC_AMPGC 0
+#define CONF_XOSC_AMPGC 1
 #endif

 // <y> Gain of the Oscillator
@@ -343,7 +343,7 @@
 // <i> Select the Gain of the oscillator
 // <id> xosc_arch_gain
 #ifndef CONF_XOSC_GAIN
-#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val
+#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_2_Val
 #endif

 // <y> Start up time for the External Oscillator
@@ -367,7 +367,7 @@
 // <i> Default: 31 us
 // <id> xosc_arch_startup
 #ifndef CONF_XOSC_STARTUP
-#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS
+#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_125000MCS
 #endif

 // </h>
@@ -600,7 +600,7 @@
 // <i> Select the clock source.
 // <id> fdpll96m_ref_clock
 #ifndef CONF_DPLL_GCLK
-#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK1_Val
+#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC
 #endif

 #if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K)
@@ -648,21 +648,21 @@
 // <i> Clock Division Factor (Applicable if reference clock is XOSC)
 // <id> fdpll96m_clock_div
 #ifndef CONF_DPLL_DIV
-#define CONF_DPLL_DIV 1
+#define CONF_DPLL_DIV 1128
 #endif

 // <o>DPLL LDRFRAC<0-15>
 // <i> Set the  fractional part of the frequency multiplier.
 // <id> fdpll96m_ldrfrac
 #ifndef CONF_DPLL_LDRFRAC
-#define CONF_DPLL_LDRFRAC 13
+#define CONF_DPLL_LDRFRAC 0
 #endif

 // <o>DPLL LDR <0-4095>
 // <i> Set the  integer part of the frequency multiplier.
 // <id> fdpll96m_ldr
 #ifndef CONF_DPLL_LDR
-#define CONF_DPLL_LDR 1463
+#define CONF_DPLL_LDR 5
 #endif

 // </h>