bootloader: clock changes

Signed-off-by: Adam Wujek <dev_public@wujek.eu>

bootloader: clock changes
Signed-off-by: Adam Wujek <dev_public@wujek.eu>
42058a96 · Adam Wujek · 7bd0a325 · 42058a96 · 42058a96 · 42058a96
Commit 42058a96 authored May 16, 2022 by Adam Wujek
4 changed files
--- a/bootloader/atmel_start_prj/atmel_start_config.atstart
+++ b/bootloader/atmel_start_prj/atmel_start_config.atstart
@@ -26,10 +26,10 @@ drivers:
    functionality: System
    api: HAL:HPL:GCLK
    configuration:
-      $input: 48000000
-      $input_id: Digital Frequency Locked Loop (DFLL48M)
-      RESERVED_InputFreq: 48000000
-      RESERVED_InputFreq_id: Digital Frequency Locked Loop (DFLL48M)
+      $input: 8000000
+      $input_id: 8MHz Internal Oscillator (OSC8M)
+      RESERVED_InputFreq: 8000000
+      RESERVED_InputFreq_id: 8MHz Internal Oscillator (OSC8M)
      _$freq_output_Generic clock generator 0: 24000000
      _$freq_output_Generic clock generator 1: 31250
      _$freq_output_Generic clock generator 2: 48000000
@@ -54,7 +54,7 @@ drivers:
      enable_gclk_gen_6__externalclock: 1000000
      enable_gclk_gen_7: false
      enable_gclk_gen_7__externalclock: 1000000
-      gclk_arch_gen_0_RUNSTDBY: false
+      gclk_arch_gen_0_RUNSTDBY: true
      gclk_arch_gen_0_enable: true
      gclk_arch_gen_0_idc: false
      gclk_arch_gen_0_oe: false
@@ -69,7 +69,7 @@ drivers:
      gclk_arch_gen_2_idc: false
      gclk_arch_gen_2_oe: false
      gclk_arch_gen_2_oov: false
-      gclk_arch_gen_3_RUNSTDBY: false
+      gclk_arch_gen_3_RUNSTDBY: true
      gclk_arch_gen_3_enable: true
      gclk_arch_gen_3_idc: false
      gclk_arch_gen_3_oe: false
@@ -97,7 +97,7 @@ drivers:
      gclk_gen_0_div: 2
      gclk_gen_0_div_sel: false
      gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
-      gclk_gen_1_div: 32
+      gclk_gen_1_div: 256
      gclk_gen_1_div_sel: false
      gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
      gclk_gen_2_div: 1
@@ -162,7 +162,7 @@ drivers:
      i2c_slave_amode: Mask
      i2c_slave_gencen: false
      i2c_slave_lowtout: false
-      i2c_slave_runstdby: false
+      i2c_slave_runstdby: true
      i2c_slave_sclsm: false
      i2c_slave_sdahold: 300-600ns hold time
      i2c_slave_sexttoen: false
@@ -481,7 +481,7 @@ drivers:
      $input_id: Generic clock generator 1
      RESERVED_InputFreq: 31250
      RESERVED_InputFreq_id: Generic clock generator 1
-      _$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
+      _$freq_output_8MHz Internal Oscillator (OSC8M): 8000000
      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 45775390.625
@@ -494,12 +494,12 @@ drivers:
      dfll48m_arch_llaw: false
      dfll48m_arch_ondemand: false
      dfll48m_arch_qldis: false
-      dfll48m_arch_runstdby: false
+      dfll48m_arch_runstdby: true
      dfll48m_arch_stable: false
-      dfll48m_arch_usbcrm: true
+      dfll48m_arch_usbcrm: false
      dfll48m_arch_waitlock: false
      dfll48m_mode: Closed Loop Mode
-      dfll48m_mul: 48000
+      dfll48m_mul: 1536
      dfll48m_ref_clock: Generic clock generator 1
      dfll_arch_cstep: 3
      dfll_arch_fstep: 31
@@ -531,8 +531,8 @@ drivers:
      osc8m_arch_enable: true
      osc8m_arch_ondemand: true
      osc8m_arch_overwrite_calibration: false
-      osc8m_arch_runstdby: false
-      osc8m_presc: '8'
+      osc8m_arch_runstdby: true
+      osc8m_presc: '1'
      osculp32k_arch_calib: 0
      osculp32k_arch_overwrite_calibration: false
      osculp32k_arch_wrtlock: false

--- a/bootloader/atmel_start_prj/config/hpl_gclk_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_gclk_config.h
@@ -151,7 +151,7 @@
 // <i>
 // <id> gclk_gen_1_div
 #ifndef CONF_GCLK_GEN_1_DIV
-#define CONF_GCLK_GEN_1_DIV 32
+#define CONF_GCLK_GEN_1_DIV 256
 #endif

 // </h>

--- a/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
@@ -84,7 +84,7 @@
 // <i> Default: No Prescaling
 // <id> osc8m_presc
 #ifndef CONF_OSC8M_PRESC
-#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val
+#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_0_Val
 #endif

 // <q> Overwrite Default Osc Calibration
@@ -479,14 +479,14 @@
 // <i> If this bit is 1: The DFLL is not stopped in standby sleep mode.
 // <id> dfll48m_arch_runstdby
 #ifndef CONF_DFLL_RUNSTDBY
-#define CONF_DFLL_RUNSTDBY 0
+#define CONF_DFLL_RUNSTDBY 1
 #endif

 // <q> USB Clock Recovery Mode
 // <i> USB Clock Recovery Mode
 // <id> dfll48m_arch_usbcrm
 #ifndef CONF_DFLL_USBCRM
-#define CONF_DFLL_USBCRM 1
+#define CONF_DFLL_USBCRM 0
 #endif

 #if CONF_DFLL_USBCRM == 1
@@ -540,7 +540,7 @@
 //  <i> Default: 0
 //  <id> dfll48m_mul
 #ifndef CONF_DFLL_MUL
-#define CONF_DFLL_MUL 48000
+#define CONF_DFLL_MUL 1536
 #endif

 // <e> DFLL Calibration Overwrite

--- a/bootloader/atmel_start_prj/hpl/core/hpl_init.c
+++ b/bootloader/atmel_start_prj/hpl/core/hpl_init.c
@@ -41,10 +41,11 @@
 #include <hpl_dmac_config.h>

 /* Referenced GCLKs (out of 0~7), should be initialized firstly
+ * - GCLK 1 for DFLL48M
 */
-#define _GCLK_INIT_1ST 0x00000000
+#define _GCLK_INIT_1ST 0x00000002
 /* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x000000FF
+#define _GCLK_INIT_LAST 0x000000FD

 /**
 * \brief Initialize the hardware abstraction layer