Commit 3fd39d9b authored by Adam Wujek's avatar Adam Wujek

bootloader/atmel_start: Disable Address Match and PREC interrupt

If enabled there is wrong data returned via i2c, like:
$ i2cdump -y 9 0x12 s 0x9a
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 22 44 88 49 92 4f 9e 54 a8 20 40 4d 9a 6f de 6e    "D?I?O?T? @M?o?n
10: dc
Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent dc36991d
Pipeline #3672 passed with stage
in 46 seconds
......@@ -1719,10 +1719,6 @@ int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const
NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
// Enable Address Match and PREC interrupt by default.
hri_sercomi2cs_set_INTEN_AMATCH_bit(hw);
hri_sercomi2cs_set_INTEN_PREC_bit(hw);
return ERR_NONE;
}
......@@ -1925,14 +1921,7 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
if (flags & SERCOM_I2CS_INTFLAG_ERROR) {
ASSERT(device->cb.error);
device->cb.error(device);
}
if (flags & SERCOM_I2CS_INTFLAG_AMATCH) {
hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(hw);
}
if (flags & SERCOM_I2CS_INTFLAG_PREC) {
hri_sercomi2cs_clear_INTFLAG_PREC_bit(hw);
}
if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
} else if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
if (!hri_sercomi2cs_get_STATUS_DIR_bit(hw)) {
ASSERT(device->cb.rx_done);
device->cb.rx_done(device, hri_sercomi2cs_read_DATA_reg(hw));
......@@ -1940,7 +1929,6 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
ASSERT(device->cb.tx);
device->cb.tx(device);
}
hri_sercomi2cs_clear_INTFLAG_DRDY_bit(hw);
#if (CONF_MCLK_LPDIV) != (CONF_MCLK_CPUDIV)
/* Adding grace time while waiting for SCL line to be released */
hri_sercomi2cs_clear_STATUS_reg(hw, 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment