Commit ae3420f6 authored by Michal Gaska's avatar Michal Gaska

changes after review

parent 5dbb51f4
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update=9/18/2019 9:55:05 PM
update=28.10.2019 17:37:22
version=1
last_client=kicad
[general]
......@@ -27,7 +27,7 @@ version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=12
BoardThickness=3.5
BoardThickness=4
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
......@@ -288,3 +288,14 @@ uViaDrill=0.1
dPairWidth=0.15
dPairGap=0.102
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=high_curr
Clearance=0.102
TrackWidth=0.102
ViaDiameter=0.5
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uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.102
dPairGap=0.127
dPairViaGap=0.25
......@@ -4859,4 +4859,102 @@ F 39 "This work is licensed under the Creative Commons CC-BY-SA 4.0 License. To
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
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Ref,Val,Package,PosX,PosY,Rot,Side
"J2","AMPHENOL_53611-G16-8LF","AMPHENOL_53611-G16-8LF",112.500000,-82.236000,270.000000,bottom
"J3","AMPHENOL_53611-G16-8LF","AMPHENOL_53611-G16-8LF",101.500000,-82.236000,270.000000,bottom
"JP1","Jumper","PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Right",104.500000,-111.000000,180.000000,bottom
"SW1","SW_DIP_x04","SW_OMRON_A6H-4102",114.250000,-110.500000,270.000000,bottom
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