adding v0.1 of main CPCIs backplane sch and layout

56d936d0 · Grzegorz Daniluk · 34797d2d · 56d936d0 · 56d936d0 · 56d936d0
Commit 56d936d0 authored Oct 06, 2019 by Grzegorz Daniluk
14 changed files
--- a/pcb/cpcis_backplane/AIRMAX.lib
+++ b/pcb/cpcis_backplane/AIRMAX.lib
--- a/pcb/cpcis_backplane/CPCI Backplane-cache.lib
+++ b/pcb/cpcis_backplane/CPCI Backplane-cache.lib
--- a/pcb/cpcis_backplane/CPCI Backplane-rescue.dcm
+++ b/pcb/cpcis_backplane/CPCI Backplane-rescue.dcm
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
--- a/pcb/cpcis_backplane/CPCI Backplane-rescue.lib
+++ b/pcb/cpcis_backplane/CPCI Backplane-rescue.lib
--- a/pcb/cpcis_backplane/CPCI Backplane.kicad_pcb
+++ b/pcb/cpcis_backplane/CPCI Backplane.kicad_pcb
--- a/pcb/cpcis_backplane/CPCI Backplane.pro
+++ b/pcb/cpcis_backplane/CPCI Backplane.pro
+update=9/18/2019 9:55:05 PM
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=schematics/
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+CopperLayerCount=12
+BoardThickness=3.5
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.09999999999999999
+MinViaDiameter=0.4
+MinViaDrill=0.2
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.102
+ViaDiameter1=0.4
+ViaDrill1=0.2
+dPairWidth1=0.102
+dPairGap1=0.127
+dPairViaGap1=0.25
+dPairWidth2=0.102
+dPairGap2=0.127
+dPairViaGap2=0.127
+dPairWidth3=0.12
+dPairGap3=0.15
+dPairViaGap3=0.15
+dPairWidth4=0.15
+dPairGap4=0.102
+dPairViaGap4=0.102
+SilkLineWidth=0.15
+SilkTextSizeV=0.7
+SilkTextSizeH=0.7
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.09999999999999999
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=Sig1.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In2.Cu]
+Name=GND2.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In3.Cu]
+Name=Sig2.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In4.Cu]
+Name=GND3.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In5.Cu]
+Name=Sig3.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In6.Cu]
+Name=GND4.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In7.Cu]
+Name=Sig4.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In8.Cu]
+Name=GND5.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In9.Cu]
+Name=Sig5.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In10.Cu]
+Name=GND6.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.102
+TrackWidth=0.102
+ViaDiameter=0.4
+ViaDrill=0.2
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.102
+dPairGap=0.127
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=CLK_diff
+Clearance=0.102
+TrackWidth=0.102
+ViaDiameter=0.4
+ViaDrill=0.2
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.102
+dPairGap=0.127
+dPairViaGap=0.25
+[pcbnew/Netclasses/2]
+Name=Diff
+Clearance=0.102
+TrackWidth=0.102
+ViaDiameter=0.4
+ViaDrill=0.2
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.102
+dPairGap=0.127
+dPairViaGap=0.25
+[pcbnew/Netclasses/3]
+Name=MGT
+Clearance=0.102
+TrackWidth=0.25
+ViaDiameter=0.4
+ViaDrill=0.2
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.15
+dPairGap=0.102
+dPairViaGap=0.25
--- a/pcb/cpcis_backplane/CPCI Backplane.sch
+++ b/pcb/cpcis_backplane/CPCI Backplane.sch
--- a/pcb/cpcis_backplane/Power.sch
+++ b/pcb/cpcis_backplane/Power.sch
--- a/pcb/cpcis_backplane/Slot_1.sch
+++ b/pcb/cpcis_backplane/Slot_1.sch
--- a/pcb/cpcis_backplane/Slot_1b.sch
+++ b/pcb/cpcis_backplane/Slot_1b.sch
--- a/pcb/cpcis_backplane/Slot_periph.sch
+++ b/pcb/cpcis_backplane/Slot_periph.sch
--- a/pcb/cpcis_backplane/fp-info-cache
+++ b/pcb/cpcis_backplane/fp-info-cache
--- a/pcb/cpcis_backplane/pdf/CPCI Backplane.pdf
+++ b/pcb/cpcis_backplane/pdf/CPCI Backplane.pdf
--- a/pcb/cpcis_backplane/sym-lib-table
+++ b/pcb/cpcis_backplane/sym-lib-table
+(sym_lib_table
+  (lib (name CPCI-Backplane-rescue)(type Legacy)(uri "${KIPRJMOD}/CPCI Backplane-rescue.lib")(options "")(descr ""))
+)