Commit 7d5e10f9 authored by Qiang Du's avatar Qiang Du

IPROG support. See README

parent e1ac2ab1
#program golden bitstream file into flash
python mbtest.py -t <target> -a 0x0 -p golden.bin
#program multiboot bitstream file into flash
python mbtest.py -t <target> -a 0x300000 -p multi.bin
#read bitstream file back:
python mbtest.py -t <target> -a 0x0 -d foo.bin
# reboot from address 0x300000 using multiboot image
python mbtest.py -t <target> -r 0x300000
......@@ -18,6 +18,7 @@ def usage():
print '-e, --erase <size in hex (min 64kB)>'
print '-i, --id'
print '-s, --status'
print '-r, --reconfigure <address in hex>'
def main(argv):
log_level = logging.DEBUG
......@@ -29,7 +30,7 @@ def main(argv):
sys.exit()
try:
opts, args = getopt.getopt(argv, 'hisa:d:p:e:t:',['help','dump=','target=','address=','program=','erase=','id','status'])
opts, args = getopt.getopt(argv, 'hisa:d:p:e:t:r:',['help','dump=','target=','address=','program=','erase=','id','status','reconfigure='])
except getopt.GetoptError as err:
print str(err)
sys.exit(2)
......@@ -38,7 +39,7 @@ def main(argv):
target_ip = 'rflab2.lbl.gov'
flash_address = 0x0
flash_size = 0xf3
prog_file = '../../syn/cute_wr/wr_core_demo/cute_top_wrc.bit'
prog_file = '../../syn/cute_wr/wr_core_demo/cute_top_wrc.bin'
dump_file = 'dump_foo'
for opt,arg in opts:
......@@ -66,6 +67,9 @@ def main(argv):
action = 'id'
elif opt in ('--status', '-s'):
action = 'status'
elif opt in ('--reconfigure', '-r'):
action = 'reconfigure'
icap_addr = int(arg, base=16)
logging.info('action ='+ action)
......@@ -88,6 +92,9 @@ def main(argv):
elif (action is 'status'):
status = mb.flash.rsr()
logging.info('Status: 0x%x'% status)
elif (action is 'reconfigure'):
logging.info('reconfiguring to add: 0x%x' % icap_addr)
mb.iprog(icap_addr)
target.close()
......
......@@ -159,6 +159,15 @@ class XilMultiboot:
break
except NAckError:
continue
elif (self.comm == ETHERBONE):
logging.info("Issuing IPROG command to board...")
self.ebone.write(self.mb_base+MB_GBBAR_OFS, 0x44 | (0x0b << 24))
self.ebone.write(self.mb_base+MB_MBBAR_OFS, addr | (0x0b << 24))
self.ebone.write(self.mb_base+MB_CR_OFS, 0x10000)
try:
self.ebone.write(self.mb_base+MB_CR_OFS, 0x20000)
except NAckError:
pass
#
# Sequence to read FPGA configuration register
......
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