From 6e1253343266f175c250f63adf63b7b2a1f9bf98 Mon Sep 17 00:00:00 2001
From: hongming <lihm.thu@gmail.com>
Date: Thu, 27 Oct 2016 22:35:07 +0800
Subject: [PATCH] Change the directory of the wrc.vhd.
---
submodules/wr-cores | 2 +-
syn/cute_wr/wr_core_demo/Makefile | 8 ++++----
syn/cute_wr/wr_core_demo/cute_top.xise | 18 +++++++++---------
top/cute_wr/wr_core_demo/Manifest.py | 2 +-
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/submodules/wr-cores b/submodules/wr-cores
index f5e528e..1a1340e 160000
--- a/submodules/wr-cores
+++ b/submodules/wr-cores
@@ -1 +1 @@
-Subproject commit f5e528e8d8e984e1b8ee0f318c25b45c422adb01
+Subproject commit 1a1340e5c51d5546effe20496034ea0c906015af
diff --git a/syn/cute_wr/wr_core_demo/Makefile b/syn/cute_wr/wr_core_demo/Makefile
index 23110f4..ac5461f 100644
--- a/syn/cute_wr/wr_core_demo/Makefile
+++ b/syn/cute_wr/wr_core_demo/Makefile
@@ -77,7 +77,6 @@ FILES := ../../../submodules/wr-cores/top/cute_wrc/ip_cores/cute_wrc.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgenplus/wb_skidpad.vhd \
../../../submodules/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
-../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../submodules/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_moving_average.vhd \
@@ -118,7 +117,7 @@ run.tcl \
../../../submodules/wr-cores/modules/wr_eca/eca_search.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../submodules/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
-../../../submodules/wr-cores/top/cute_wrc/ip_cores/wrc.vhd \
+../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../submodules/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
@@ -143,7 +142,7 @@ run.tcl \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
-../../../submodules/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
+../../../submodules/wr-cores/modules/timing/pulse_gen.vhd \
../../../submodules/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
@@ -280,7 +279,7 @@ cute_top.xise \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
-../../../submodules/wr-cores/modules/timing/pulse_gen.vhd \
+../../../submodules/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
../../../submodules/wr-cores/modules/wr_eca/eca.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
@@ -356,6 +355,7 @@ cute_top.xise \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
+../../../submodules/wrpc-sw/wrc.vhd \
../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../../top/cute_wr/wr_core_demo/cute_top.ucf \
../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
diff --git a/syn/cute_wr/wr_core_demo/cute_top.xise b/syn/cute_wr/wr_core_demo/cute_top.xise
index f970ffc..e9a3c94 100644
--- a/syn/cute_wr/wr_core_demo/cute_top.xise
+++ b/syn/cute_wr/wr_core_demo/cute_top.xise
@@ -404,9 +404,6 @@
<file xil_pn:name="../../../submodules/wr-cores/modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
- <file xil_pn:name="../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
- </file>
<file xil_pn:name="../../../submodules/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
@@ -521,8 +518,8 @@
<file xil_pn:name="../../../submodules/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
- <file xil_pn:name="../../../submodules/wr-cores/top/cute_wrc/ip_cores/wrc.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <file xil_pn:name="../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
@@ -596,8 +593,8 @@
<file xil_pn:name="../../../submodules/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
- <file xil_pn:name="../../../submodules/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <file xil_pn:name="../../../submodules/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../submodules/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
@@ -1004,8 +1001,8 @@
<file xil_pn:name="../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
- <file xil_pn:name="../../../submodules/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <file xil_pn:name="../../../submodules/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../submodules/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -1229,6 +1226,9 @@
<file xil_pn:name="../../../submodules/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
+ <file xil_pn:name="../../../submodules/wrpc-sw/wrc.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
<file xil_pn:name="../../../submodules/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
diff --git a/top/cute_wr/wr_core_demo/Manifest.py b/top/cute_wr/wr_core_demo/Manifest.py
index 1467220..f853cdb 100644
--- a/top/cute_wr/wr_core_demo/Manifest.py
+++ b/top/cute_wr/wr_core_demo/Manifest.py
@@ -1,4 +1,4 @@
-files = ["cute_top.vhd", "cute_top.ucf", "cute_reset_gen.vhd","user_tcp_demo.vhd","xwr_com5402.ngc"]
+files = ["cute_top.vhd", "cute_top.ucf", "cute_reset_gen.vhd","user_tcp_demo.vhd","xwr_com5402.ngc","../../../submodules/wrpc-sw/wrc.vhd"]
modules = {
"local" : ["../../../submodules/wr-cores/top/cute_wrc/ip_cores/"]
--
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