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Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
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  • Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
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Opened Feb 21, 2022 by Tristan Gingold@tgingold
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incorrect voltage translator for FMC JTAG signals

U4 (page 14) is used to translate voltage from FMC_VADJ to P3V3 for the FMC JTAG signals.

But according to ANSI/VITA 57.1-2019:

Rule 5.66: The FMC JTAG signals shall require LVTTL (3.3V) levels on the JTAG signals.

So U4 should be removed.

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Reference: project/cute-wr-dp#4