Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP issueshttps://ohwr.org/project/cute-wr-dp/issues2022-02-21T07:53:35Zhttps://ohwr.org/project/cute-wr-dp/issues/4incorrect voltage translator for FMC JTAG signals2022-02-21T07:53:35ZTristan Gingoldincorrect voltage translator for FMC JTAG signalsU4 (page 14) is used to translate voltage from FMC_VADJ to P3V3 for the FMC JTAG signals.
But according to ANSI/VITA 57.1-2019:
Rule 5.66: The FMC JTAG signals shall require LVTTL (3.3V) levels on the JTAG signals.
So U4 should be removed.https://ohwr.org/project/cute-wr-dp/issues/1Hardware LED pin bug2019-03-21T07:26:51Zli hongmingHardware LED pin bugThe LED pins bug:
the cathodes are on pin 1 and 3 while on the PCB they are connected to
P3.3V instead of the FPGA.li hongmingli hongming