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Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
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Cycle Analytics
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Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
Commits
d2b4c5101d0fc1c96f66555be571584528af5c8d
Switch branch/tag
cute-wr-dp
schematics
05-FPGA_bank3.SchDoc
25 Oct, 2018
1 commit
Change TRIG to CLK and modify its pin to K3.
· d2b4c510
hongming
authored
Oct 25, 2018
d2b4c510
30 Mar, 2018
1 commit
Version CUTEDP-V2.2.
· 3373722c
hongming
authored
Mar 30, 2018
3373722c
05 Apr, 2017
1 commit
CUTEWR-DP-V2.
· 112336c2
hongming
authored
Apr 05, 2017
112336c2
