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Conv TTL RS485
Commit d133efb1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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[submodule "conv-ttl-rs485-gw"]
path = conv-ttl-rs485-gw
url = git@ohwr.org:level-conversion/conv-ttl-rs485/conv-ttl-rs485-gw.git
[submodule "conv-ttl-rs485-hw"]
path = conv-ttl-rs485-hw
url = git@ohwr.org:level-conversion/conv-ttl-rs485/conv-ttl-rs485-hw.git
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This is the project of the new RS-485 repetitor boards.
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-------------------------------------------------------------------------------
SVEC schematics review 25.04.2012
-------------------------------------------------------------------------------
MEETING SUMMARY
+ DATE 18-07-2012
+ PLACE CERN Prevessin, Building 864, Room 1-A15
+ SUBJECT CONV-TTL-RS485 Review
+ SVN http://www.ohwr.org/projects/conv-ttl-rs485
+ REVISION 3
+ PARTICIPANTS:
Van der Bij, Erik EVB Erik.van.der.Bij@cern.ch
Cattin, Matthieu MC matthieu.cattin@cern.ch
Gil Soriano, Carlos CGS carlos.gil.soriano@cern.ch
+ SUMMARY
It is need to replace the front array of leds for the Dialight 568 ones.
===============================================================================
| ! : fatal |
| + : important |
| - : minor |
| ? : question |
| * : note |
| A : already |
===============================================================================
===============================================================================
SCHEMATICS
+ convTTLrs485_TOP.SchDoc
--+ PowerSupply.SchDoc
--+ FPGAbank.SchDoc
--+ Clocks&Monitor.SchDoc
--+ VME64xConn.SchDoc
--+ Communication.SchDoc
--+ FrontTTL.SchDoc
--+ FrontPanelLeds.SchDoc
--+ Input RS485.SchDoc
--+ Input Unit RS485.SchDoc
--+ Output RS485.SchDoc
--+ Output Unit RS485.SchDoc
--+ JTAG&Button.SchDoc
--> BOM
===============================================================================
--------------------------------------
PowerSupply.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FPGAbank.SchDoc
--------------------------------------
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--------------------------------------
Clocks&Monitor.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
VME64xConn.SchDoc
--------------------------------------
[CGS] - Blue text "P12V_VME" in P1D must be removed.
--------------------------------------
--------------------------------------
Communication.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FrontTTL.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FrontPanelLeds.SchDoc
--------------------------------------
[CGS] ! All the three arrays of red leds should be replaced by Dialigth 568.
--------------------------------------
--------------------------------------
Input RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Input Unit RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Output RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Output Unit RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
JTAG&Button.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
BOM
--------------------------------------
--------------------------------------
===============================================================================
LAYOUT
===============================================================================
[CGS] + SW1 is not readable. It must include "TTL/INV_TTL_N"
[CGS] + SW2 should be moved away from SW1. Improve readability
[CGS] + Space up the fuses F1 and F2 for ease of replacement.
[CGS] - Move logo and webpage to the huge empty room in the lower part of the
board.
conv-ttl-rs485-gw @ 28ae2bbf
Subproject commit 28ae2bbf237ccf567da29f91b45f12d95b2e024f
conv-ttl-rs485-hw @ 73db8290
Subproject commit 73db8290f5d8028df555bb522a9d4ee29b6212c7
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CLK20_VCXO IC15-E16
EXTRA_SWITCH_1 IC15-F22
EXTRA_SWITCH_2 IC15-G22
EXTRA_SWITCH_3 IC15-H21
EXTRA_SWITCH_4 IC15-H22
EXTRA_SWITCH_5 IC15-J22
EXTRA_SWITCH_6 IC15-K21
EXTRA_SWITCH_7 IC15-K22
FPGA_CLK_N IC15-G11
FPGA_CLK_P IC15-H12
FPGA_GA0 IC15-H20
FPGA_GA1 IC15-J20
FPGA_GA2 IC15-K19
FPGA_GA3 IC15-K20
FPGA_GA4 IC15-L19
FPGA_GAP IC15-H19
FPGA_INPUT_TTL1_N IC15-T3
FPGA_INPUT_TTL2_N IC15-U4
FPGA_INPUT_TTL3_N IC15-W3
FPGA_INPUT_TTL4_N IC15-W4
FPGA_INPUT_TTL5_N IC15-V3
FPGA_INPUT_TTL6_N IC15-U3
FPGA_INV_OE IC15-N4
FPGA_OE IC15-N3
FPGA_OUT_TTL1 IC15-D1
FPGA_OUT_TTL2 IC15-E1
FPGA_OUT_TTL3 IC15-F2
FPGA_OUT_TTL4 IC15-F1
FPGA_OUT_TTL5 IC15-G1
FPGA_OUT_TTL6 IC15-H2
FPGA_PLLDAC1_DIN IC15-Y14
FPGA_PLLDAC1_SCLK IC15-AA14
FPGA_PLLDAC1_SYNC_N IC15-AB15
FPGA_PLLDAC2_DIN IC15-AB13
FPGA_PLLDAC2_SCLK IC15-Y13
FPGA_PLLDAC2_SYNC_N IC15-AB14
FPGA_PROM_CCLK IC15-Y20
FPGA_PROM_CSO_B_N IC15-AA3
FPGA_PROM_DIN IC15-AA20
FPGA_PROM_MOSI IC15-AB20
FPGA_RS485_INA_TTL_1 IC15-Y12
FPGA_RS485_INA_TTL_2 IC15-AB12
FPGA_RS485_INA_TTL_3 IC15-AB11
FPGA_RS485_INA_TTL_4 IC15-AB10
FPGA_RS485_INA_TTL_5 IC15-AB9
FPGA_RS485_INA_TTL_6 IC15-AA8
FPGA_RS485_INB_TTL_1 IC15-AA12
FPGA_RS485_INB_TTL_2 IC15-Y11
FPGA_RS485_INB_TTL_3 IC15-Y10
FPGA_RS485_INB_TTL_4 IC15-AA10
FPGA_RS485_INB_TTL_5 IC15-AB8
FPGA_RS485_INB_TTL_6 IC15-AB7
FPGA_RS485_OE IC15-AB6
FPGA_RTMM0 IC15-V21
FPGA_RTMM1 IC15-V22
FPGA_RTMM2 IC15-U22
FPGA_RTMP0 IC15-W22
FPGA_RTMP1 IC15-Y22
FPGA_RTMP2 IC15-Y21
FPGA_SFP_LOS IC15-G3
FPGA_SFP_PRESENCE IC15-E3
FPGA_SFP_RATE_SELECT IC15-C4
FPGA_SFP_SCL IC15-F3
FPGA_SFP_SDA IC15-G4
FPGA_SYSRESET_N IC15-L20
FPGA_TRIG_RS485_1 IC15-W18
FPGA_TRIG_RS485_2 IC15-Y18
FPGA_TRIG_RS485_3 IC15-W17
FPGA_TRIG_RS485_4 IC15-Y17
FPGA_TRIG_RS485_5 IC15-Y16
FPGA_TRIG_RS485_6 IC15-Y15
FPGA_TRIG_TTL_OE IC15-M3
GND R134-2
INV_IN_1_N IC15-Y1
INV_IN_2_N IC15-Y2
INV_IN_3_N IC15-AA1
INV_IN_4_N IC15-AA2
INV_OUT_1 IC15-H1
INV_OUT_2 IC15-J1
INV_OUT_3 IC15-K2
INV_OUT_4 IC15-K1
LED_CTRL0 IC15-M5
LED_CTRL0_OEN IC15-M4
LED_CTRL1 IC15-K6
LED_CTRL1_OEN IC15-K5
LED_MULTICAST_2_0 IC15-F9
LED_MULTICAST_3_1 IC15-F10
LED_WR_GMT_TTL_TTLN IC15-E5
LED_WR_LINK_SYSERROR IC15-F7
LED_WR_OK_SYSPW IC15-F8
LED_WR_OWNADDR_I2C IC15-E6
MULTICAST_ADDR_1 IC15-B21
MULTICAST_ADDR_2 IC15-B22
MULTICAST_ADDR_3 IC15-C22
MULTICAST_ADDR_4 IC15-D21
P3V3 R100-2 R111-2 R133-2
PULSE_FRONT_LED1_N IC15-H3
PULSE_FRONT_LED2_N IC15-J4
PULSE_FRONT_LED3_N IC15-J3
PULSE_FRONT_LED4_N IC15-K3
PULSE_FRONT_LED5_N IC15-L4
PULSE_FRONT_LED6_N IC15-L3
PULSE_REAR_LED1 IC15-AB17
PULSE_REAR_LED2 IC15-AB19
PULSE_REAR_LED3 IC15-AA16
PULSE_REAR_LED4 IC15-AA18
PULSE_REAR_LED5 IC15-AB16
PULSE_REAR_LED6 IC15-AB18
RST IC15-M16
SCL_I IC15-F19
SCL_O IC15-E20
SCL_OE IC15-H18
SDA_I IC15-G20
SDA_O IC15-F20
SDA_OE IC15-J19
SFP_TX_DISABLE IC15-E4
SFP_TX_FAULT IC15-D2
THERMOMETER IC15-B1
TTL/INV_TTL_N IC15-L22
FPGA_HEADER_IN1 IC15-A17
FPGA_HEADER_IN2 IC15-A18
FPGA_HEADER_IN3 IC15-B18
FPGA_HEADER_IN4 IC15-A19
FPGA_HEADER_IN5 IC15-A20
FPGA_HEADER_IN6 IC15-B20
FPGA_HEADER_OUT1 IC15-F15
FPGA_HEADER_OUT2 IC15-F16
FPGA_HEADER_OUT3 IC15-F17
FPGA_HEADER_OUT4 IC15-F14
FPGA_HEADER_OUT5 IC15-H14
FPGA_HEADER_OUT6 IC15-H13
hdl/IMAGES/image1/constraints/V1/net2ucf.py deleted 100644 → 0
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#!/usr/bin/python
## @package net2ucf.py
# @author Matthieu Cattin, Carlos Gil Soriano.
# This is a modified net2ucf.py by Carlos Gil Soriano,
# previously done by Matthieu Cattin.
import re
## @class net2ucf class able to extract ucf files from an Altium NET files
class NET2UCF:
## @brief Constructor of the ucf extractor
# @param path_ucfFile Path to be written the ucf file
# @param path_excludedNetsFile A path with the nets files to be excluded
# @param ICid IC identificator to extract the ucf from
def __init__(self, path_netFile, path_ucfFile, path_excludedNetsFile, ICid):
if path_netFile.endswith('.NET'):
try:
self.netFile = open(path_netFile, "r")
except IOError as e:
print '.NET file does not exist!'
else:
raise Exception('Bad extension of the net file')
if path_ucfFile.endswith('.ucf'):
try:
self.ucfFile = open(path_ucfFile, "w")
except IOError as e:
print '.ucf file does not exist!'
else:
raise Exception('Bad extension of the ucf file')
if path_excludedNetsFile.endswith('.XNET'):
try:
self.excludedNetsFile = open(path_excludedNetsFile, "r")
except IOError as e:
print '.XNET file does not exist!'
print "I'm here!"
self.listExcludedNets = []
for line in self.excludedNetsFile:
ln = line.split()
self.listExcludedNets.append(ln[0])
print 'Excluded nets:\n' + str(self.listExcludedNets)
else:
raise Exception('Bad extension of the excluded nets file')
self.ICid = ICid
## @fn generateUCF(self)
# @brief Function that process the NET file and generates the UCF one.
def generateUCF(self):
for line in self.netFile:
ln = line.split()
skip = False
for item in self.listExcludedNets:
if ln[0].startswith(str(item)):
print str(ln[0])+'Omitted because is a excluded net'
skip = True
if skip == False:
try:
print ln;
if ln[1].startswith('IC15'):
self.ucfFile.write("NET \""+ln[0]+"\" LOC = "+ln[1].split('-')[1]+";\n")
except IOError as e:
print 'Bad line in FPGA.NET'
print '-------------------------------------'
print '-------- NET2UCF program --------'
print '-------------------------------------\n'
print 'Case sensitive!\n'
path_NetFile = raw_input('Insert the path of the NET file. Format is \n'+'-- [PATH]/[name].NET:\t')
path_ucfFile = raw_input('Insert path of the ucf file. Format is \n'+'-- [PATH]/[name].ucf:\t')
path_excludedNetsFile = raw_input('Insert path of the file containing nets not to be included'+ '-- [PATH]/[name].XNET:\t')
ICid = raw_input('Insert which IC to get the ucf file from:\t')
net2ucf_inst = NET2UCF(path_NetFile, path_ucfFile, path_excludedNetsFile, ICid)
net2ucf_inst.generateUCF()
hdl/IMAGES/image1/constraints/V1/rs485.ucf deleted 100644 → 0
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hdl/IMAGES/image1/rtl/rs485_pkg.vhd deleted 100644 → 0
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library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bicolor_led_ctrl_pkg.ALL;
package rs485_pkg is
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
constant c_NB_ARRAY_LEDS : NATURAL := 12;
constant c_LED_INTENSITY : STD_LOGIC_VECTOR(6 downto 0) := "0011111";
--! Front array LEDs individual assignment
--! Pairings:
--! COLUMN t_led_state
--! 0 0 - 6
--! 1 1 - 7
--! 2 2 - 8
--! 3 3 - 9
--! 4 4 - 10
--! 5 5 - 11
constant c_LED_NB_WR_ADDR : NATURAL := 0;
constant c_LED_NB_WR_GMT : NATURAL := 1;
constant c_LED_NB_WR_LINK : NATURAL := 2;
constant c_LED_NB_WR_OK : NATURAL := 3;
constant c_LED_NB_MULTICAST0 : NATURAL := 4;
constant c_LED_NB_MULTICAST1 : NATURAL := 5;
constant c_LED_NB_I2C : NATURAL := 6;
constant c_LED_NB_TTL_N : NATURAL := 7;
constant c_LED_NB_ERR : NATURAL := 8;
constant c_LED_NB_PWR : NATURAL := 9;
constant c_LED_NB_MULTICAST2 : NATURAL := 10;
constant c_LED_NB_MULTICAST3 : NATURAL := 11;
constant c_LED_COLOR_PWR : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_ERR : STD_LOGIC_VECTOR(1 downto 0) := c_LED_RED;
constant c_LED_COLOR_TTL_N : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_I2C : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_OK : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_LINK : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_GMT : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST3 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST2 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST1 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST0 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
type t_leds_array_top is
record
PWR : STD_LOGIC;
ERR : STD_LOGIC;
TTL_N : STD_LOGIC;
I2C : STD_LOGIC;
end record;
type t_leds_array_middle is
record
WR_OK : STD_LOGIC;
WR_LINK : STD_LOGIC;
WR_GMT : STD_LOGIC;
WR_ADDR : STD_LOGIC;
end record;
type t_leds_array_bottom is
record
MULTICAST : UNSIGNED(3 downto 0);
end record;
type t_leds_array is
record
top : t_leds_array_top;
middle : t_leds_array_middle;
bottom : t_leds_array_bottom;
end record;
type t_led_state is
record
STATE : STD_LOGIC_VECTOR(1 downto 0);
end record;
type t_led_state_array is array(natural range <>) of t_led_state;
-- constant c_leds_array_top_default : t_leds_array_top := (PWR => '0',
-- ERR => '0',
-- TTL_N => '0',
-- I2C => '0');
--
-- constant c_leds_array_middle_default : t_leds_array_middle := (WR_OK => '0',
-- WR_LINK => '0',
-- WR_GMT => '0',
-- WR_ADDR => '0');
--
-- constant c_leds_array_bottom_default : t_leds_array_bottom := (MULTICAST
-- => (others => '0'));
constant c_NB_COLUMN : NATURAL := 6;
constant c_NB_LINE : NATURAL := 6;
component bicolor_led_ctrl is
generic(g_NB_COLUMN : NATURAL := c_NB_COLUMN;
g_NB_LINE : NATURAL := c_NB_LINE;
g_CLK_FREQ : NATURAL := 20000000; -- in Hz
g_REFRESH_RATE : NATURAL := 250); -- in Hz
port(rst_n_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
led_intensity_i : in STD_LOGIC_VECTOR(6 downto 0);
led_state_i : in STD_LOGIC_VECTOR(
(g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out STD_LOGIC_VECTOR(g_NB_COLUMN - 1 downto 0);
line_o : out STD_LOGIC_VECTOR( g_NB_LINE - 1 downto 0);
line_oen_o : out STD_LOGIC_VECTOR( g_NB_LINE - 1 downto 0));
end component;
component image1_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
end component;
function f_LED_STATE(state: STD_LOGIC_VECTOR(1 downto 0)) return t_led_state;
function f_STD_LOGIC_VECTOR(led_state : t_led_state) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(led_state_array : t_led_state_array)
return STD_LOGIC_VECTOR;
end rs485_pkg;
package body rs485_pkg is
--! @brief Translation function from STD_LOGIC_VECTOR to t_led_state
--! @param state LED state in STD_LOGIC_VECTOR format
function f_LED_STATE(state: STD_LOGIC_VECTOR(1 downto 0)) return t_led_state is
variable v_return : t_led_state;
begin
v_return.STATE(0) := state(0);
v_return.STATE(1) := state(1);
return v_return;
end f_LED_STATE;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state
--! @param led_state_array LED state in STD_LOGIC_VECTOR format
function f_STD_LOGIC_VECTOR(led_state : t_led_state)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(1 downto 0);
begin
v_return(0) := led_state.STATE(0);
v_return(1) := led_state.STATE(1);
return v_return;
end f_STD_LOGIC_VECTOR;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state_array
--! @param led_state_array LED array state in STD_LOGIC_VECTOR format
function f_STD_LOGIC_VECTOR(led_state_array : t_led_state_array)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(c_NB_COLUMN*c_NB_LINE - 1 downto 0);
variable v_led_state_tmp : t_led_state;
variable v_led_state_slv_tmp : STD_LOGIC_VECTOR(1 downto 0);
begin
for i in 0 to c_NB_COLUMN*c_NB_LINE - 1 loop
v_led_state_tmp := led_state_array(i);
v_led_state_slv_tmp := f_STD_LOGIC_VECTOR(v_led_state_tmp);
v_return(2*i + 1 downto 2*i) := v_led_state_slv_tmp;
end loop;
return v_return;
end f_STD_LOGIC_VECTOR;
end rs485_pkg;
hdl/IMAGES/image1/top/rs485_top.vhd deleted 100644 → 0
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----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description:
--
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.image1_pkg.ALL;
use work.rs485_pkg.ALL;
use work.bicolor_led_ctrl_pkg.ALL;
entity rs485_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := work.rs485_pkg.c_NUMBER_OF_CHANNELS);
port(FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
LED_CTRL0 : out STD_LOGIC;
LED_CTRL0_OEN : out STD_LOGIC;
LED_CTRL1 : out STD_LOGIC;
LED_CTRL1_OEN : out STD_LOGIC;
LED_MULTICAST_2_0 : out STD_LOGIC;
LED_MULTICAST_3_1 : out STD_LOGIC;
LED_WR_GMT_TTL_TTLN : out STD_LOGIC;
LED_WR_LINK_SYSERROR : out STD_LOGIC;
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_RS485_INA_TTL : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_RS485_INB_TTL : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_RTM : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
FPGA_OE : out STD_LOGIC;
FPGA_RS485_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
TTL_or_INV_TTL_N : in STD_LOGIC;
RST : in STD_LOGIC;
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
end rs485_top;
architecture Behavioral of rs485_top is
--! TODO: connect to Matthieu's LEDs IP core
signal s_leds_array_image1 : t_leds_array;
signal s_led_state_array : t_led_state_array(
c_NB_ARRAY_LEDS - 1 downto 0);
signal s_pulse_i_rear : STD_LOGIC_VECTOR(6 downto 1);
signal s_rst_n : STD_LOGIC := '0';
begin
-- g_rs485_inputs: for i in 1 to 6 generate
-- begin
-- inst_125m_IBUFDS : IBUFDS
-- generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => TRUE)
-- port map (O => s_pulse_i_rear(i), I => FPGA_RS485_INA_TTL(i),
-- IB => FPGA_RS485_INB_TTL(i));
-- end generate;
inst_image1_top: image1_top
generic map(g_NUMBER_OF_CHANNELS => g_NUMBER_OF_CHANNELS)
port map(FPGA_CLK_P => FPGA_CLK_P,
FPGA_CLK_N => FPGA_CLK_N,
led_pw_o => s_leds_array_image1.top.PWR,
led_err_o => s_leds_array_image1.top.ERR,
led_ttl_o => s_leds_array_image1.top.TTL_N,
led_o_front => PULSE_FRONT_LED_N,
led_o_rear => PULSE_REAR_LED,
pulse_i_front => FPGA_INPUT_TTL_N,
pulse_o_front => FPGA_OUT_TTL,
pulse_i_rear => FPGA_RS485_INA_TTL,
pulse_o_rear => FPGA_TRIG_RTM,
inv_i => INV_IN_N,
inv_o => INV_OUT,
SCL_I => SCL_I,
SCL_O => SCL_O,
SCL_OE => SCL_OE,
SDA_I => SDA_I,
SDA_O => SDA_O,
SDA_OE => SDA_OE,
FPGA_GA => FPGA_GA ,
FPGA_GAP => FPGA_GAP,
FPGA_PROM_CCLK => FPGA_PROM_CCLK,
FPGA_PROM_CSO_B_N => FPGA_PROM_CSO_B_N,
FPGA_PROM_DIN => FPGA_PROM_DIN,
FPGA_PROM_MOSI => FPGA_PROM_MOSI,
led_link_up_o => s_leds_array_image1.middle.WR_LINK,
led_pps_o => s_leds_array_image1.middle.WR_GMT,
led_wr_ok_o => s_leds_array_image1.middle.WR_OK,
fpga_o_en => FPGA_OE,
fpga_o_blo_en => FPGA_RS485_OE,
fpga_o_ttl_en => FPGA_TRIG_TTL_OE,
fpga_o_inv_en => FPGA_INV_OE,
level => TTL_or_INV_TTL_N,
switch_i => RST,
manual_rst_n_o => open, --! We don't have MR_N in RS485
FPGA_RTMM => FPGA_RTMM,
FPGA_RTMP => FPGA_RTMP);
--! Here are organized in the same disposition as in the front panel.
--! Take a look to rs485_pkg.vhd for the correct order for
--! bicolor_led_ctrl
s_led_state_array(c_LED_NB_PWR) <= f_LED_STATE(c_LED_COLOR_PWR)
when s_leds_array_image1.top.PWR = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_ERR) <= f_LED_STATE(c_LED_COLOR_ERR)
when s_leds_array_image1.top.ERR = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_TTL_N) <= f_LED_STATE(c_LED_COLOR_TTL_N)
when s_leds_array_image1.top.TTL_N = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_I2C) <= f_LED_STATE(c_LED_COLOR_I2C)
when s_leds_array_image1.top.I2C = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_OK) <= f_LED_STATE(c_LED_COLOR_WR_OK)
when s_leds_array_image1.middle.WR_OK = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_LINK) <= f_LED_STATE(c_LED_COLOR_WR_LINK)
when s_leds_array_image1.middle.WR_LINK = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_GMT) <= f_LED_STATE(c_LED_COLOR_WR_GMT)
when s_leds_array_image1.middle.WR_GMT = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_ADDR) <= f_LED_STATE(c_LED_COLOR_WR_ADDR)
when s_leds_array_image1.middle.WR_ADDR = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST3) <= f_LED_STATE(c_LED_COLOR_MULTICAST3)
when s_leds_array_image1.bottom.MULTICAST(3) = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST2) <= f_LED_STATE(c_LED_COLOR_MULTICAST2)
when s_leds_array_image1.bottom.MULTICAST(2) = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST1) <= f_LED_STATE(c_LED_COLOR_MULTICAST1)
when s_leds_array_image1.bottom.MULTICAST(1) = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST0) <= f_LED_STATE(c_LED_COLOR_MULTICAST0)
when s_leds_array_image1.bottom.MULTICAST(0) = '1'
else f_LED_STATE(c_LED_OFF);
s_rst_n <= not(RST);
inst_bicolor_led_ctrl: bicolor_led_ctrl
port map(rst_n_i => s_rst_n,
clk_i => CLK20_VCXO,
led_intensity_i => c_LED_INTENSITY,
led_state_i => f_STD_LOGIC_VECTOR(s_led_state_array),
column_o(0) => LED_WR_OWNADDR_I2C,
column_o(1) => LED_WR_GMT_TTL_TTLN,
column_o(2) => LED_WR_LINK_SYSERROR,
column_o(3) => LED_WR_OK_SYSPW,
column_o(4) => LED_MULTICAST_2_0,
column_o(5) => LED_MULTICAST_3_1,
line_o(0) => LED_CTRL0,
line_o(1) => LED_CTRL1,
line_oen_o(0) => LED_CTRL0_OEN,
line_oen_o(1) => LED_CTRL1_OEN);
end Behavioral;
pcb/EDA-02452-V1-0_project/EDA-02452-V1-0_project.Annotation deleted 100644 → 0
View file @ 5f043871
[DesignatorManager]
LogicalDesignator0=J2
LogicalPartID0=2
DocumentName0=RTMM_top.SchDoc
ChannelName0=RTMM_top
UniqueID0=\AIKNHLLQ
PhysicalDesignator0=J2
PhysicalDesignatorLocked0=0
LogicalDesignator1=D34
LogicalPartID1=1
DocumentName1=RTMM_top.SchDoc
ChannelName1=RTMM_top
UniqueID1=\ARILQPDB
PhysicalDesignator1=D34
PhysicalDesignatorLocked1=0
LogicalDesignator2=D30
LogicalPartID2=1
DocumentName2=RTMM_top.SchDoc
ChannelName2=RTMM_top
UniqueID2=\AUWLGUUK
PhysicalDesignator2=D30
PhysicalDesignatorLocked2=0
LogicalDesignator3=D29
LogicalPartID3=1
DocumentName3=RTMM_top.SchDoc
ChannelName3=RTMM_top
UniqueID3=\BESHNGMF
PhysicalDesignator3=D29
PhysicalDesignatorLocked3=0
LogicalDesignator4=D21
LogicalPartID4=1
DocumentName4=RTMM_top.SchDoc
ChannelName4=RTMM_top
UniqueID4=\BIKSFIKK
PhysicalDesignator4=D21
PhysicalDesignatorLocked4=0
LogicalDesignator5=D1
LogicalPartID5=1
DocumentName5=RTMM_top.SchDoc
ChannelName5=RTMM_top
UniqueID5=\BOTGBGKX
PhysicalDesignator5=D1
PhysicalDesignatorLocked5=0
LogicalDesignator6=D26
LogicalPartID6=1
DocumentName6=RTMM_top.SchDoc
ChannelName6=RTMM_top
UniqueID6=\BTGJOTTY
PhysicalDesignator6=D26
PhysicalDesignatorLocked6=0
LogicalDesignator7=D23
LogicalPartID7=1
DocumentName7=RTMM_top.SchDoc
ChannelName7=RTMM_top
UniqueID7=\BUEPTKMD
PhysicalDesignator7=D23
PhysicalDesignatorLocked7=0
LogicalDesignator8=D12
LogicalPartID8=1
DocumentName8=RTMM_top.SchDoc
ChannelName8=RTMM_top
UniqueID8=\CJGYSSKM
PhysicalDesignator8=D12
PhysicalDesignatorLocked8=0
LogicalDesignator9=D18
LogicalPartID9=1
DocumentName9=RTMM_top.SchDoc
ChannelName9=RTMM_top
UniqueID9=\CULATBYN
PhysicalDesignator9=D18
PhysicalDesignatorLocked9=0
LogicalDesignator10=D38
LogicalPartID10=1
DocumentName10=RTMM_top.SchDoc
ChannelName10=RTMM_top
UniqueID10=\DWTLOXUJ
PhysicalDesignator10=D38
PhysicalDesignatorLocked10=0
LogicalDesignator11=D47
LogicalPartID11=1
DocumentName11=RTMM_top.SchDoc
ChannelName11=RTMM_top
UniqueID11=\EIYRYWNU
PhysicalDesignator11=D47
PhysicalDesignatorLocked11=0
LogicalDesignator12=D42
LogicalPartID12=1
DocumentName12=RTMM_top.SchDoc
ChannelName12=RTMM_top
UniqueID12=\EQYLIJHI
PhysicalDesignator12=D42
PhysicalDesignatorLocked12=0
LogicalDesignator13=D46
LogicalPartID13=1
DocumentName13=RTMM_top.SchDoc
ChannelName13=RTMM_top
UniqueID13=\ERXXSLXY
PhysicalDesignator13=D46
PhysicalDesignatorLocked13=0
LogicalDesignator14=D8
LogicalPartID14=1
DocumentName14=RTMM_top.SchDoc
ChannelName14=RTMM_top
UniqueID14=\FGBHDNOJ
PhysicalDesignator14=D8
PhysicalDesignatorLocked14=0
LogicalDesignator15=D37
LogicalPartID15=1
DocumentName15=RTMM_top.SchDoc
ChannelName15=RTMM_top
UniqueID15=\FMVOKFPD
PhysicalDesignator15=D37
PhysicalDesignatorLocked15=0
LogicalDesignator16=D32
LogicalPartID16=1
DocumentName16=RTMM_top.SchDoc
ChannelName16=RTMM_top
UniqueID16=\GNUJXUCA
PhysicalDesignator16=D32
PhysicalDesignatorLocked16=0
LogicalDesignator17=D44
LogicalPartID17=1
DocumentName17=RTMM_top.SchDoc
ChannelName17=RTMM_top
UniqueID17=\GQXOHVQI
PhysicalDesignator17=D44
PhysicalDesignatorLocked17=0
LogicalDesignator18=D13
LogicalPartID18=1
DocumentName18=RTMM_top.SchDoc
ChannelName18=RTMM_top
UniqueID18=\GTSETWQN
PhysicalDesignator18=D13
PhysicalDesignatorLocked18=0
LogicalDesignator19=J2
LogicalPartID19=4
DocumentName19=RTMM_top.SchDoc
ChannelName19=RTMM_top
UniqueID19=\HDLFLVKI
PhysicalDesignator19=J2
PhysicalDesignatorLocked19=0
LogicalDesignator20=D33
LogicalPartID20=1
DocumentName20=RTMM_top.SchDoc
ChannelName20=RTMM_top
UniqueID20=\HEVQRKNM
PhysicalDesignator20=D33
PhysicalDesignatorLocked20=0
LogicalDesignator21=D39
LogicalPartID21=1
DocumentName21=RTMM_top.SchDoc
ChannelName21=RTMM_top
UniqueID21=\HNKDQNRV
PhysicalDesignator21=D39
PhysicalDesignatorLocked21=0
LogicalDesignator22=D35
LogicalPartID22=1
DocumentName22=RTMM_top.SchDoc
ChannelName22=RTMM_top
UniqueID22=\IHKKCEQJ
PhysicalDesignator22=D35
PhysicalDesignatorLocked22=0
LogicalDesignator23=D2
LogicalPartID23=1
DocumentName23=RTMM_top.SchDoc
ChannelName23=RTMM_top
UniqueID23=\JCIIIOVC
PhysicalDesignator23=D2
PhysicalDesignatorLocked23=0
LogicalDesignator24=D19
LogicalPartID24=1
DocumentName24=RTMM_top.SchDoc
ChannelName24=RTMM_top
UniqueID24=\JPCVJJBH
PhysicalDesignator24=D19
PhysicalDesignatorLocked24=0
LogicalDesignator25=D22
LogicalPartID25=1
DocumentName25=RTMM_top.SchDoc
ChannelName25=RTMM_top
UniqueID25=\KDEWEJUQ
PhysicalDesignator25=D22
PhysicalDesignatorLocked25=0
LogicalDesignator26=D16
LogicalPartID26=1
DocumentName26=RTMM_top.SchDoc
ChannelName26=RTMM_top
UniqueID26=\KDTJEJCJ
PhysicalDesignator26=D16
PhysicalDesignatorLocked26=0
LogicalDesignator27=J2
LogicalPartID27=3
DocumentName27=RTMM_top.SchDoc
ChannelName27=RTMM_top
UniqueID27=\KPFEUJQX
PhysicalDesignator27=J2
PhysicalDesignatorLocked27=0
LogicalDesignator28=D48
LogicalPartID28=1
DocumentName28=RTMM_top.SchDoc
ChannelName28=RTMM_top
UniqueID28=\LDJWCJKF
PhysicalDesignator28=D48
PhysicalDesignatorLocked28=0
LogicalDesignator29=J2
LogicalPartID29=5
DocumentName29=RTMM_top.SchDoc
ChannelName29=RTMM_top
UniqueID29=\LIOKQRAL
PhysicalDesignator29=J2
PhysicalDesignatorLocked29=0
LogicalDesignator30=D27
LogicalPartID30=1
DocumentName30=RTMM_top.SchDoc
ChannelName30=RTMM_top
UniqueID30=\LONOKABF
PhysicalDesignator30=D27
PhysicalDesignatorLocked30=0
LogicalDesignator31=D31
LogicalPartID31=1
DocumentName31=RTMM_top.SchDoc
ChannelName31=RTMM_top
UniqueID31=\NNGOYATV
PhysicalDesignator31=D31
PhysicalDesignatorLocked31=0
LogicalDesignator32=J3
LogicalPartID32=1
DocumentName32=RTMM_top.SchDoc
ChannelName32=RTMM_top
UniqueID32=\PEWJEQYV
PhysicalDesignator32=J3
PhysicalDesignatorLocked32=0
LogicalDesignator33=D5
LogicalPartID33=1
DocumentName33=RTMM_top.SchDoc
ChannelName33=RTMM_top
UniqueID33=\PFJOKYWD
PhysicalDesignator33=D5
PhysicalDesignatorLocked33=0
LogicalDesignator34=D15
LogicalPartID34=1
DocumentName34=RTMM_top.SchDoc
ChannelName34=RTMM_top
UniqueID34=\PHQTLMHH
PhysicalDesignator34=D15
PhysicalDesignatorLocked34=0
LogicalDesignator35=D25
LogicalPartID35=1
DocumentName35=RTMM_top.SchDoc
ChannelName35=RTMM_top
UniqueID35=\RJIFTCES
PhysicalDesignator35=D25
PhysicalDesignatorLocked35=0
LogicalDesignator36=D14
LogicalPartID36=1
DocumentName36=RTMM_top.SchDoc
ChannelName36=RTMM_top
UniqueID36=\RMNEIKUT
PhysicalDesignator36=D14
PhysicalDesignatorLocked36=0
LogicalDesignator37=D24
LogicalPartID37=1
DocumentName37=RTMM_top.SchDoc
ChannelName37=RTMM_top
UniqueID37=\RMORNHPP
PhysicalDesignator37=D24
PhysicalDesignatorLocked37=0
LogicalDesignator38=D3
LogicalPartID38=1
DocumentName38=RTMM_top.SchDoc
ChannelName38=RTMM_top
UniqueID38=\RSRKASJV
PhysicalDesignator38=D3
PhysicalDesignatorLocked38=0
LogicalDesignator39=D11
LogicalPartID39=1
DocumentName39=RTMM_top.SchDoc
ChannelName39=RTMM_top
UniqueID39=\RYTAQFOT
PhysicalDesignator39=D11
PhysicalDesignatorLocked39=0
LogicalDesignator40=D7
LogicalPartID40=1
DocumentName40=RTMM_top.SchDoc
ChannelName40=RTMM_top
UniqueID40=\SCJESUPU
PhysicalDesignator40=D7
PhysicalDesignatorLocked40=0
LogicalDesignator41=D20
LogicalPartID41=1
DocumentName41=RTMM_top.SchDoc
ChannelName41=RTMM_top
UniqueID41=\SJXTFVSM
PhysicalDesignator41=D20
PhysicalDesignatorLocked41=0
LogicalDesignator42=J2
LogicalPartID42=6
DocumentName42=RTMM_top.SchDoc
ChannelName42=RTMM_top
UniqueID42=\SMVHFCPX
PhysicalDesignator42=J2
PhysicalDesignatorLocked42=0
LogicalDesignator43=D9
LogicalPartID43=1
DocumentName43=RTMM_top.SchDoc
ChannelName43=RTMM_top
UniqueID43=\ULRJYSXE
PhysicalDesignator43=D9
PhysicalDesignatorLocked43=0
LogicalDesignator44=D40
LogicalPartID44=1
DocumentName44=RTMM_top.SchDoc
ChannelName44=RTMM_top
UniqueID44=\UQNCUFPM
PhysicalDesignator44=D40
PhysicalDesignatorLocked44=0
LogicalDesignator45=D43
LogicalPartID45=1
DocumentName45=RTMM_top.SchDoc
ChannelName45=RTMM_top
UniqueID45=\VCXBFDTT
PhysicalDesignator45=D43
PhysicalDesignatorLocked45=0
LogicalDesignator46=D36
LogicalPartID46=1
DocumentName46=RTMM_top.SchDoc
ChannelName46=RTMM_top
UniqueID46=\VIXHMSEJ
PhysicalDesignator46=D36
PhysicalDesignatorLocked46=0
LogicalDesignator47=D41
LogicalPartID47=1
DocumentName47=RTMM_top.SchDoc
ChannelName47=RTMM_top
UniqueID47=\VLJKINPI
PhysicalDesignator47=D41
PhysicalDesignatorLocked47=0
LogicalDesignator48=D17
LogicalPartID48=1
DocumentName48=RTMM_top.SchDoc
ChannelName48=RTMM_top
UniqueID48=\WEPVQBOG
PhysicalDesignator48=D17
PhysicalDesignatorLocked48=0
LogicalDesignator49=J2
LogicalPartID49=1
DocumentName49=RTMM_top.SchDoc
ChannelName49=RTMM_top
UniqueID49=\XAUGDADD
PhysicalDesignator49=J2
PhysicalDesignatorLocked49=0
LogicalDesignator50=D10
LogicalPartID50=1
DocumentName50=RTMM_top.SchDoc
ChannelName50=RTMM_top
UniqueID50=\XIYLTFLN
PhysicalDesignator50=D10
PhysicalDesignatorLocked50=0
LogicalDesignator51=D6
LogicalPartID51=1
DocumentName51=RTMM_top.SchDoc
ChannelName51=RTMM_top
UniqueID51=\XWNWNGKX
PhysicalDesignator51=D6
PhysicalDesignatorLocked51=0
LogicalDesignator52=D28
LogicalPartID52=1
DocumentName52=RTMM_top.SchDoc
ChannelName52=RTMM_top
UniqueID52=\YDRFLWOK
PhysicalDesignator52=D28
PhysicalDesignatorLocked52=0
LogicalDesignator53=D4
LogicalPartID53=1
DocumentName53=RTMM_top.SchDoc
ChannelName53=RTMM_top
UniqueID53=\YJEYJBYL
PhysicalDesignator53=D4
PhysicalDesignatorLocked53=0
LogicalDesignator54=D45
LogicalPartID54=1
DocumentName54=RTMM_top.SchDoc
ChannelName54=RTMM_top
UniqueID54=\YMCDSYUA
PhysicalDesignator54=D45
PhysicalDesignatorLocked54=0
[SheetNumberManager]
SheetNumberOrder=Display Order
SheetNumberMethod=Increasing
pcb/EDA-02494-V1-0_project/EDA-02494-V1-0_project.PrjPCBStructure deleted 100644 → 0
View file @ 5f043871
Record=SheetSymbol|SourceDocument=RTMP_top.SchDoc|Designator=U_Panel|SchDesignator=U_Panel|FileName=Panel.SchDoc|SymbolType=Normal|RawFileName=Panel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=RTMP_top.SchDoc|Designator=U_SqConnector|SchDesignator=U_SqConnector|FileName=SqConnector.SchDoc|SymbolType=Normal|RawFileName=SqConnector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=RTMP_top.SchDoc
pcb/EDA-02494-V2-0_project/EDA-02494-V1-0_project.PrjPCBStructure deleted 100644 → 0
View file @ 5f043871
Record=SheetSymbol|SourceDocument=RTMP_top.SchDoc|Designator=U_Panel|SchDesignator=U_Panel|FileName=Panel.SchDoc|SymbolType=Normal|RawFileName=Panel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=RTMP_top.SchDoc|Designator=U_SqConnector|SchDesignator=U_SqConnector|FileName=SqConnector.SchDoc|SymbolType=Normal|RawFileName=SqConnector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=RTMP_top.SchDoc
pcb/EDA-02541-V1-0_project/EDA-02541-V1-0_project.PrjPCBStructure deleted 100644 → 0
View file @ 5f043871
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_Clocks&Monitor|SchDesignator=U_Clocks&Monitor|FileName=Clocks&Monitor.SchDoc|SymbolType=Normal|RawFileName=Clocks&Monitor.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_Communication|SchDesignator=U_Communication|FileName=Communication.SchDoc|SymbolType=Normal|RawFileName=Communication.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_FPGAbank|SchDesignator=U_FPGAbank|FileName=FPGAbank.SchDoc|SymbolType=Normal|RawFileName=FPGAbank.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_FrontPanelLeds|SchDesignator=U_FrontPanelLeds|FileName=FrontPanelLeds.SchDoc|SymbolType=Normal|RawFileName=FrontPanelLeds.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_FrontTTL|SchDesignator=U_FrontTTL|FileName=FrontTTL.SchDoc|SymbolType=Normal|RawFileName=FrontTTL.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_Input RS485|SchDesignator=U_Input RS485|FileName=Input RS485.SchDoc|SymbolType=Normal|RawFileName=Input RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_JTAG&Button|SchDesignator=U_JTAG&Button|FileName=JTAG&Button.SchDoc|SymbolType=Normal|RawFileName=JTAG&Button.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_Output RS485|SchDesignator=U_Output RS485|FileName=Output RS485.SchDoc|SymbolType=Normal|RawFileName=Output RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_PowerSupply|SchDesignator=U_PowerSupply|FileName=PowerSupply.SchDoc|SymbolType=Normal|RawFileName=PowerSupply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=convTTLrs485_TOP.SchDoc|Designator=U_VME64xConn|SchDesignator=U_VME64xConn|FileName=VME64xConn.SchDoc|SymbolType=Normal|RawFileName=VME64xConn.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Input RS485.SchDoc|Designator=U_Input Unit RS485_1|SchDesignator=U_Input Unit RS485_1|FileName=Input Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Input Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Input RS485.SchDoc|Designator=U_Input Unit RS485_2|SchDesignator=U_Input Unit RS485_2|FileName=Input Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Input Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Input RS485.SchDoc|Designator=U_Input Unit RS485_3|SchDesignator=U_Input Unit RS485_3|FileName=Input Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Input Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Input RS485.SchDoc|Designator=U_Input Unit RS485_4|SchDesignator=U_Input Unit RS485_4|FileName=Input Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Input Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Input RS485.SchDoc|Designator=U_Input Unit RS485_5|SchDesignator=U_Input Unit RS485_5|FileName=Input Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Input Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Input RS485.SchDoc|Designator=U_Input Unit RS485_6|SchDesignator=U_Input Unit RS485_6|FileName=Input Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Input Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Output RS485.SchDoc|Designator=U_Output Unit RS485_1|SchDesignator=U_Output Unit RS485_1|FileName=Output Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Output Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Output RS485.SchDoc|Designator=U_Output Unit RS485_2|SchDesignator=U_Output Unit RS485_2|FileName=Output Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Output Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Output RS485.SchDoc|Designator=U_Output Unit RS485_3|SchDesignator=U_Output Unit RS485_3|FileName=Output Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Output Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Output RS485.SchDoc|Designator=U_Output Unit RS485_4|SchDesignator=U_Output Unit RS485_4|FileName=Output Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Output Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Output RS485.SchDoc|Designator=U_Output Unit RS485_5|SchDesignator=U_Output Unit RS485_5|FileName=Output Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Output Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=Output RS485.SchDoc|Designator=U_Output Unit RS485_6|SchDesignator=U_Output Unit RS485_6|FileName=Output Unit RS485.SchDoc|SymbolType=Normal|RawFileName=Output Unit RS485.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=convTTLrs485_TOP.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC15|DocumentName=FPGAbank.SchDoc|LibraryReference=XC6SLX45T-3FGG484C|SubProjectPath= |Configuration= |Description=Spartan-6 LXT 1.2V FPGA, 296 User I/Os, 484-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 3, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX45T-3FGG484C|SubPartUniqueId1=LXCCBOAQ|SubPartDocPath1=FPGAbank.SchDoc|SubPartUniqueId2=SQRPFNCU|SubPartDocPath2=FPGAbank.SchDoc|SubPartUniqueId3=UWEVCIXJ|SubPartDocPath3=FPGAbank.SchDoc|SubPartUniqueId4=YAMRVFRC|SubPartDocPath4=FPGAbank.SchDoc|SubPartUniqueId5=CDCOBMPD|SubPartDocPath5=Communication.SchDoc|SubPartUniqueId6=QHEAESDF|SubPartDocPath6=JTAG&Button.SchDoc|SubPartUniqueId7=UWPWENEI|SubPartDocPath7=PowerSupply.SchDoc|SubPartUniqueId8=NRHFJTEU|SubPartDocPath8=PowerSupply.SchDoc|SubPartUniqueId9=LYONHVRY|SubPartDocPath9=JTAG&Button.SchDoc
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LAYOUT NOTES
POSITIONING/LAYOUT OF THE COMPONENTS
** 5V and 3V3 POWER SUPPLY PI FILTERS
The pi filters are a little bit bulky due to the OSCON capacitor. Most of the
power lines from VME are in the lower part of P1 connector, so the snippets can
be placed in between P1 and P2, respecting the spacing to the end of the board
(better if OSCONs are not the closest capacitors to the border, because they
can get accidentally damaged due to its bigger height).
Small pi filters for HS lines should be placed as close as possible to their
respective ICs.
** POWER SUPPLY
This design only has a switching power supply. Recommended layout from Texas can
be found in the datasheet and it should be followed. If better layout can be
done, do not hesitate to tell! :-)
The 3V3_VME net is located in P1 connector. This is the net that, after the pi
filter, will offer the power to the input of thee switching power supplies. So,
the PS should be positioned in the upper mid part of the VME board.
** I2C and VME GA pins
This board is not using VME bus. Instead is only underlying in SERA, SERB pins
from VME64x standard.
The buffer for these two lines should be placed close to P1 connector.
** RS485 DRIVERS
This board is intended to be used together with a separate second board.
This additional board, namely a Rear Transition Module, will be connected in
the rear part of a VME crate and will interconnect lines with the Front VME
board via P2 connector.
The lines connected by the P2 connector will be the RS485 I/O lines. Hence,
all the RS485 drivers must be placed in the lower mid part of the double height
VME board.
** FPGA
Pin swapping can be performed in most of the FPGA. Do not do pin swapping in
PROM lines. If clock lines are moved please assign it to GLCK pins.
** EXTERNAL PLL
Better if this part is positioned away from the RS485 drivers. It can be placed
as in CONV-TTL-BLO in the upper part inbetween SFP connector and FPGA.
Same for the the DACs fetched into it.
** FLASH MEMORY
The closer to FPGA, the better.
** FRONT PANEL
If possible, it should be placed the SFP connector and the double LEMOs in
exactly the same fashion.
For the LEDs, three rows of LEDs will be placed in the upper part of the board.
The first LED out of four in the pack must be the one that goes closer to the
board.
Starting from the top, the first row corresponds to LED_SYS_PW_N, the second one
to LED_MULTICAST1_N and the third one to LED_WR_OWN_ADDR_N
** SWITCHES
There are two micro-switches:
- 8 switch: applies serigraphie for individual switch.
- 4 switch: it should have serigraphie with "MULTICAST ADDR" and markings "MSB"
and "LSB"
** SERIGRAPHIE
Please, do not put CERN logo. Instead put
"http://www.ohwr.org/projects/conv-ttl-rs485/"
"Conv-TTL-RS485"
"[EDA number]"
LAYERS
It should fit in a six layers board.
HS LINES
The ones of the clocking resources and the FPGA MGT. MGTRREF must be equalized
as it is specified by Spartan 6 layout notes.
FRONT PANEL
It must follow a similar design to CONV-TTL-BLO front panel with the exception
of the top three rows of LEDs.
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