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Conv TTL RS485
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Conv TTL RS485
Commits
8b74588b
Commit
8b74588b
authored
Aug 20, 2014
by
Theodor-Adrian Stana
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doc: Add SDB descriptor to memory map
parent
fad5b210
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conv-ttl-rs485-gw
conv-ttl-rs485-gw
+1
-1
ug-conv-ttl-rs485.bib
doc/ug/ug-conv-ttl-rs485.bib
+12
-0
ug-conv-ttl-rs485.tex
doc/ug/ug-conv-ttl-rs485.tex
+37
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conv-ttl-rs485-gw
@
7d1f4ea8
Subproject commit
c1f2d83b47ec44058c303d409ac20fca6402b878
Subproject commit
7d1f4ea8c3ee1ef3af25e7981208891a53fc91e6
doc/ug/ug-conv-ttl-rs485.bib
View file @
8b74588b
...
...
@@ -58,3 +58,15 @@
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{sdb,
title = {{SDB specification v1.1}},
howpublished = {\url{http://www.ohwr.org/documents/256}}
}
@misc{onewire-core,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
doc/ug/ug-conv-ttl-rs485.tex
View file @
8b74588b
...
...
@@ -9,8 +9,8 @@
% Hyperrefs
\usepackage
[
colorlinks = true,
linkcolor =
Mahogany
,
citecolor =
Mahogany
,
linkcolor =
black
,
citecolor =
black
,
urlcolor = blue,
]
{
hyperref
}
...
...
@@ -1045,7 +1045,7 @@ $reg. index = \frac{addr}{4} + 1$
\end
{
center
}
\begin
{
table
}
[
h
]
\caption
{
CONV
-
TTL
-
RS
485
memory map
}
\caption
{
\textit
{
conv
\_
common
\_
gw
}
memory map
}
\label
{
tbl:memmap
}
\centerline
{
...
...
@@ -1055,8 +1055,8 @@ $reg. index = \frac{addr}{4} + 1$
\multicolumn
{
1
}{
c
}{
\textbf
{
Peripheral
}}
&
\multicolumn
{
2
}{
c
}{
\textbf
{
Address range
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
Board registers
&
0
x
000
&
0
x
0
ff
&
Coverter board registers
\\
MultiBoot
&
0
x
100
&
0
x
01
f
&
MultiBoot module
\\
% Thermometer & 0x080 & 0x084 & Thermometer chip
\\
MultiBoot
&
0
x
100
&
0
x
110
&
MultiBoot module
\\
SDB descriptor
&
0
xf
00
&
0
xfff
&
SDB descriptor
(
see~
\cite
{
sdb
}
)
\\
\hline
\end
{
tabular
}
}
...
...
@@ -1072,6 +1072,38 @@ $reg. index = \frac{addr}{4} + 1$
%------------------------------------------------------------------------------
\include
{
multiboot
-
regs
}
%%------------------------------------------------------------------------------
%% SUBSEC: Thermo
%%------------------------------------------------------------------------------
%\subsection{Thermometer module}
%\label{app:memmap-thermo}
%
%\indent Base address: 0x080
%
%\vspace*{11pt}
%
%\centerline
%{
% \rowcolors{2}{white}{gray!25}
% \begin{tabular}{l l l p{.5\textwidth}}
% \hline
% \textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
% \hline
% 0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
% 0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
% \hline
% \end{tabular}
%}
%
%\vspace*{11pt}
%
%For details on the bits of the thermometer module access registers, see the
%OneWire Master module's documentation~\cite{onewire-core}.
%
%Note that the OWCDR should be set accordingly for proper functioning of the
%one-wire timings. The value for the current version of the gateware is
%\verb-OWCDR = 0x00130063-.
%======================================================================================
\end
{
appendices
}
%======================================================================================
...
...
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