Commit 3c4cc4ba authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Merge branch 'proposed-master'

parents c40f87f2 c1d3b6a1
*.~*
doc/ug/fig/*.pdf
......@@ -6,4 +6,4 @@
url = git@ohwr.org:level-conversion/conv-ttl-rs485/conv-ttl-rs485-tst.git
[submodule "conv-ttl-rs485-gw"]
path = conv-ttl-rs485-gw
url = git://ohwr.org/level-conversion/conv-ttl-rs485/conv-ttl-rs485-gw.git
url = git@ohwr.org:level-conversion/conv-ttl-rs485/conv-ttl-rs485-gw.git
conv-ttl-rs485-gw @ d81130fe
Subproject commit 5f388feae52b22e6214842e2e29682a52c879dc8
Subproject commit d81130fe94bcd6b340a6495dbebdb67a7fb4e187
conv-ttl-rs485-hw @ 12438280
Subproject commit f2a158f7236a4d40de093f1f26068889e7f88bbf
Subproject commit 124382804cd2d9c6d0000c868ec908d86cb4ea79
conv-ttl-rs485-tst @ 2cf50e56
Subproject commit 987fa158711bf2978200bb14e1d3d61fb8d744c7
Subproject commit 2cf50e5632d77374afaf99004e80636c18894a1b
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 22, 2015
\hfill August 29, 2018
\vspace*{3cm}
......@@ -24,7 +24,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}
\noindent \rule{\textwidth}{.05cm}
......
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howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{conv-ttl-rtm-rs485-db9-ohwr,
title = {{CONV-TTL-RTM-RS485-DB9 Wiki Page on OHWR}},
howpublished = {\url{https://www.ohwr.org/projects/conv-ttl-rs485-hw/wiki/DB9-RTM}}
}
@misc{conv-rs485-rtm-opt-ohwr,
title = {{CONV-RS485-OPT-RTM Project Page on OHWR}},
howpublished = {\url{https://www.ohwr.org/projects/conv-rs485-opt-rtm/wiki/wiki}}
}
@misc{conv-ttl-rs485-ohwr,
title = {{CONV-TTL-RS485 Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{conv-ttl-rs485-gw-releases,
title = {{CONV-TTL-RS485 Gateware Releases Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485-gw/wiki/Releases}}
......@@ -18,6 +33,11 @@
howpublished = {\url{http://www.ohwr.org/documents/389}}
}
@misc{conv-rs485-opt-rtm-hwg,
title = {{CONV-RS485-OPT-RTM Hardware Guide on OHWR}},
howpublished = {\url{https://www.ohwr.org/documents/757}}
}
@misc{conv-ttl-rs485-sch,
title = {{CONV-TTL-RS485 on CERN EDMS}},
howpublished = {\url{https://edms.cern.ch/nav/EDA-02541}}
......@@ -43,8 +63,8 @@
}
@misc{m25p32,
title = {{M25P32 32Mb 3V NOR Serial Flash Embedded Memory}},
howpublished = {\url{http://cern.ch/go/vSq8}}
title = {{MX25L3233F 32Mb 3V NOR Serial Flash Embedded Memory}},
howpublished = {\url{http://cern.ch/go/7BfN}}
}
@misc{ug380,
......@@ -67,3 +87,9 @@
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{ds18b20,
author = {{Maxim Integrated}},
title = {{DS18B20 -- Programmable Resolution 1-Wire Digital Thermometer}},
note = {\url{http://datasheets.maximintegrated.com/en/ds/DS18B20.pdf}}
}
\ No newline at end of file
......@@ -80,6 +80,7 @@ work, see \\
addition of how to read gateware version in Section~\ref{sec:reprog-bitstreams} \\
22-01-2015 & 2.0 & Added changes for V3 front module boards, sections on advanced diagnostics and
referred to gateware guide for specific gateware versions in the Memory Map Appendix \\
15-12-2017 & 3.0 & Added changes for V4 front module boards\\
\hline
\end{tabular}
}
......@@ -123,34 +124,65 @@ work, see \\
\section{Introduction}
\label{sec:intro}
CONV-TTL-RS485 is an open hardware design \cite{ohwr} intended for replicating TTL and RS-485
pulses, or for timing distribution. The main features of the board are:
CONV-TTL-RS485 is an open hardware design \cite{ohwr} intended for replicating TTL, RS-485 and optical
pulses. The main application for this system at CERN would be for General Machine Timing (GMT) frame
distribution. The main features of the board are:
\begin{itemize}
\item VME64x form-factor
\item Possibility to use as timing repeater card
\item Six independent pulse replication channels, each channel capable of replicating
\item Possibility to use two supported Rear Transition Modules (RTMs) at the back
\begin{itemize}
\item \textbf{CONV-TTL-RS485-RTM-DB9} \cite{conv-ttl-rtm-rs485-db9-ohwr} 2-Channel, RS-485 signal repeaters, each with 1 input and 5 outputs. This RTM uses D-Sub9 connectors.
\item \textbf{CONV-RS485-OPT-RTM} \cite{conv-rs485-rtm-opt-ohwr} 3-Channel Optical outputs each with 1 input and 2 outputs. This RTM uses ST connectors.
\textit{Note: A design exists with 6-Channel RS-485 outputs with LEMO 0S (2-pin)
connectors, each with one input and 3 outputs.
\textbf{However this design is no longer supported and no productions have
been made of this configuration}. Therefore it will not be discussed further in this document.}
\end{itemize}
\item Independent pulse replication channels, each channel capable of replicating
\begin{itemize}
\item TTL to TTL
\item With CONV-TTL-RS485 motherboard - 6 Channels with:
\begin{itemize}
\item TTL to TTL
\item TTL-BAR to TTL-BAR
\end{itemize}
\item Four general-purpose inverter channels, for conversion from TTL to TTL-BAR and vice versa
\item CONV-TTL-RS485 motherboard with CONV-TTL-RTM-RS485-DB9 board - 2 Channels with:
\begin{itemize}
\item TTL to RS-485
\item TTL-BAR to TTL-BAR
\item TTL-BAR to RS-485
\item RS-485 to TTL
\item RS-485 to TTL-BAR
\item RS-485 to RS-485
\end{itemize}
\item CONV-TTL-RS485 motherboard with CONV-RS485-OPT-RTM board - 3 Channels with:
\begin{itemize}
\item TTL to Optical
\item TTL-BAR to Optical
\item Optical to TTL
\item Optical to TTL-BAR
\item Optical to Optical
\end{itemize}
\end{itemize}
\item Four general-purpose inverter channels, for conversion from TTL to TTL-BAR and viceversa
\item Each TTL and inverter channel has 50~$\Omega$ input termination
\item Each TTL and inverter channel capable of driving 50~$\Omega$ load
\item Each RS-485 channel capable of driving up to 256 nodes
\item Each RS-485 channel contains lack of signal detection logic
\item Each RS-485 channel has optional input or output 100~$\Omega$ termination
\item Diagnostics
\begin{itemize}
\item converter board ID
\item hardware version
\item gateware version
\item state of on-board switches and RTM detection lines
\item state of on-board switches and RTM detection/ID lines
\item line state at board input
\item input pulse counters
\item input pulse counters for front and rear pulses (TTL or RS-485/optical)
\item input pulse time-stamping with dedicated per-channel latest timestamp
readout
\item manual pulse triggering
......@@ -163,10 +195,14 @@ pulses, or for timing distribution. The main features of the board are:
\end{itemize}
Pulse conversion is obtained by combining the CONV-TTL-RS485 front module (FM) board
with a CONV-TTL-RTM rear-transition module (RTM) together with an attached
CONV-TTL-RTM-RS485 piggyback board, as shown in Figure~\ref{fig:conv-sys-bd}.
with of the two rear-transition modules (RTM), as shown in Figure~\ref{fig:conv-sys-bd} for the D-Sub9 vesion of the RTM.
In this case, a pulse on a channel's input on any side (TTL on the FM side or RS-485 on the
RTM side) is replicated on both the FM and the RTM outputs for the channel.
RTM side) is replicated on both the FM and the RTM outputs for the channel.\\
\emph{\textbf{Note that this motherboard can support RTMs with up to 6 RS-485 channels,
with typically one input port and three outputs. However the custom RTM CONV-TTL-RS485-RTM-DB9, with only 2
RS-485 channels, each having 1 input and 5 outputs, using D-Sub9 connectors, is
recommended for CERN applications}}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/conv-sys-bd}}
......@@ -180,6 +216,8 @@ RTM side) is replicated on both the FM and the RTM outputs for the channel.
\begin{itemize}
\item CONV-TTL-RS485 OHWR Wiki page~\cite{conv-ttl-rs485-ohwr}
\item CONV-TTL-RS485-RTM-DB9 OHWR Wiki page~\cite{conv-ttl-rtm-rs485-db9-ohwr}
\item CONV-RS485-OPT-RTM OHWR Wiki page~\cite{conv-rs485-rtm-opt-ohwr}
\item CONV-TTL-RS485 schematics~\cite{conv-ttl-rs485-sch}
\item CONV-TTL-RS485 HDL Guide~\cite{conv-ttl-rs485-hdlg}
\end{itemize}
......@@ -191,12 +229,13 @@ RTM side) is replicated on both the FM and the RTM outputs for the channel.
\section{Front and rear panels}
\label{sec:front-rear-panel}
Two panels exist in the context of the RS-485 pulse repeater boards. The first of these is the
Three panels exist in the context of the RS-485 pulse repeater boards. The first of these is the
\textit{front panel}, which corresponds to FM boards, contains various connectors
for TTL-level pulses and the SFP connector, as well as various status LEDs. The second is
the \textit{rear panel}, located on the other side of the VME backplane and corresponding
to the RTM boards. The rear panel offers RS-485 LEMO0S connectors and status
LEDs for pulse replication confirmation.
for TTL-level pulses and the SFP connector, as well as various status LEDs. The other two are
the \textit{rear panels}, located on the other side of the VME backplane and corresponding
to the RTM boards CONV-TTL-RS485-RTM-DB9 and CONV-RS485-OPT-RTM.
The rear panel offers signal repetition in RS-485 or optical signaling,
see section~\ref{sec:rp} , and status LEDs for pulse replication confirmation.
%--------------------------------------------------------------------------------------
% SUBSEC: Front panel
......@@ -262,14 +301,16 @@ Section~\ref{sec:pulse-ttl-vs-ttlbar}).
A simplified diagram of pulse repetition is shown in Figure~\ref{fig:ttl-chan},
more details can be found in Section~\ref{sec:pulse-rep}. If a TTL (TTL-BAR) pulse arrives
on a channel input, it is regenerated on the output of the same channel in TTL (TTL-BAR),
as well as the RS-485 outputs of the same channel on the rear panel, if an RTM board with
an attached RS-485 piggyback is present. Similarly, if an RS-485 pulse arrives on the rear
panel, it is replicated on the TTL output channel.
as well as the outputs of the same channel on the rear panel, if an RTM board with
an attached RS-485 piggyback is present (only on CONV-TTL-RS485-RTM-DB9 also known as the copper RTM),
or alternatively the compatible optical RTM.
Similarly, if a pulse arrives on the rear
panel (RS-485 or optical), it is replicated on the TTL output channel.
Each TTL replication channel has a pulse LED which flashes shortly whenever a pulse is replicated
Each TTL replication channel has a pulse LED which flashes for a short time whenever a pulse is replicated
on the channel.
All TTL input channels are terminated with 50$\Omega$ resistors; TTL output channels are
All TTL input channels are terminated with 50~$\Omega$ resistors; TTL output channels are
not terminated.
\begin{figure}[h]
......@@ -282,11 +323,11 @@ not terminated.
\subsubsection{General-purpose inverters}
Four general-purpose TTL inverter channels can be found in the lower part of the front panel.
The output of a channel is always an inverted version of the channel input (Figure~\ref{fig:invttl-chan}).
No regeneration is performed on the input signal, nor is it in any way connected to the RS-485 outputs
No regeneration is performed on the input signal, nor is it in any way connected to the RS-485/optical outputs
on the RTM. The input signal is simply passed through an inverter and the FPGA, and presented at the
channel output.
Each INV-TTL channel has one LED which flashes shortly on every falling edge of the input
Each INV-TTL channel has one LED which flashes for a short time on every falling edge of the input
signal.
All general-purpose inputs are terminated with 50$\Omega$ resistors; the outputs are not
......@@ -304,36 +345,48 @@ terminated.
\subsection{Rear panel}
\label{sec:rp}
The rear panel on CONV-TTL-RTM-RS485 boards is shown in Figure~\ref{fig:rear-panel}. It contains the
input and output connectors, as well as pulse status LEDs for the six RS-485 pulse channels. An RS-485
pulse at the input connector of a channel is passed through the FPGA and regenerated at the three outputs
\begin{figure}[h]
\centerline{\includegraphics[scale=.83]{fig/rear-panel-db9}}
\caption{Rear panel - D-Sub9 RTM}
\label{fig:rear-panel-db9}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[scale=.83]{fig/rear-panel-opt}}
\caption{Rear panel - Optical RTM}
\label{fig:rear-panel-db9}
\end{figure}
The rear panel of the compatible RTM boards are shown in Figures~\ref{fig:rear-panel-db9}
and~\ref{fig:rear-panel-db9}.
For the CONV-TTL-RTM-RS485-DB9, the rear panel consists of the
input and output connectors, as well as pulse status LEDs for each RS-485 pulse channels. An RS-485
pulse at the input connector of a channel is passed through the FPGA and regenerated at the five outputs
of the same channel in RS-485 level, as well as in TTL level at the output connector of the corresponding
TTL channel on the front panel.
With the optical version of the RTM, a single column of 9 ST connectors,
offering 3 I/O channels each with 1 input and 2 outputs, in addition to a pulse status LED, see Fig.~\ref{fig:rear-panel-db9}. For this board, optical pulses are received and transmitted using appropriate optical transceivers. These optical signals are then translated to RS-485 and sent on to the system motherboard through the VME P2 connector. From then on, the signal is treated on the motherboard in the same way as one coming from the copper RTM. The hardware guide~\cite{conv-rs485-opt-rtm-hwg} for this specific RTM contains further details on its hardware implementation.
\begin{figure}[h]
\centerline{\includegraphics[scale=.83]{fig/rear-panel}}
\caption{Rear panel}
\label{fig:rear-panel}
\centerline{\includegraphics[width=.8\textwidth]{fig/oterm}}
\caption{\label{fig:oterm} Output termination enable}
\end{figure}
Each RS-485 output on a channel has its dedicated transceiver capable of driving 256 nodes. Additionally,
\subsection{Input and output termination }
On the motherboard, each RS-485 output on a channel has its dedicated transceiver capable of driving 256 nodes. Additionally,
each input and output channel has a selectable 100~$\Omega$ termination, which can be enabled by the
input and output termination switches (see Section~\ref{sec:switches}). Setting the input or output
termination enable switch to the ON position enables a connection via a solid-state relay, which in turns
enables the termination connection as shown in Figures~\ref{fig:oterm}~and~\ref{fig:iterm}.
Finally, when a pulse is repeated on the output connector of a channel, the pulse status LED flashes briefly.
\begin{figure}[h]
\centerline{\includegraphics[width=.8\textwidth]{fig/oterm}}
\caption{\label{fig:oterm} Output termination enable}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=.8\textwidth]{fig/iterm}}
\caption{\label{fig:iterm} Input termination enable}
\end{figure}
%======================================================================================
% SEC: Switches
%======================================================================================
......@@ -347,15 +400,15 @@ board's multicast address.
Figure~\ref{fig:switches} shows the switches and Table~\ref{tbl:switches} lists the used ones.
Note that all switches in Table~\ref{tbl:switches} are board-wide switches; selecting
one position or the other yields a selection valid for all six pulse replication channels.
one position or the other yields a selection valid for all available pulse replication channels.
\begin{figure}[h]
\begin{figure}
\centerline{\includegraphics[width=.55\textwidth]{fig/switches}}
\caption{Switches on the CONV-TTL-RS485 board}
\label{fig:switches}
\end{figure}
\begin{table}[htbp]
\begin{table}[h]
\caption{General-purpose switches on CONV-TTL-RS485}
\label{tbl:switches}
\centerline
......@@ -369,11 +422,11 @@ one position or the other yields a selection valid for all six pulse replication
\textbf{ON} -- glitch filter enabled, output jitter present \newline
\textbf{OFF} -- glitch filter disabled, no output jitter \textbf{(default)} \\
SW1.2 & Input termination enable (see Section~\ref{sec:rp}) \newline
\textbf{ON} -- input terminations for all channels are turned on \newline
\textbf{OFF} -- input terminations for all channels are turned off \\
\textbf{ON} -- enables input terminations for all RS-485 channels \newline
\textbf{OFF} -- disables input terminations for all RS-485 channels \\
SW1.3 & Output termination enable (see Section~\ref{sec:rp}) \newline
\textbf{ON} -- output terminations for all channels are turned on \newline
\textbf{OFF} -- output terminations for all channels are turned off \\
\textbf{ON} -- enables output terminations for all RS-485 channels \newline
\textbf{OFF} -- disables output terminations for all RS-485 channels \\
SW2.4 & TTL/TTL-BAR selection switch (see Section~\ref{sec:pulse-ttl-vs-ttlbar}) \newline
\textbf{ON} -- TTL channels receive and generate TTL \textbf{(default)} \newline
\textbf{OFF} -- TTL channels receive and generate TTL-BAR \\
......@@ -389,7 +442,7 @@ perform no particular function, but their setting is reflected in the status reg
The multicast switches shown in Figure~\ref{fig:switches} can be used to select a
multicast address for the board. At the moment, no particular functionality is defined
in this respect, but setting a switch to ON is reflected in the other switches
in this respect as of release 2.0 of the gateware, but setting a switch to ON is reflected in the other switches
register~(OSWR -- see Appendix~\ref{app:memmap}).
The status of all on-board switches can be read from status registers; for more information
......@@ -407,6 +460,9 @@ see Section~\ref{sec:diag-sw-rtmdet}.
%--------------------------------------------------------------------------------------
\subsection{Pulse signal definition}
\label{sec:pulse-def}
\textit{As optical signaling has specific parameters, the rest of this document will focus
on RS-485 signaling properties, specifically for the CONV-TTL-RTM-RS485-DB9 RTM. For details specific
to the optical RTM, the reader is referred to the hardware guide for this board~\cite{conv-rs485-opt-rtm-hwg}}
There are three pulse types that can be generated by the CONV-TTL-RS485 card:
\begin{itemize}
......@@ -694,9 +750,25 @@ in the board status register (SR -- see Appendix~\ref{app:memmap}) and the
\label{sec:diag}
This section details the remote diagnostics features implemented via the logic
inside the FPGA on-board the CONV-TTL-RS485. Diagnostics data about a CONV-TTL-RS485
inside the FPGA on-board the CONV-TTL-RS485. Diagnostics data from a CONV-TTL-RS485
can be obtained via the I$^2$C interface detailed in Section~\ref{sec:comm}.
The following diagnostics features are implemented on the CONV-TTL-BLO:
\begin{itemize}
\item converter board identification
\item reading of the FPGA gateware version
\item reading of the PCB hardware version
\item reading the state of the on-board switches
\item reading the state of the RTM detection lines
\item reading the unique board ID and on-board temperature
\item input pulse counters
\item input pulse time-tagging
\item remotely reset the FPGA logic
\item manually trigger a pulse
\end{itemize}
%------------------------------------------------------------------------------
% SUBSEC: Board ID
%------------------------------------------------------------------------------
......@@ -721,14 +793,50 @@ The gateware version can be read from the least significant eight bits of the
status register (SR -- see Appendix~\ref{app:memmap}). The gateware version
is split into major and minor version numbers (Figure~\ref{fig:gwvers}).
Both numbers are decimal numbers. The major version number increments on major
changes in the gateware, such as the implementation of new blocks. The minor
version increments on small bug fixes.
changes in the gateware, such as the implementation of new blocks, or changes in
the register map. The minor version increments on small bug fixes.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/gwvers}}
\caption{\label{fig:gwvers} Gateware version field in the status register}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: PCB hardware version
%------------------------------------------------------------------------------
\subsection{Hardware version}
\label{sec:diag-pcbvers}
From v4 boards on-wards, the PCB version is provided to the FPGA via a resistor network implementing 4 bits
for the version number
and 2 bits for potential revisions. The value is available in the SR register (SR -- see Appendix
~\ref{app:memmap} in 6 bits.
So for instance a v4.1 board will be given as "010001", with the Least significant 2 bits
providing the revision number,
and the most significant byte providing the version number.\\
Note also that PCB identification is not available in boards v3 and earlier, and therefore the
HWVERS field in the SR register will read as all zeroes.
%------------------------------------------------------------------------------
% SUBSEC: Thermo, unique ID
%------------------------------------------------------------------------------
\subsection{Unique board ID and temperature readout}
\label{sec:diag-id-therm}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Not implemented in golden gateware versions \\
\hline
\end{tabular}
\vspace*{11pt}
CONV-TTL-RS485 boards contain a thermometer chip~\cite{ds18b20} which can be used to read the
board temperature. This thermometer chip is also factory-programmed with a unique
ID which can be used to uniquely identify a CONV-TTL-RS485.
The FPGA on-board the CONV-TTL-RS485 makes available the temperature and the unique ID values available in
3 registers accessible via I2C (See Appendix~\ref{app:memmap}).
%------------------------------------------------------------------------------
% SUBSEC: Line state
%------------------------------------------------------------------------------
......@@ -754,6 +862,8 @@ also reflected in the LSR.
The state of the on-board switches and that of the RTM detection lines can
also be read from the SR (see Appendix~\ref{app:memmap}).
The RTM pins are given as 6 bits in the Status Register SR, these bits correspond to :
rtmp2-rtmp1-rtmp0-rtmm2-rtmm1-rtmm0 in this order, corresponding to SR.RTM[5:0].
An active-high logic has been selected for both the switches and the RTM
detection lines~\cite{rtm-det}, therefore if a switch is on, or an RTM line is active,
its corresponding bit in the SR is set high.
......@@ -768,6 +878,26 @@ its corresponding bit in the SR is set high.
\caption{\label{fig:sr-switches} Switch mapping to the SR}
\end{figure}
Different RTM line codes are assigned to different RTM boards. Table below shows
RTM line status for the two RTMs CONV-TTL-RS485-RTM-DB9 CONV-TTL-RS485-RTM-OPT
\begin{table}[h] \scriptsize
\caption{RTM line codes}
\label{tbl:rtm-code}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c c c c c c}
\textbf{RTM type} & rtmp2 & rtmp1 & rtmp0 & rtmm2 & rtmm1 & rtmm0 \\
\hline
CONV-TTL-RS485-RTM-DB9 & High & Low & High & Low & Low & High \\
\hline
CONV-TTL-RS485-RTM-OPT & Low & Low & Low & Low & Low & High \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
% SUBSEC: Pulse counters
%------------------------------------------------------------------------------
......@@ -782,12 +912,12 @@ its corresponding bit in the SR is set high.
\vspace*{11pt}
One channel is allocated on the input of each counter, after the OR gate preceding
Each channel is assigned two counters after the OR gate preceding
the pulse generator. The input counter logic, which is repeated on each channel,
is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a
TTL or an RS-485 input, the pulse counter is incremented and stored to the channel's
pulse counter register (CHxPCR -- see Appendix~\ref{app:memmap}). The CHxPCR is a
read-write register that can be written at any time via I$^2$C with a user-defined value.
TTL or an RS485 input, the corresponding pulse counter is incremented and stored to one of the
two channel pulse counter registers (CHxFPPCR or CHxRPPCR -- see Appendix~\ref{app:memmap}).
The CHxFPPCR/CHxRPPCR is a read-write register that can be written at any time via I$^2$C with a user-defined value.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
......@@ -828,7 +958,7 @@ stored into the time-tag buffer, it is also stored to the latest timestamp regis
\subsubsection{Pulse timetags}
%------------------------------------------------------------------------------
Two timetags are available on the CONV-TTL-RS485. These timetags are listed in
Two timetags are available on the CONV-TTL-RS-485. These timetags are listed in
Table~\ref{tbl:timetags}. When White-Rabbit (WR) is present, the precise centralized
and synchronized timing from the WR network is used. When WR is not present, the local
time tag is used. Note that due to the fact that this timetag is unsynchronized,
......
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