##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW       = "SLOW"
##-- DRIVE      = "12"
##----------------------------------------

NET "RST"                     LOC = M16;
 NET "RST"                     IOSTANDARD = "LVCMOS33";
##NET "FPGA_SYSRESET_N"         LOC = L20;
## NET "FPGA_SYSRESET_N"         IOSTANDARD = "LVCMOS33";
##
NET "CLK20_VCXO"              LOC = E16;
 NET "CLK20_VCXO"       IOSTANDARD = "LVCMOS33";
 NET "CLK20_VCXO"       TNM_NET = "CLK20_VCXO";
   TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;

NET "FPGA_CLK_N"              LOC = G11;
  NET "FPGA_CLK_N"      IOSTANDARD = "LVDS_25";
NET "FPGA_CLK_P"              LOC = H12;
  NET "FPGA_CLK_P"      IOSTANDARD = "LVDS_25";
   TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_N" 125 MHz HIGH 50%;
   TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_P" 125 MHz HIGH 50%;


##======================================
##--        FRONT PANEL TTLS
##======================================
##-- LEDs
##--
##-- + UBT:                   LVTTL input
##-------------------
NET "LED_CTRL0"               LOC = M5;
  NET "LED_CTRL0"              IOSTANDARD = "LVTTL";
  NET "LED_CTRL0"              DRIVE = "4";
  NET "LED_CTRL0"              SLEW  = "QUIETIO";
NET "LED_CTRL0_OEN"           LOC = M4;
  NET "LED_CTRL0_OEN"          IOSTANDARD = "LVTTL";
  NET "LED_CTRL0_OEN"          DRIVE = "4";
  NET "LED_CTRL0_OEN"          SLEW  = "QUIETIO";
NET "LED_CTRL1"               LOC = K6;
  NET "LED_CTRL1"              IOSTANDARD = "LVTTL";
  NET "LED_CTRL1"              DRIVE = "4";
  NET "LED_CTRL1"              SLEW  = "QUIETIO";
NET "LED_CTRL1_OEN"           LOC = K5;
  NET "LED_CTRL1_OEN"          IOSTANDARD = "LVTTL";
  NET "LED_CTRL1_OEN"          DRIVE = "4";
  NET "LED_CTRL1_OEN"          SLEW  = "QUIETIO";
NET "LED_MULTICAST_2_0"       LOC = F9;
  NET "LED_MULTICAST_2_0"      IOSTANDARD = "LVTTL";
  NET "LED_MULTICAST_2_0"      DRIVE = "4";
  NET "LED_MULTICAST_2_0"      SLEW  = "QUIETIO";
NET "LED_MULTICAST_3_1"       LOC = F10;
  NET "LED_MULTICAST_3_1"      IOSTANDARD = "LVTTL";
  NET "LED_MULTICAST_3_1"      DRIVE = "4";
  NET "LED_MULTICAST_3_1"      SLEW  = "QUIETIO";
NET "LED_WR_GMT_TTL_TTLN"     LOC = E5;
  NET "LED_WR_GMT_TTL_TTLN"    IOSTANDARD = "LVTTL";
  NET "LED_WR_GMT_TTL_TTLN"    DRIVE = "4";
  NET "LED_WR_GMT_TTL_TTLN"    SLEW  = "QUIETIO";
NET "LED_WR_LINK_SYSERROR"    LOC = F7;
  NET "LED_WR_LINK_SYSERROR"   IOSTANDARD = "LVTTL";
  NET "LED_WR_LINK_SYSERROR"   DRIVE = "4";
  NET "LED_WR_LINK_SYSERROR"   SLEW  = "QUIETIO";
NET "LED_WR_OK_SYSPW"         LOC = F8;
  NET "LED_WR_OK_SYSPW"        IOSTANDARD = "LVTTL";
  NET "LED_WR_OK_SYSPW"        DRIVE = "4";
  NET "LED_WR_OK_SYSPW"        SLEW  = "QUIETIO";
NET "LED_WR_OWNADDR_I2C"      LOC = E6;
  NET "LED_WR_OWNADDR_I2C"     IOSTANDARD = "LVTTL";
  NET "LED_WR_OWNADDR_I2C"     DRIVE = "4";
  NET "LED_WR_OWNADDR_I2C"     SLEW  = "QUIETIO";
##-------------------
##-- Front channel LEDs
##--
##-- + ACT family:          CMOS/TTL 3.3V inputs
##--
##-- Renamed: PULSE_FRONT_LEDx_N --> PULSE_FRONT_LED_Nx
##--
##-------------------
NET "PULSE_FRONT_LED_N1"      LOC = H3;
  NET "PULSE_FRONT_LED_N1"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED_N1"     DRIVE = "4";
  NET "PULSE_FRONT_LED_N1"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED_N2"      LOC = J4;
  NET "PULSE_FRONT_LED_N2"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED_N2"     DRIVE = "4";
  NET "PULSE_FRONT_LED_N2"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED_N3"      LOC = J3;
  NET "PULSE_FRONT_LED_N3"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED_N3"     DRIVE = "4";
  NET "PULSE_FRONT_LED_N3"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED_N4"      LOC = K3;
  NET "PULSE_FRONT_LED_N4"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED_N4"     DRIVE = "4";
  NET "PULSE_FRONT_LED_N4"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED_N5"      LOC = L4;
  NET "PULSE_FRONT_LED_N5"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED_N5"     DRIVE = "4";
  NET "PULSE_FRONT_LED_N5"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED_N6"      LOC = L3;
  NET "PULSE_FRONT_LED_N6"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED_N6"     DRIVE = "4";
  NET "PULSE_FRONT_LED_N6"     SLEW  = "QUIETIO";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family:          CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED1"         LOC = AB17;
  NET "PULSE_REAR_LED1"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED1"     DRIVE = "4";
  NET "PULSE_REAR_LED1"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED2"         LOC = AB19;
  NET "PULSE_REAR_LED2"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED2"     DRIVE = "4";
  NET "PULSE_REAR_LED2"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED3"         LOC = AA16;
  NET "PULSE_REAR_LED3"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED3"     DRIVE = "4";
  NET "PULSE_REAR_LED3"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED4"         LOC = AA18;
  NET "PULSE_REAR_LED4"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED4"     DRIVE = "4";
  NET "PULSE_REAR_LED4"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED5"         LOC = AB16;
  NET "PULSE_REAR_LED5"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED5"     DRIVE = "4";
  NET "PULSE_REAR_LED5"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED6"         LOC = AB18;
  NET "PULSE_REAR_LED6"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED6"     DRIVE = "4";
  NET "PULSE_REAR_LED6"     SLEW  = "QUIETIO";


##-------------------
##-- TTL trigger inputs
##--
##-- + ACT family:          CMOS/TTL 3.3V inputs
##--
##-- Renamed: FPGA_INPUT_TTLx_N --> FPGA_INPUT_TTL_Nx
##--
##-------------------
NET "FPGA_INPUT_TTL_N1"       LOC = T3;
  NET "FPGA_INPUT_TTL_N1"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N2"       LOC = U4;
  NET "FPGA_INPUT_TTL_N2"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N3"       LOC = W3;
  NET "FPGA_INPUT_TTL_N3"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N4"       LOC = W4;
  NET "FPGA_INPUT_TTL_N4"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N5"       LOC = V3;
  NET "FPGA_INPUT_TTL_N5"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N6"       LOC = U3;
  NET "FPGA_INPUT_TTL_N6"     IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL1"           LOC = D1;
  NET "FPGA_OUT_TTL1"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL2"           LOC = E1;
  NET "FPGA_OUT_TTL2"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL3"           LOC = F2;
  NET "FPGA_OUT_TTL3"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL4"           LOC = F1;
  NET "FPGA_OUT_TTL4"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL5"           LOC = G1;
  NET "FPGA_OUT_TTL5"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL6"           LOC = H2;
  NET "FPGA_OUT_TTL6"         IOSTANDARD = "LVCMOS33";
##-------------------
##-- Bottomly allocated GPIOs
##--
##-- + IN     ACT family:          CMOS/TTL 3.3V inputs
##-- + OUT    BCT family (BiCMOS): TTL inputs
##--
##-- Renamed: INV_IN_x_N --> INV_IN_Nx
##-- Renamed: INV_OUT_x  --> INV_OUTx
##--
##-------------------
NET "INV_IN_N1"              LOC = Y1;
 NET "INV_IN_N1"         IOSTANDARD = "LVCMOS33";
NET "INV_IN_N2"              LOC = Y2;
 NET "INV_IN_N2"         IOSTANDARD = "LVCMOS33";
NET "INV_IN_N3"              LOC = AA2;
 NET "INV_IN_N3"         IOSTANDARD = "LVCMOS33";
NET "INV_IN_N4"              LOC = AA2;
 NET "INV_IN_N4"         IOSTANDARD = "LVCMOS33";
NET "INV_OUT1"               LOC = H1;
 NET "INV_OUT1"          IOSTANDARD = "LVCMOS33";
NET "INV_OUT2"               LOC = J1;
 NET "INV_OUT2"          IOSTANDARD = "LVCMOS33";
NET "INV_OUT3"               LOC = K2;
 NET "INV_OUT3"          IOSTANDARD = "LVCMOS33";
NET "INV_OUT4"               LOC = K1;
 NET "INV_OUT4"          IOSTANDARD = "LVCMOS33";


##======================================
##--          RTM signals
##======================================
##-- Blocking input to FPGA
##--
##-- Renamed: FPGA_RS485_INA_TTL_1 --> FPGA_RS485_INA_TTL1
##--          FPGA_TRIG_RS485_x    --> FPGA_TRIG_RTMx
##--
##-------------------
NET "FPGA_RS485_INA_TTL1"    LOC = Y12;
 NET "FPGA_RS485_INA_TTL1"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL2"    LOC = AB12;
 NET "FPGA_RS485_INA_TTL2"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL3"    LOC = AB11;
 NET "FPGA_RS485_INA_TTL3"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL4"    LOC = AB10;
 NET "FPGA_RS485_INA_TTL4"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL5"    LOC = AB9;
 NET "FPGA_RS485_INA_TTL5"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INA_TTL6"    LOC = AA8;
 NET "FPGA_RS485_INA_TTL6"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL1"    LOC = AA12;
 NET "FPGA_RS485_INB_TTL1"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL2"    LOC = Y11;
 NET "FPGA_RS485_INB_TTL2"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL3"    LOC = Y10;
 NET "FPGA_RS485_INB_TTL3"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL4"    LOC = AA10;
 NET "FPGA_RS485_INB_TTL4"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL5"    LOC = AB8;
 NET "FPGA_RS485_INB_TTL5"    IOSTANDARD = "LVCMOS33";
NET "FPGA_RS485_INB_TTL6"    LOC = AB7;
 NET "FPGA_RS485_INB_TTL6"    IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RTM1"       LOC = W18;
 NET "FPGA_TRIG_RTM1"       IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RTM2"       LOC = Y18;
 NET "FPGA_TRIG_RTM2"       IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RTM3"       LOC = W17;
 NET "FPGA_TRIG_RTM3"       IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RTM4"       LOC = Y17;
 NET "FPGA_TRIG_RTM4"       IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RTM5"       LOC = Y16;
 NET "FPGA_TRIG_RTM5"       IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_RTM6"       LOC = Y15;
 NET "FPGA_TRIG_RTM6"       IOSTANDARD = "LVCMOS33";

##======================================
##--       VME CONNECTOR SIGNALS
##======================================
##-- I2C lines
##--
##-- + UBT:                   LVTTL input
##-------------------
NET "SCL_I"                   LOC = F19;
  NET "SCL_I"                  IOSTANDARD = "LVTTL";
NET "SCL_O"                   LOC = E20;
  NET "SCL_O"                  IOSTANDARD = "LVTTL";
  NET "SCL_O"                  DRIVE = "4";
NET "SCL_OE"                  LOC = H18;
  NET "SCL_OE"                 IOSTANDARD = "LVTTL";
  NET "SCL_OE"                 DRIVE = "4";
  NET "SCL_OE"                 PULLDOWN;
NET "SDA_I"                   LOC = G20;
  NET "SDA_I"                  IOSTANDARD = "LVTTL";
NET "SDA_O"                   LOC = F20;
  NET "SDA_O"                  IOSTANDARD = "LVTTL";
  NET "SDA_O"                  SLEW = "FAST";
  NET "SDA_O"                  DRIVE = "4";
  NET "SDA_O"                  PULLUP;
NET "SDA_OE"                  LOC = J19;
  NET "SDA_OE"                 IOSTANDARD = "LVTTL";
  NET "SDA_OE"                 SLEW = "FAST";
  NET "SDA_OE"                 DRIVE = "4";
  NET "SDA_OE"                 PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT:                   LVTTL input
##-------------------
NET "FPGA_GA0"                LOC = H20;
  NET "FPGA_GA0"               IOSTANDARD = "LVTTL";
NET "FPGA_GA1"                LOC = J20;
  NET "FPGA_GA1"               IOSTANDARD = "LVTTL";
NET "FPGA_GA2"                LOC = K19;
  NET "FPGA_GA2"               IOSTANDARD = "LVTTL";
NET "FPGA_GA3"                LOC = K20;
  NET "FPGA_GA3"               IOSTANDARD = "LVTTL";
NET "FPGA_GA4"                LOC = L19;
  NET "FPGA_GA4"               IOSTANDARD = "LVTTL";
NET "FPGA_GAP"                LOC = H19;
  NET "FPGA_GAP"               IOSTANDARD = "LVTTL";
##-------------------
##-- ROM memory
##-------------------
NET "FPGA_PROM_CCLK"          LOC = Y20;
  NET "FPGA_PROM_CCLK"         IOSTANDARD = "LVTTL";
NET "FPGA_PROM_CSO_B_N"       LOC = AA3;
  NET "FPGA_PROM_CSO_B_N"      IOSTANDARD = "LVTTL";
NET "FPGA_PROM_DIN"           LOC = AA20;
  NET "FPGA_PROM_DIN"          IOSTANDARD = "LVTTL";
NET "FPGA_PROM_MOSI"          LOC = AB20;
  NET "FPGA_PROM_MOSI"         IOSTANDARD = "LVTTL";


####======================================
####--          WHITE RABBIT
####======================================
####-------------------
####-- Thermo for UID
####-------------------
##NET "THERMOMETER"             LOC = B1;
## NET "THERMOMETER"            IOSTANDARD = "LVCMOS25";
####-------------------
####-- DACs control
####--
####-- + CMOS 3.3V input
####-------------------
##NET "FPGA_PLLDAC1_DIN"        LOC = Y14;
##  NET "FPGA_PLLDAC1_DIN"      IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SCLK"       LOC = AA14;
##  NET "FPGA_PLLDAC1_SCLK"     IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC1_SYNC_N"     LOC = AB15;
##  NET "FPGA_PLLDAC1_SYNC_N"   IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_DIN"        LOC = AB13;
##  NET "FPGA_PLLDAC2_DIN"      IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SCLK"       LOC = Y13;
##  NET "FPGA_PLLDAC2_SCLK"     IOSTANDARD = "LVCMOS25";
##NET "FPGA_PLLDAC2_SYNC_N"     LOC = AB14;
##  NET "FPGA_PLLDAC2_SYNC_N"   IOSTANDARD = "LVCMOS25";
####-------------------
####-- SFP connection
####-------------------
##NET "FPGA_SFP_LOS"            LOC = G3;
## NET "FPGA_SFP_LOS"            IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_PRESENCE"       LOC = E3;
## NET "FPGA_SFP_PRESENCE"       IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_RATE_SELECT"    LOC = C4;
## NET "FPGA_SFP_RATE_SELECT"    IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_SCL"            LOC = F3;
## NET "FPGA_SFP_SCL"            IOSTANDARD = "LVCMOS33";
##NET "FPGA_SFP_SDA"            LOC = G4;
## NET "FPGA_SFP_SDA"            IOSTANDARD = "LVCMOS33";
##NET "SFP_TX_DISABLE"          LOC = E4;
## NET "SFP_TX_DISABLE"          IOSTANDARD = "LVCMOS33";
##NET "SFP_TX_FAULT"            LOC = D2;
## NET "SFP_TX_FAULT"            IOSTANDARD = "LVCMOS33";
####-------------------
####-- FPGA MGT lines
####-------------------
##NET "FPGAMGTCLK0_P"      LOC = A10;
## NET "FPGAMGTCLK0_P"      IOSTANDARD = "LVDS_12";
##NET "FPGAMGTCLK0_N"      LOC = B10;
## NET "FPGAMGTCLK0_N"      IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_P"        LOC = D7;
## NET "MGTSFPRX0_P"        IOSTANDARD = "LVDS_12";
##NET "MGTSFPRX0_N"        LOC = C7;
## NET "MGTSFPRX0_N"        IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_P"        LOC = B6;
## NET "MGTSFPTX0_P"        IOSTANDARD = "LVDS_12";
##NET "MGTSFPTX0_N"        LOC = A6;
## NET "MGTSFPTX0_N"        IOSTANDARD = "LVDS_12";


##======================================
##--         ADDITIONAL PINS
##======================================
##--
##-- + HC                     CMOS 3.3V input
##-------------------
NET "FPGA_OE"                 LOC = N3;
 NET "FPGA_OE"                 IOSTANDARD = "LVCMOS33";
 NET "FPGA_OE"                 DRIVE = "4";
 NET "FPGA_OE"                 SLEW  = "QUIETIO";
NET "FPGA_RS485_OE"           LOC = AB6;
 NET "FPGA_RS485_OE"           IOSTANDARD = "LVCMOS33";
 NET "FPGA_RS485_OE"           DRIVE = "4";
 NET "FPGA_RS485_OE"           SLEW  = "QUIETIO";
NET "FPGA_TRIG_TTL_OE"        LOC = M3;
 NET "FPGA_TRIG_TTL_OE"        IOSTANDARD = "LVCMOS33";
 NET "FPGA_TRIG_TTL_OE"        DRIVE = "4";
 NET "FPGA_TRIG_TTL_OE"        SLEW  = "QUIETIO";
NET "FPGA_INV_OE"             LOC = N4;
 NET "FPGA_INV_OE"             IOSTANDARD = "LVCMOS33";
 NET "FPGA_INV_OE"             DRIVE = "4";
 NET "FPGA_INV_OE"             SLEW  = "QUIETIO";
##-------------------
##-- Configuration Switches
##
##-- Renamed: TTL/INV_TTL_N --> TTL_or_INV_TTL_N 
##-------------------
NET "EXTRA_SWITCH_1"          LOC = F22;
 NET "EXTRA_SWITCH_1"          IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_2"          LOC = G22;
 NET "EXTRA_SWITCH_2"          IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_3"          LOC = H21;
 NET "EXTRA_SWITCH_3"          IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_4"          LOC = H22;
 NET "EXTRA_SWITCH_4"          IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_5"          LOC = J22;
 NET "EXTRA_SWITCH_5"          IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_6"          LOC = K21;
 NET "EXTRA_SWITCH_6"          IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_7"          LOC = K22;
 NET "EXTRA_SWITCH_7"          IOSTANDARD = "LVCMOS33";
NET "TTL_or_INV_TTL_N"        LOC = L22;
 NET "TTL_or_INV_TTL_N"        IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_1"        LOC = B21;
 NET "MULTICAST_ADDR_1"        IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_2"        LOC = B22;
 NET "MULTICAST_ADDR_2"        IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_3"        LOC = C22;
 NET "MULTICAST_ADDR_3"        IOSTANDARD = "LVCMOS33";
NET "MULTICAST_ADDR_4"        LOC = D21;
 NET "MULTICAST_ADDR_4"        IOSTANDARD = "LVCMOS33";
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT:                   CMOS 3.3V input
##-------------------
NET "FPGA_RTMM0"              LOC = V21;
 NET "FPGA_RTMM0"              IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM1"              LOC = V22;
 NET "FPGA_RTMM1"              IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM2"              LOC = U22;
 NET "FPGA_RTMM2"              IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP0"              LOC = W22;
 NET "FPGA_RTMP0"              IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP1"              LOC = Y22;
 NET "FPGA_RTMP1"              IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP2"              LOC = Y21;
 NET "FPGA_RTMP2"              IOSTANDARD = "LVCMOS33";
####-------------------
####-- General purpose
####--
####-- + ACT:                   CMOS 3.3V input
####-------------------
##NET "FPGA_HEADER_OUT1"        LOC = F15;
## NET "FPGA_HEADER_OUT1"        IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_OUT2"        LOC = F16;
## NET "FPGA_HEADER_OUT2"        IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_OUT3"        LOC = F17;
## NET "FPGA_HEADER_OUT3"        IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_OUT4"        LOC = F14;
## NET "FPGA_HEADER_OUT4"        IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_OUT5"        LOC = H14;
## NET "FPGA_HEADER_OUT5"        IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_OUT6"        LOC = H13;
## NET "FPGA_HEADER_OUT6"        IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_IN1"         LOC = A17;
## NET "FPGA_HEADER_IN1"         IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_IN2"         LOC = A18;
## NET "FPGA_HEADER_IN2"         IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_IN3"         LOC = B18;
## NET "FPGA_HEADER_IN3"         IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_IN4"         LOC = A19;
## NET "FPGA_HEADER_IN4"         IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_IN5"         LOC = A20;
## NET "FPGA_HEADER_IN5"         IOSTANDARD = "LVCMOS33";
##NET "FPGA_HEADER_IN6"         LOC = B20;
## NET "FPGA_HEADER_IN6"         IOSTANDARD = "LVCMOS33";
