##---------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW       = "SLOW"
##-- DRIVE      = "12"
##----------------------------------------


NET "RST_N"            LOC = N20;
 NET "RST_N"            IOSTANDARD = "LVCMOS33";
NET "FPGA_SYSRESET_N"  LOC = L20;
 NET "FPGA_SYSRESET_N"  IOSTANDARD = "LVCMOS33";
NET "MR_N"             LOC = T22;
 NET "MR_N"             IOSTANDARD = "LVCMOS33";

NET "CLK20_VCXO"       LOC = E16;
 NET "CLK20_VCXO"       IOSTANDARD = "LVCMOS33";
 NET "CLK20_VCXO"       TNM_NET = "CLK20_VCXO";
   TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;

NET "FPGA_CLK_N"       LOC = H12;
  NET "FPGA_CLK_N"      IOSTANDARD = "LVDS_25";
NET "FPGA_CLK_P"       LOC = G11;
  NET "FPGA_CLK_P"      IOSTANDARD = "LVDS_25";
   TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_N" 125 MHz HIGH 50%;
   TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_P" 125 MHz HIGH 50%;


##======================================
##--        FRONT PANEL TTLS
##======================================
##-- LEDs
##--
##-- + UBT:                   LVTTL input
##-------------------
NET "LED_CTRL0"               LOC = M18;
  NET "LED_CTRL0"              IOSTANDARD = "LVTTL";
  NET "LED_CTRL0"              DRIVE = "4";
  NET "LED_CTRL0"              SLEW  = "QUIETIO";
NET "LED_CTRL0_OEN"           LOC = T20;
  NET "LED_CTRL0_OEN"          IOSTANDARD = "LVTTL";
  NET "LED_CTRL0_OEN"          DRIVE = "4";
  NET "LED_CTRL0_OEN"          SLEW  = "QUIETIO";
NET "LED_CTRL1"               LOC = M17;
  NET "LED_CTRL1"              IOSTANDARD = "LVTTL";
  NET "LED_CTRL1"              DRIVE = "4";
  NET "LED_CTRL1"              SLEW  = "QUIETIO";
NET "LED_CTRL1_OEN"           LOC = U19;
  NET "LED_CTRL1_OEN"          IOSTANDARD = "LVTTL";
  NET "LED_CTRL1_OEN"          DRIVE = "4";
  NET "LED_CTRL1_OEN"          SLEW  = "QUIETIO";
NET "LED_MULTICAST_2_0"       LOC = P16;
  NET "LED_MULTICAST_2_0"      IOSTANDARD = "LVTTL";
  NET "LED_MULTICAST_2_0"      DRIVE = "4";
  NET "LED_MULTICAST_2_0"      SLEW  = "QUIETIO";
NET "LED_MULTICAST_3_1"       LOC = P17;
  NET "LED_MULTICAST_3_1"      IOSTANDARD = "LVTTL";
  NET "LED_MULTICAST_3_1"      DRIVE = "4";
  NET "LED_MULTICAST_3_1"      SLEW  = "QUIETIO";
NET "LED_WR_GMT_TTL_TTLN"     LOC = N16;
  NET "LED_WR_GMT_TTL_TTLN"    IOSTANDARD = "LVTTL";
  NET "LED_WR_GMT_TTL_TTLN"    DRIVE = "4";
  NET "LED_WR_GMT_TTL_TTLN"    SLEW  = "QUIETIO";
NET "LED_WR_LINK_SYSERROR"    LOC = R15;
  NET "LED_WR_LINK_SYSERROR"   IOSTANDARD = "LVTTL";
  NET "LED_WR_LINK_SYSERROR"   DRIVE = "4";
  NET "LED_WR_LINK_SYSERROR"   SLEW  = "QUIETIO";
NET "LED_WR_OK_SYSPW"         LOC = R16;
  NET "LED_WR_OK_SYSPW"        IOSTANDARD = "LVTTL";
  NET "LED_WR_OK_SYSPW"        DRIVE = "4";
  NET "LED_WR_OK_SYSPW"        SLEW  = "QUIETIO";
NET "LED_WR_OWNADDR_I2C"      LOC = N15;
  NET "LED_WR_OWNADDR_I2C"     IOSTANDARD = "LVTTL";
  NET "LED_WR_OWNADDR_I2C"     DRIVE = "4";
  NET "LED_WR_OWNADDR_I2C"     SLEW  = "QUIETIO";
##-------------------
##-- Front channel LEDs
##--
##-- + ACT family:          CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_FRONT_LED1_N"      LOC = H5;
  NET "PULSE_FRONT_LED1_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED1_N"     DRIVE = "4";
  NET "PULSE_FRONT_LED1_N"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED2_N"      LOC = J6;
  NET "PULSE_FRONT_LED2_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED2_N"     DRIVE = "4";
  NET "PULSE_FRONT_LED2_N"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED3_N"      LOC = K6;
  NET "PULSE_FRONT_LED3_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED3_N"     DRIVE = "4";
  NET "PULSE_FRONT_LED3_N"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED4_N"      LOC = K5;
  NET "PULSE_FRONT_LED4_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED4_N"     DRIVE = "4";
  NET "PULSE_FRONT_LED4_N"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED5_N"      LOC = M7;
  NET "PULSE_FRONT_LED5_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED5_N"     DRIVE = "4";
  NET "PULSE_FRONT_LED5_N"     SLEW  = "QUIETIO";
NET "PULSE_FRONT_LED6_N"      LOC = M6;
  NET "PULSE_FRONT_LED6_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_FRONT_LED6_N"     DRIVE = "4";
  NET "PULSE_FRONT_LED6_N"     SLEW  = "QUIETIO";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family:          CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED1_N"      LOC = AB17;
  NET "PULSE_REAR_LED1_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED1_N"     DRIVE = "4";
  NET "PULSE_REAR_LED1_N"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED2_N"      LOC = AB19;
  NET "PULSE_REAR_LED2_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED2_N"     DRIVE = "4";
  NET "PULSE_REAR_LED2_N"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED3_N"      LOC = AA16;
  NET "PULSE_REAR_LED3_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED3_N"     DRIVE = "4";
  NET "PULSE_REAR_LED3_N"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED4_N"      LOC = AA18;
  NET "PULSE_REAR_LED4_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED4_N"     DRIVE = "4";
  NET "PULSE_REAR_LED4_N"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED5_N"      LOC = AB16;
  NET "PULSE_REAR_LED5_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED5_N"     DRIVE = "4";
  NET "PULSE_REAR_LED5_N"     SLEW  = "QUIETIO";
NET "PULSE_REAR_LED6_N"      LOC = AB18;
  NET "PULSE_REAR_LED6_N"     IOSTANDARD = "LVCMOS33";
  NET "PULSE_REAR_LED6_N"     DRIVE = "4";
  NET "PULSE_REAR_LED6_N"     SLEW  = "QUIETIO";


##-------------------
##-- TTL trigger inputs
##--
##-- + ACT family:          CMOS/TTL 3.3V inputs
##-------------------
NET "FPGA_INPUT_TTL1_N"      LOC = T2;
  NET "FPGA_INPUT_TTL1_N"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL2_N"      LOC = U3;
  NET "FPGA_INPUT_TTL2_N"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL3_N"      LOC = V5;
  NET "FPGA_INPUT_TTL3_N"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL4_N"      LOC = W4;
  NET "FPGA_INPUT_TTL4_N"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL5_N"      LOC = T6;
  NET "FPGA_INPUT_TTL5_N"     IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL6_N"      LOC = T3;
  NET "FPGA_INPUT_TTL6_N"     IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL1"          LOC = C1;
  NET "FPGA_OUT_TTL1"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL2"          LOC = F2;
  NET "FPGA_OUT_TTL2"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL3"          LOC = F5;
  NET "FPGA_OUT_TTL3"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL4"          LOC = H4;
  NET "FPGA_OUT_TTL4"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL5"          LOC = J4;
  NET "FPGA_OUT_TTL5"         IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL6"          LOC = H2;
  NET "FPGA_OUT_TTL6"         IOSTANDARD = "LVCMOS33";
##-------------------
##-- Bottomly allocated GPIOs
##--
##-- + IN     ACT family:          CMOS/TTL 3.3V inputs
##-- + OUT    BCT family (BiCMOS): TTL inputs
##
##-- Schematics name:              INV_IN_*
##---- renamed to                  INV_IN[*]
##-------------------
NET "INV_IN_1_N"         LOC = V2;
 NET "INV_IN_1_N"         IOSTANDARD = "LVCMOS33";
NET "INV_IN_2_N"         LOC = W3;
 NET "INV_IN_2_N"         IOSTANDARD = "LVCMOS33";
NET "INV_IN_3_N"         LOC = Y2;
 NET "INV_IN_3_N"         IOSTANDARD = "LVCMOS33";
NET "INV_IN_4_N"         LOC = AA2;
 NET "INV_IN_4_N"         IOSTANDARD = "LVCMOS33";
NET "INV_OUT_1"          LOC = J3;
 NET "INV_OUT_1"          IOSTANDARD = "LVCMOS33";
NET "INV_OUT_2"          LOC = L3;
 NET "INV_OUT_2"          IOSTANDARD = "LVCMOS33";
NET "INV_OUT_3"          LOC = M3;
 NET "INV_OUT_3"          IOSTANDARD = "LVCMOS33";
NET "INV_OUT_4"          LOC = P2;
 NET "INV_OUT_4"          IOSTANDARD = "LVCMOS33";


##======================================
##--          RTM signals
##======================================
##-- Blocking input to FPGA
##
##-- Schematics name:       FPGA_BLO_IN_*
##---- renamed to           FPGA_BLO_IN[*]
##-------------------
NET "FPGA_BLO_IN_1"      LOC = Y9;
  NET "FPGA_BLO_IN_1"      IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_2"      LOC = AA10;
  NET "FPGA_BLO_IN_2"      IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_3"      LOC = W12;
  NET "FPGA_BLO_IN_3"      IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_4"      LOC = AA6;
  NET "FPGA_BLO_IN_4"      IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_5"      LOC = Y7;
  NET "FPGA_BLO_IN_5"      IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_6"      LOC = AA8;
  NET "FPGA_BLO_IN_6"      IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO1"     LOC = W9;
  NET "FPGA_TRIG_BLO1"     IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO2"     LOC = T10;
  NET "FPGA_TRIG_BLO2"     IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO3"     LOC = V7;
  NET "FPGA_TRIG_BLO3"     IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO4"     LOC = U9;
  NET "FPGA_TRIG_BLO4"     IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO5"     LOC = T8;
  NET "FPGA_TRIG_BLO5"     IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO6"     LOC = R9;
  NET "FPGA_TRIG_BLO6"     IOSTANDARD = "LVCMOS33";

##======================================
##--       VME CONNECTOR SIGNALS
##======================================
##-- I2C lines
##--
##-- + UBT:                   LVTTL input
##-------------------
NET "SCL_I"                  LOC = F19;
  NET "SCL_I"                  IOSTANDARD = "LVTTL";
NET "SCL_O"                  LOC = E20;
  NET "SCL_O"                  IOSTANDARD = "LVTTL";
  NET "SCL_O"                  DRIVE = "4";
NET "SCL_OE"                 LOC = H18;
  NET "SCL_OE"                 IOSTANDARD = "LVTTL";
  NET "SCL_OE"                 DRIVE = "4";
  NET "SCL_OE"                 PULLDOWN;
NET "SDA_I"                  LOC = G20;
  NET "SDA_I"                  IOSTANDARD = "LVTTL";
NET "SDA_O"                  LOC = F20;
  NET "SDA_O"                  IOSTANDARD = "LVTTL";
  NET "SDA_O"                  SLEW = "FAST";
  NET "SDA_O"                  DRIVE = "4";
  NET "SDA_O"                  PULLUP;
NET "SDA_OE"                 LOC = J19;
  NET "SDA_OE"                 IOSTANDARD = "LVTTL";
  NET "SDA_OE"                 SLEW = "FAST";
  NET "SDA_OE"                 DRIVE = "4";
  NET "SDA_OE"                 PULLDOWN;
##-------------------
##-- Geographical Address
##--
##-- + UBT:                   LVTTL input
##-------------------
NET "FPGA_GA0"               LOC = H20;
  NET "FPGA_GA0"              IOSTANDARD = "LVTTL";
NET "FPGA_GA1"               LOC = J20;
  NET "FPGA_GA1"              IOSTANDARD = "LVTTL";
NET "FPGA_GA2"               LOC = K19;
  NET "FPGA_GA2"              IOSTANDARD = "LVTTL";
NET "FPGA_GA3"               LOC = K20;
  NET "FPGA_GA3"              IOSTANDARD = "LVTTL";
NET "FPGA_GA4"               LOC = L19;
  NET "FPGA_GA4"              IOSTANDARD = "LVTTL";
NET "FPGA_GAP"               LOC = H19;
  NET "FPGA_GAP"              IOSTANDARD = "LVTTL";
##-------------------
##-- ROM memory
##-------------------
NET "FPGA_PROM_CCLK"         LOC = Y20;
  NET "FPGA_PROM_CCLK"         IOSTANDARD = "LVTTL";
NET "FPGA_PROM_CSO_B_N"      LOC = AA3;
  NET "FPGA_PROM_CSO_B_N"      IOSTANDARD = "LVTTL";
NET "FPGA_PROM_DIN"          LOC = AA20;
  NET "FPGA_PROM_DIN"          IOSTANDARD = "LVTTL";
NET "FPGA_PROM_MOSI"         LOC = AB20;
  NET "FPGA_PROM_MOSI"         IOSTANDARD = "LVTTL";


##======================================
##--          WHITE RABBIT
##======================================
##-------------------
##-- Thermo for UID
##-------------------
NET "THERMOMETER"            LOC = B1;
 NET "THERMOMETER"            IOSTANDARD = "LVCMOS25";
##-------------------
##-- DACs control
##--
##-- + CMOS 3.3V input
##-------------------
NET "FPGA_PLLDAC1_DIN"       LOC = AB14;
  NET "FPGA_PLLDAC1_DIN"      IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SCLK"      LOC = AA14;
  NET "FPGA_PLLDAC1_SCLK"     IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SYNC_N"    LOC = AB15;
  NET "FPGA_PLLDAC1_SYNC_N"   IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_DIN"       LOC = W14;
  NET "FPGA_PLLDAC2_DIN"      IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SCLK"      LOC = Y14;
  NET "FPGA_PLLDAC2_SCLK"     IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SYNC_N"    LOC = W13;
  NET "FPGA_PLLDAC2_SYNC_N"   IOSTANDARD = "LVCMOS25";
##-------------------
##-- SFP connection
##-------------------
NET "FPGA_SFP_LOS"           LOC = G3;
  NET "FPGA_SFP_LOS"           IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF0"      LOC = K8;
  NET "FPGA_SFP_MOD_DEF0"      IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_RATE_SELECT"   LOC = C4;
  NET "FPGA_SFP_RATE_SELECT"   IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF1"      LOC = G4;
  NET "FPGA_SFP_MOD_DEF1"      IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF2"      LOC = F3;
  NET "FPGA_SFP_MOD_DEF2"      IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_TX_DISABLE"    LOC = E4;
  NET "FPGA_SFP_TX_DISABLE"    IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_TX_FAULT"      LOC = D2;
  NET "FPGA_SFP_TX_FAULT"      IOSTANDARD = "LVCMOS33";
##-------------------
##-- FPGA MGT lines
##-------------------
NET "FPGAMGTCLK0_P"      LOC = A10;
 NET "FPGAMGTCLK0_P"      IOSTANDARD = "LVDS_12";
NET "FPGAMGTCLK0_N"      LOC = B10;
 NET "FPGAMGTCLK0_N"      IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_P"        LOC = D7;
 NET "MGTSFPRX0_P"        IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_N"        LOC = C7;
 NET "MGTSFPRX0_N"        IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_P"        LOC = B6;
 NET "MGTSFPTX0_P"        IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_N"        LOC = A6;
 NET "MGTSFPTX0_N"        IOSTANDARD = "LVDS_12";


##======================================
##--         ADDITIONAL PINS
##======================================
##--
##-- + HC                     CMOS 3.3V input
##-------------------
NET "FPGA_OE"            LOC = R3;
 NET "FPGA_OE"            IOSTANDARD = "LVCMOS33";
 NET "FPGA_OE"            DRIVE = "4";
 NET "FPGA_OE"            SLEW  = "QUIETIO";
NET "FPGA_BLO_OE"        LOC = P5;
 NET "FPGA_BLO_OE"        IOSTANDARD = "LVCMOS33";
 NET "FPGA_BLO_OE"        DRIVE = "4";
 NET "FPGA_BLO_OE"        SLEW  = "QUIETIO";
NET "FPGA_TRIG_TTL_OE"   LOC = N3;
 NET "FPGA_TRIG_TTL_OE"   IOSTANDARD = "LVCMOS33";
 NET "FPGA_TRIG_TTL_OE"   DRIVE = "4";
 NET "FPGA_TRIG_TTL_OE"   SLEW  = "QUIETIO";
NET "FPGA_INV_OE"        LOC = P6;
 NET "FPGA_INV_OE"        IOSTANDARD = "LVCMOS33";
 NET "FPGA_INV_OE"        DRIVE = "4";
 NET "FPGA_INV_OE"        SLEW  = "QUIETIO";
##-------------------
##-- Configuration Switches
##
##-- Schematics name          EXTRA_SWITCH_*
##---- renamed to             EXTRA_SWITCH[*]
##-------------------
NET "EXTRA_SWITCH_1"     LOC = F22;
 NET "EXTRA_SWITCH_1"     IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_2"     LOC = G22;
 NET "EXTRA_SWITCH_2"     IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_3"     LOC = H21;
 NET "EXTRA_SWITCH_3"     IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_4"     LOC = H22;
 NET "EXTRA_SWITCH_4"     IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_5"     LOC = J22;
 NET "EXTRA_SWITCH_5"     IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_6"     LOC = K21;
 NET "EXTRA_SWITCH_6"     IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_7"     LOC = K22;
 NET "EXTRA_SWITCH_7"     IOSTANDARD = "LVCMOS33";
NET "TTL/INV_TTL_N"      LOC = L22;
 NET "TTL/INV_TTL_N"      IOSTANDARD = "LVCMOS33";
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT:                   CMOS 3.3V input
##-------------------
NET "FPGA_RTMM0_N"       LOC = V21;
 NET "FPGA_RTMM0_N"       IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM1_N"       LOC = V22;
 NET "FPGA_RTMM1_N"       IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM2_N"       LOC = U22;
 NET "FPGA_RTMM2_N"       IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP0_N"       LOC = W22;
 NET "FPGA_RTMP0_N"       IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP1_N"       LOC = Y22;
 NET "FPGA_RTMP1_N"       IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP2_N"       LOC = Y21;
 NET "FPGA_RTMP2_N"       IOSTANDARD = "LVCMOS33";
##-------------------
##-- General purpose
##--
##-- + ACT:                   CMOS 3.3V input
##-------------------
NET "FPGA_HEADER_OUT_N1"    LOC = F15;
 NET "FPGA_HEADER_OUT_N1"    IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N2"    LOC = F16;
 NET "FPGA_HEADER_OUT_N2"    IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N3"    LOC = F17;
 NET "FPGA_HEADER_OUT_N3"    IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N4"    LOC = F14;
 NET "FPGA_HEADER_OUT_N4"    IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N5"    LOC = H14;
 NET "FPGA_HEADER_OUT_N5"    IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N6"    LOC = H13;
 NET "FPGA_HEADER_OUT_N6"    IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N1"     LOC = A17;
 NET "FPGA_HEADER_IN_N1"     IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N2"     LOC = A18;
 NET "FPGA_HEADER_IN_N2"     IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N3"     LOC = B18;
 NET "FPGA_HEADER_IN_N3"     IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N4"     LOC = A19;
 NET "FPGA_HEADER_IN_N4"     IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N5"     LOC = A20;
 NET "FPGA_HEADER_IN_N5"     IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N6"     LOC = B20;
 NET "FPGA_HEADER_IN_N6"     IOSTANDARD = "LVCMOS33";
