\subsection{Converter board registers}
\label{app:conv-regs}

Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name} 
		& \textbf{Description} \\
\hline
\endfirsthead
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name} 
		& \textbf{Description} \\
\hline
\endhead
\hline
\endfoot
0x0 & 0x54343538 & BIDR & Board ID Register\\
0x4 & (1)        & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & \textit{Reserved}  & Write as 0. Read undefined.\\
0x10 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x14 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x18 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x1c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x20 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x24 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x28 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x2c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x30 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x34 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x38 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x3c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x40 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x44 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x48 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x4c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x50 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x54 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x58 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x5c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x60 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x64 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x68 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x6c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x70 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x74 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x78 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x7c & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x80 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x84 & 0x00000000 & \textit{Reserved} & Write as 0. Read undefined.\\
0x88 & (2) & LSR & Line Status Register\\
0x8c & 0x00000000 & MSWR & Multicast Switch Register\\
\end{longtable}
}

\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.

\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.

\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}

\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline
\end{tabular}
}

\begin{itemize}
\item \begin{small}
{\bf 
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54343538
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}

\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
\hline
\end{tabular}
}

\begin{itemize}
\item \begin{small}
{\bf 
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\                     Rightmost nibble hex value is minor release decimal value \\		     e.g. \\		     0x11 -- v1.1 \\		     0x2e -- v2.14
\end{small}
\item \begin{small}
{\bf 
SWITCHES
} [\emph{read-only}]: Status of on-board general-purpose switches
\\
1 -- switch is ON \\		     0 -- switch is OFF
\end{small}
\item \begin{small}
{\bf 
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
\\
1 -- line active \\                     0 -- line inactive
\end{small}
\item \begin{small}
{\bf 
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\                     0 -- no timeout \\                     This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf 
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\                     0 -- idle \\                     This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}

\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - \\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
\hline
\end{tabular}
}

\begin{itemize}
\item \begin{small}
{\bf 
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\                     0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf 
RST
} [\emph{read/write}]: Reset bit
\\
1 -- initiate logic reset \\                     0 -- no reset
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}

\vspace{11pt}
\pagebreak
\subsubsection{LSR -- Line Status Register}
\label{app:conv-regs-lsr}

\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
\hline
\end{tabular}
}

\begin{itemize}
\item \begin{small}
{\bf 
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
\end{small}
\item \begin{small}
{\bf 
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
\end{small}
\item \begin{small}
{\bf 
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
\end{small}
\item \begin{small}
{\bf 
REARFS
} [\emph{read-only}]: Input failsafe state
\\
High if line is in failsafe mode (no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}

\pagebreak
\subsubsection{MSWR -- Multicast Switch Register}
\label{app:conv-regs-mwsr}

\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}SWITCHES[3:0]}\\
\hline
\end{tabular}
}

\begin{itemize}
\item \begin{small}
{\bf 
SWITCHES
} [\emph{read-only}]: Multicast address (from switch)
\\
1 -- switch is ON \\      0 -- switch is OFF
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
